Add IDE-R and KT device to chipset.cb and leave it off by default.
Change-Id: Iaa51e3dc107eb3f06ad7b2aad72a6bc112999d98
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This ACPI interface is required by e.g., the intel/common/pcie/rtd3
driver, which is used by some alderlake boards.
BUG=b:190080798
TEST=disassemble SSDT and find \_SB.PCI0.PMC.IPCS
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I59eae47e623587d35e394c9bff21481fcad2d6b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55172
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add common gpio functionalities across qualcomm soc targets.
This common gpio driver would allow the consumers to be able to
configure gpio function, set/get gpio direction as input/output,
configure the gpio as pull-up/pull-down, configure the gpio as an
IRQ and also query the gpio irq status.
The GPIO pin definition would be SoC specific.
BUG=b:182963902
TEST=Validated on qualcomm sc7180 and sc7280 development board
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Change-Id: Ia672130c6ca938d9284cae5071307637709480d1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55076
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds the ACPI hardware error source table (HEST) support.
This involves a few different parts: (1) The ACPI HEST table which is filled
with the appropriate fields (2) Reserved memory which is used by runtime
SW to provide error information. OS will not accept a HEST table with
this memory set to 0.
The ASL code to enable APEI bit will be submitted in a separate patch.
Tested on DeltaLake mainboard with following options enabled
SOC_INTEL_XEON_RAS
After boot to Linux, the following will show in dmesg:
HEST: Table parsing has been initialized
Change-Id: If76b2af153616182cc053ca878f30fe056e9c8bd
Signed-off-by: Rocky Phagura <rphagura@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52090
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
As per the comments in CB:54090 mainboard api
mainboard_tcss_get_port_info() is simplified and moved to tcss common
block code.
Signed-off-by: Deepti Deshatty <deepti.deshatty@intel.com>
Change-Id: I7894363df4862f7cfe733d93e6160677fb8a9e31
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54733
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
This patch adds support for loading SPM firmware from CBFS to SPM SRAM.
SPM needs its own firmware to enable SPM suspend/resume function which
turns off several resources such as DRAM/mainpll/26M clk when linux
system suspend.
TEST=program counter of SPM is correct value after booting up.
Change-Id: Ia0f9b9f86e44b293c1cc47213946304c64aea75e
Signed-off-by: Dawei Chien <dawei.chien@mediatek.com>
Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55140
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use currently global_lp4x_mem_parts.json.txt to regenerate SPD files for
LP4x memory parts that can be used with ADL-based mainboards.
BUG=b:186616388
Change-Id: I5e76a887f81d432adbcfc2f8956b44f4343db5c2
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54950
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Load SSPM firmware and boot up SSPM in ramstage.
This adds 23ms to the boot time.
TEST=Load SSPM blob ok, and we can see some logs of SSPM from AP.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ia227ea9f7d58129068cb36ec2de7d9feb677006b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55051
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Since the MCA(X) registers have defined values on the cold boot path,
the is_warm_reset check can be dropped. Also the warm reset bit in the
NCP_ERR register doesn't behave as the PPR [1] suggested; no matter if
something was written to the register or the machine went through a warm
reset cycle, the NCP_WARM_BOOT bit never got set.
[1] checked with PPR for AMD Family 17h Models 11h,18h B1 (RV,PCO)
#55570 Rev 3.15
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4e6df98ffd5d15ca204c9847a76c19c753726737
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55059
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The chipset devicetree only has the essential PCIe devices enabled that
are needed for the SoC code to work. It also defines aliases for all
PCIe devices that can be used to reference the devices in the mainboard-
specific devicetrees and devicetree overrides. To make the change easier
to review that part will be done in a follow-up patch.
Despite missing in the PPR, device pci 18.7 exists on Picasso.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6b7c3fd32579a23539594672593a243172c161c7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The Guybrush platform needs to set up some GPIOs immediately before the
FSP-M runs. Add a platform specific call. This will be used in a
follow-on commit.
BUG=b:184796302, b:184598323
TEST=Build
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I37d2625ff426347852e98a9a50f15368e0213449
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54638
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
PLTRST# is currently asserted and latched when eSPI_RST# gets asserted.
If eSPI_RST# isn't used on a platform or it doesn't properly assert
in all cases, then PLTRST# will never be asserted. This could result in
the AP and EC being out of sync.
BUG=b:188188172, b:188935533
TEST=Warm reset guybrush with partial #22 rework. Verify that peripheral
channel is correctly reset.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I20d12edf3efc6100096e24aa8d1aec76bbde264f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Update FADT table per relevant PM settings:
Fix PM Timer block access size and disable C2 and C3 states for the CPU.
Further on, set the century byte offset in FADT to point to the common location in CMOS.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I72a57bf8ec61c3eabc4522c2695ae4b16979f188
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54958
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Upload the FSP-M UPD configs. This CL also updated the chip.h and
devicetree.cb with the relevant variables and configs.
This CL also updated the GPIO related settings (PMC & SD card) in
devicetree.cb.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: If6321064b37535b390cf3dd7c41a719c598a0cd7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54892
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
On RW boot path psp_verstage call cbfs_map which calls chain of
_cbfs_alloc, cbfs_boot_lookup and cbfs_get_boot_device. Then
cbfs_get_boot_device initializes MCACHE which is used later.
However on RO boot path psp_verstage doesn't try to find anything in the
CBFS which results RO MCACHE not to be initialized. Add
cbfs_get_boot_device(true) to explicitly initialize MCACHE on recovery
boot.
BUG=b:177091575
BRANCH=none
TEST=build and boot jelboz
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I6c4b522fef5a4affd215faa122bdf6b53190cf3d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54711
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We were missing the stdint.h header, and the header was sorted
incorrectly in chip.h
BUG=non
TEST=build guybrush
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I209d3c9c48e5b06b2a56759af51cf2858eb99f51
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54922
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Since the default for the corresponding UPD of the Picasso FSP is
DXIO_PSPP_POWERSAVE and the devicetree default is DXIO_PSPP_PERFORMANCE,
add a deviectree setting for each board that's using the Picasso SoC
code to not change the setting for the existing boards.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0008ebb0c0f339ed3bdf24ab95a20aa83d5be2c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54934
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This allows boards to specify which PSPP policy (basically a dynamic
trade-off between power consumption and PCIe link speed) should be used
and also makes sure that the boards are using the expected PSPP policy
and not just the UPD default from the FSP binary that has already
changed once during the development.
BUG=b:188793754
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1b6459b2984711e72b79f5d4d90e04cb4b78d512
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54930
Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
TBT PowerResource _ON/_OFF methods are currently invoked by _PS0 and
_PS3 respectively. It is defined for ACPI driver to call _ON and _OFF
methods. This change drops the _PS0 and _PS3 call for _ON/_OFF and
returns TBT PowerResource declaration in the _PR0 and _PR3, then ACPI
driver will call the TBT PowerResource _ON and _OFF methods.
BUG=b:188891878
TEST=Traced both of TBT _ON and _OFF methods invocation and execution
at run time. Verified TBT's power_state to be D3Cold.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I398b3f58ec89f98673cbbe633149d31188ec3351
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54812
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This patch also adds the additional 10 MCAX registers to the BERT MSR
error record.
BUG=b:186038401
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I31912d3b3e77e905f64b6143042f5e7f73db7407
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52616
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This patch includes changes to update the soundwire master count.
Change-Id: Iffaf90569c19fb5ca3ce4775cc6dc6f8093f7c52
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54719
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
After Thunderbolt firmware is downloaded to IMR, its authentication
validity needs to be checked. This change implements the valid_tbt_auth
function. Thunderbolt DSD and its corresponding IMR_VAID will be
present to kernel only if its authentication is successful.
BUG=b:188695995
TEST=Validated TGL TBT firmware authentication and its IMR_VALID
into SSDT which is properly present to kernel.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I3c9dda341ae6f19a2a8c85f92edda3dfa08c917a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54693
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
After Thunderbolt firmware is downloaded to IMR, its authentication
validity needs to be checked. This change adds the TBT firmware IMR
status register offset and its authentication valid bit for
valid_tbt_auth function usage.
BUG=b:188695995
TEST=Built coreboot image successfully.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I742a00b6b58c45c1261f06b06a94346ad0a74829
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54888
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
After Thunderbolt firmware is downloaded to IMR, its authentication
validity needs to be checked. This change adds the TBT firmware IMR
status register offset and its authentication valid bit for
valid_tbt_auth function usage.
BUG=b:188695995
TEST=Built Voxel coreboot image successfully.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Ia25827f18a10bf4d2dcabfe81565ac326851af3e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54709
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The AMD FSP is using a new structure for USB and USB C phy settings.
This patch removes old, unused structures, adds the new one and
enables the devicetree interface for it.
Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com>
Change-Id: I011ca40a334e4fd26778ca7f18b653298b14019b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
1. Remove the extra UAB devices in xhci.asl
2. Update SD controller ADR in scs.asl
3. Remove the unused SCS PID
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I1906fb4e6893dc5e2b0bc8d85f4a7b2efc85c3a4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54867
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update SA & IGD DIDs table as per latest EDS (Doc no: 601458).
Add extra SKUs and fix the mismatched SKU numbers accordingly.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I62fd9e6a7cf0fc6f541f3d6d9edd31d41db7279f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
scan-build found a dead assignment, that the value stored to `res` is
never read. Use `pci_dev_read_resources()` instead, as done in
`sb/intel/common/smbus_ops.c` since commit 5f734327
(sb/intel/common/smbus_ops.c: Clean up read resources) avoiding the
assignment.
Change-Id: Ic59063b05a45dca411bf5b56c1abf3dd66ff0437
Found-by: scan-build (coreboot toolchain v0ad5fbd48d 2020-12-24 - clang version 11.0.0)
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54904
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Build of the entire smm-class is skipped if we have
HAVE_SMI_HANDLER=n.
Change-Id: I64bdcb28a996609111861ebafe172493b0650354
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54852
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Rocky Phagura
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
ESPI_SLAVE_CHANNEL_READY is a read-only bit from the host perspective.
It is set when the eSPI peripheral has configured the channel.
We actually want to set the ESPI_SLAVE_CHANNEL_ENABLE flag. This never
caused an issue before because the peripheral channel is enabled by
default after PLTRST# is deasserted. This does fix the case where
periph_ch_en == 0. It now properly clears the enable flag.
BUG=b:188188172, b:188935533
TEST=Boot guybrush to OS, perform warm reset
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I24e0734d5652601ae9c967da528fec5e3f780991
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54883
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The ChromeEC might take longer than 1ms for the peripheral channel to be
enabled. The PLTRST# interrupt handler takes about ~539us.
This doesn't account for the time it takes for the interrupt handler
to be scheduled. Increasing the timeout to 10ms gives ample time.
BUG=b:188188172, b:188935533
TEST=Boot guybrush and no longer see channel enable errors
Suggested-by: Rob Barnes <robbarnes@google.com>
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ib6db577bf06175ceb17b446af706ad8c9f891481
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54788
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The default of CBFS_MCACHE_SIZE is increased to 0x4000 in CB:54146 but
we have limited space on the PSP thus cannot afford it.
BUG=b:177091575
BRANCH=none
Signed-off-by: Kangheui Won <khwon@chrmoium.org>
Change-Id: I94dd782ae00d0b18ad6dd2fc061e4318bda88579
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54710
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This new definition is for MT53E512M32D1NP-046 WT:B used on Cret.
BUG=b:183057749
TEST=Generate SPDs
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: Ica5df61d96d2c4cbe62a560a53bd3bd08eb121f9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54746
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
NCP_ERR is a 1 byte register in I/O-space, so use inb and not inw. The
variable the result gets assigned to is also a uint8_t.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9fd8c139004111d6227c0316ba2a8b0281541654
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54736
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
