This is required for the HDA device to work.
Change-Id: I5fd3617c4cb1e69b7e0ecf6cddf4c143da99b927
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78201
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This adds support for the Librem 11 tablet, using the ME 13.50.15.1436
binary from the original BIOS (version 28.D8.E1.021) and FSP binaries
from a Jasper Lake Chromebook.
The following features were tested with PureOS:
* Audio (speakers, microphone, headset jack)
* Cameras
* Display
* Touchscreen and pen
* Keyboard cover, with tablet/laptop mode switch indicated via ACPI
* Power and volume buttons
* USB-C ports (USB 2/3, DP alt mode, PD charging)
* SD card reader
* WLAN
* Bluetooth
* NVMe SSD (socketed)
* Battery state information from EC
* Accelerometer
A UART is accessible with soldering via test points on the mainboard,
documented in the mainboard Kconfig with a toggle to enable it for
coreboot logging.
Change-Id: I545994889ddfb41f56de09b3a42840bccbd7c4aa
Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78343
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Based on schematics and confirm with EE to remove TOF function.
BUG=b:290891557
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: I1ae6a6562d87f8da5f41691a7606a1aa10989443
Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78147
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The next board revision of Librem 14 (v1-02) has replaced the ALC256
codec with ALC269. Add verbs for it.
Two GPIOs were changed from SMBus native functions to NC for this
revision. They are not used on either revision, change to NC.
Change-Id: I43b6265d2f502c05d5539ff3abf53ade0da6d706
Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78347
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
New Librem 14s have a newer CPU stepping, which changes them from CML
v1 to v2. The product is not significantly different and remains v1,
specifically "v1-02".
Select SOC_INTEL_COMETLAKE_1_2 to support all CPU steppings.
Change-Id: Iab37208b81e973714a2c088d2346eda518bf1214
Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78346
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Define SOC_INTEL_COMETLAKE_1_2, which creates a build supporting both
Comet Lake v1 and v2 by including both sets of FSP binaries and
selecting one based on the CPUID.
A mainboard can select this instead of SOC_INTEL_COMETLAKE_1 or ..._2
to support all CML-U steppings in one build.
Change-Id: Ic8bf444560fd6b57064c47faf038643fabde010e
Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78345
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
Support embedding a second FSP-M/FSP-S binary for an SoC that can
select one at runtime.
Comet Lake v1 and v2 are different steppings of the same SKUs, but they
require different FSP binaries. Supporting both in a single build
requires embedding both FSPs and selecting one at runtime based on the
CPUID. This is desirable for a product that may have different CPU
steppings but is not otherwise differentiated enough for a separate
firmware build.
An SoC can select PLATFORM_USES_SECOND_FSP to indicate that two FSP-M/
FSP-S binaries are required. Implement soc_select_fsp_m_cbfs() and
soc_select_fsp_s_cbfs() to choose one based on platform-specific
criteria. For Comet Lake, the first FSP is CML v1 and the second is
CML v2, but in principle a platform could define any meaning for the
first and second FSP.
FSP-T is not affected, only one FSP-T can be embedded if FSP_CAR is
used.
Only one set of FSP headers is used, which is sufficient for Comet Lake
v1/v2; their headers are equivalent.
ADD_FSP_BINARIES, FSP_USE_REPO, and FSP_FULL_FD are supported for both
sets of FSP-S/FSP-M but cannot be configured separately, both use the
same configuration.
Change-Id: Ied4c6c49a6bdf278238272edd47a2006258be8e5
Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78344
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
XFS is barely used. In order to save some space, drop it from the
package list.
Change-Id: Ic1cc567eb3f555bdf5567f3d036c84ce58691128
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78400
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Bump to 23.05 and also rename settings in order to compliant with newest
namespaces and names.
Change-Id: I4a23466bef5c45ebb82d92038ec2595103c984d3
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78399
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Within TBT PCIe, following register offsets have been updated for
production silicon. Update ASL with new offsets.
1. MPC - Miscellaneous Port Configuration Register
2. RPPGEN - Root Port Power Gating Enable
3. SMSCS - SMI/SCI Status Register
BUG=306026121
TEST= Check TBT PCIe Tunnel creation and device enumration.
Change-Id: I0497f7108ef5046c2694aece232263582514a0c5
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78163
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Commit bd9c562a9e ("acpi: Configure
slp-s0 residency counter frequency in LPIT table") led to jenkins
reporting the following error:
!!!!! Error: defined(CONFIG_ACPI_SOC_INTEL_SLP_S0_FREQ_HZ)
used at src/include/acpi/acpi.h:457. Symbols of type 'hex'
are always defined.
Since hex Kconfig are always defined there is no need to test it being
defined but also no need to handle zero or non-zero values.
In addition:
1. This config was defined in Meteor Lake specific Kconfig file while
it should actually be define closer to where it is being used (here
soc/intel/common/block/acpi/Kconfig) and only set by the SoC Kconfig.
2. Once moved and under control of `SOC_INTEL_COMMON_BLOCK_ACPI_LPIT'
gating (lpit.c), the Kconfig name needed to be adjusted to better fit
its use.
3. Make Meteor Lake Kconfig sets the config but does not define it
anymore.
TEST=LPIT ACPI table Counter Frequency field is set to 0x2005 on rex
Change-Id: I2083c9209e61be6180cca2c9f74097e2f4b4ce9a
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78458
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
The microcode for RPL-S C0 and H0 is actually available, however, the
name of the file contained a typo: 06-b7-05 vs 06-bf-05. Fix the typos
in the comments.
Moreover, the ADL-S C0/H0 microcode file 06-97-05 has the same sha256
sum as the equivalent RPL-S C0/H0 microcode file 06-bf-05. The sha256
sum of ADL-S/RPL-S C0/H0 microcode on intel-microcode tag
microcode-20230808:
5d8d4a4d5456c43b7cc04937c80aec094ccbf3bd89f34ffa5182913ef944a9f9
Update the comments to correctly indicate supported CPU steppings.
Change-Id: I4c848e0dfc40f6c8e26a9b31e7c4cf4c5a09128f
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78413
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The SCI handler for the GPE associated with the Super I/O did not clear
the respective PME status bits resulting in the SCI reoccurring
endlessly. The /proc/interrupts reported millions of ACPI interrupts
generated in just a few minutes of uptime. The flood of interrupts
caused some units to be unusable in extreme cases once attempted to
boot Qubes OS for example. On systems like Qubes OS it had a huge
impact on performance due to many IPCs the SCIs caused under Xen.
Clear the PME bits of devices that report a PME event. Then clear
the global PME status bit at the end of SCI handler to prevent the SCI
from asserting again until a new event occurrs. With this change
the number of ACPI interrupts generated in the first minutes of uptime
settles at a few thousands.
TEST=Boot Qubes OS R4.1.2 on Dell OptiPlex 9010 SFF and check
/proc/interrupts in dom0 if the number of ACPI interrupts is only
a few thousands.
Change-Id: I64e03d268138a62b46084be41343ef7fb089dfc3
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Remove the existing FSP 4221.00 headers subdirectory called
4221.00_google, and have Google vendor devices use FSP 4301.01.
BUG=b:306181828
TEST=`emerge-brya coreboot chromeos-bootimage`, flash and boot skolas to kernel.
Change-Id: Ic64b3aec62f0d6302278393bf06d090f43c0d592
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78444
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: <srinivas.kulkarni@intel.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Package C-state auto demotion feature allows hardware to determine lower
C-state as per platform policy. Since platform sets performance policy
to balanced from hardware, auto demotion can be disabled without
performance impact.
Also, disabling this feature results soc to enter below PC8 state and
additional power savings ~30mW in Local-Video-Playback scenario.
Change-Id: I6ff408280178a24686180f72f79522d2741607a1
Signed-off-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78278
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
System sleep time (SLP_S0 signal asserted) is measured in ticks, for
Meteor Lake soc in 122us (i.e. ~8197Hz) granularity/ticks.
Change-Id: I1e95cd69e941d4d72d5c36a07660ca07ee2499ba
Signed-off-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78277
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Intel platforms use Low Power Idle Table (LPIT) to enumerate platform
Low Power Idle states. There are two types of low power residencies
a) CPU PKG C10 - read via MSR (Function fixed hardware interface)
b) Platform Controller Hub (PCH) SLP_S0 - read via memory mapped
Ref. https://www.uefi.org/sites/default/files/resources/Intel_ACPI_Low_Power_S0_Idle.pdf
System sleep time (SLP_S0 signal asserted) is measured in ticks,
varies in every platform and based on PMC clock.
BUG=b:300440936
TEST=check kernel cpuidle sysfs for non-zero residency after s0ix cycle
and both must match
cat /sys/devices/system/cpu/cpuidle/low_power_idle_system_residency_us
cat /sys/kernel/debug/pmc_core/slp_s0_residency_usec
Change-Id: I401dd4a09a67d81a9ea3a56cd22f1a681e2a9349
Signed-off-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78164
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch ensures that the IGD joins the MBUS when the firmware splash
screen feature is enabled (aka BMP_LOGO config is enabled).
For ChromeOS platform, it prevents the i915 driver from reinitializing
the display, which can save up to 75ms-80ms of boot time and eliminate
a brief period of blank screen between the firmware splash screen and
the OS login prompt.
BUG=b:284799726
TEST=Able to build and boot google/rex.
Change-Id: I36af167afa902053a987602d494a8830ad9b1b1a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
This patch implements `.final` hooks for the IGD device to perform the
required operations before handing the control to the payload or OS.
The MBUS (Memory Bus) is a high-speed interface that connects the
graphics controller to the system memory. It provides a dedicated data
path for graphics data, which helps to improve graphics performance.
The MBUS is a key technology that helps to make the Intel i915 driver
powerful and versatile graphics drivers available. It provides the
high-speed data transfer capabilities that are essential for smooth
and responsive graphics performance.
Enable this config to ensure that the Intel GFX controller joins the
MBUS before the i915 driver is loaded. This is necessary to prevent
the i915 driver from re-initializing the display if the firmware has
already initialized it. Without this config, the i915 driver will
initialize the display to bring up the login screen although the
firmware has initialized the display using the GFX MMIO registers and
framebuffer.
Kernel graphics driver can avoid redundant display init by firmware,
which can optimize boot time by ~15ms-30ms.
Ensures hashing mode is 1x4 to enable a single pipe between Pipe A or B.
Typically, internal display is on Pipe-A, so 1x4 restricts MBUS joining
to internal display alone.
BUG=b:284799726
TEST=Able to build and boot google/rex
Change-Id: I60ae76dc783383e027e66edbcdeeb535472caeb1
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78385
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enabling support of WiFi SAR table for all rex variants by
setting the option at baseboard level.
BUG=b:290689824
TEST=emerge-rex coreboot
Change-Id: I17709cb5d75b56c6c1f386ab527c5c8730011bed
Signed-off-by: YH Lin <yueherngl@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78308
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
WiFi SAR table for karis will be place into the CBFS later on and
as a result adding the hook in coreboot to make use of the SAR
table once the table is available.
BUG=b:290689824
TEST=emerge-rex coreboot
Change-Id: Ic989024ab9eb0fc439fc701c335a85986c4cfec5
Signed-off-by: YH Lin <yueherngl@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78260
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update default fan settings(FAN_SETTING_1) in FAN field.
Bit 6-7, FAN, 0 --> FAN_SETTING_1
BUG=b:290689824, b:294155897
TEST=Dump ssdt table and check fan settings is existed
Change-Id: Id69ec67202b5d769cd3a9a68344a6d8913ebd78b
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78216
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Commit 9b230ae295 introduced a redefinition of the config option
`BOARD_GOOGLE_BROX`, which is already defined in Kconfig.name
accordingly and thus causing a Kconfig warning. Fix that by removing the
type redefinition.
Change-Id: Iea6219a686a23d8d48a0bfb6ac642efd482fded9
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78394
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Create the anraggar variant of the nissa reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:304920262
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_ANRAGGAR
Change-Id: I95e72188679fc825c94c4043ed02b0aad310c6a3
Signed-off-by: wuweimin <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78363
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
For Raptor Lake, select Raptor Lake's .fd file and header.
TEST=Boot to OS on Google Brya board with RPL silicon.
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: Ib3172b06b23e19be453142af764dd027bfe8043d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78014
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Disable SD card GPIO with fw_config for quandiso units without SD
card and pull GPP_H12 to high to match the spec.
BUG=b:296506936
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: Iad6789d42b9a3f9b979fd481a88cc7d69db2dcfe
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78253
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Shawn Ku <shawnku@google.com>
This script lists all new commits from users with few merged commits.
By default, it looks at the last week, and considers anyone with fewer
than 5 commits merged to be a new user.
Currently the only command line argument that's accepted is the gerrit
username of the person running the query. To modify any of the other
options, the values hard-coded into the script need to be updated.
To keep down the number of repeated queries, the script saves lists of
users considered to be experienced, as well as the commits from new
users that it lists.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ic698798f3fddc77900c8c4e6f8427991bda3f2d1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
This patch adds support for detecting dual displays (eDP and HDMI) on
Intel platforms. This information is useful for setting the
`lb_framebuffer.has_external_display` variable, which is used to
determine whether depthchage should avoid shutting down when an
extended display is present.
TEST= Able to build and boot google/rex, where depthchage now
successfully avoids shutting down when both eDP and HDMI displays
are attached.
w/o this patch:
with eDP and HDMI attached: .has_external_display=0
with eDP attached: .has_external_display=0
with HDMI attached: .has_external_display=1
w/ this patch:
with eDP and HDMI attached: .has_external_display = 1
with eDP attached: .has_external_display=0
with HDMI attached: .has_external_display=1
Change-Id: Ie39d48da75a21e3508a1fbcf09da31caedaa1c0a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78383
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iec6e05bbe9fad7d78002560b78169dc293294af6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78341
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
This code only gets built when the SOC selects
SOC_AMD_COMMON_BLOCK_DATA_FABRIC_EXTENDED_MMIO which no SoC before Genoa
does.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia5495ebf0f157fd0c456ce44acaf1ab222a188dd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78340
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Due to copy-paste error, the UART2 device name is the same as
UART1. Fix it.
Change-Id: I796d09f321101a36731a56099af738c9485df8a2
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Reserve SBREG BAR if it is outside of the PCH reserved memory range.
Desktop series processors have larger SBREG BARs, which, unlike mobile
processors, do not fall into the standard PCH reserved range
(0xfc800000 - 0xfe7fffff). Create a separate reservation for such a case. There is no telling what could happen if the reservation is not
made in ACPI.
TEST=Boot Windows 11 and Ubuntu 22.04 on MSI PRO Z690-A DDR4
Change-Id: Ibaf45daba37e3acfcea0e653df69fa5c2f480c4a
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77445
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
When battery level is below critical level or battery is not present,
cpus need to run with a power optimized configuration to avoid platform
instabilities. This will check the current battery status and configure
cpu power limits properly.
BUG=b:296952944
TEST=Build rex0 and check cpu power limits are configured with
a performance efficient configuration and the platform boots to OS if
battery level is above the critical level. And check cpu power limits
are configured with a power optimized configuration and boots to OS
without an issue if battery is not present or battery level is at or
below critical level.
Change-Id: I12fd40abda76c8e7522b06a5aee72665f32ddec8
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78322
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This adds is_battery_present_and_above_critical_threshold to check the
battery is present and the battery level is above critical level.
BUG=b:296952944
TEST=Build rex and check is_battery_present_and_above_critical_threshold
returns the correct battery status.
Change-Id: Ib38be55bc42559bab4f12d5e8580ddc3e1a6acc1
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78321
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This CL is just getting the initial brox framework to get the
baseboard building. Copied files from brask baseboard and tried to
remove contents of some files like the device tree and memory IDs.
Added support for memory part "MT62F512M32D2DR-031 WT:B", mapped to
DRAM ID 0.
BUG=b:300690448
BRANCH=None
TEST=./util/abuild/abuild -p none -t GOOGLE_BROX -x -a
Change-Id: I929b465646ac4c69d4bab33ce23848c7b1fa0f98
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78009
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
The board has three SATA controllers, so add the remaining two
on PCI device 18.0 and 19.0.
TEST=Verify in lspci the sata controllers.
Change-Id: Ia654c4ef895b52338554d89c25f61b262fbbcbbb
Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77892
Reviewed-by: Annie Chen <chen.annieet@inventec.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Systemagent related functions are not used in this file. Remove the
unused the header file.
Change-Id: Ifbb04898e9dcebef96d8c73771e66e0d6fabc7fb
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78312
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To support an RPL SKU on dochi, it must use the FSP for RPL.
Select SOC_INTEL_RAPTORLAKE for dochi so that it will use the RPL
FSP headers.
BUG=b:299570339
TEST=emerge-brya intel-rplfsp coreboot
coreboot-private-files-baseboard-brya
Change-Id: I51c28744bd9f21fae58bad38abb01d38965140a4
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78323
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Pull GPP_C1 to high in ramstage to meet touchscreen power sequence.
BUG=b:302236370
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot chromeos-bootimage
& test touchscreen function on quandiso DUT
Change-Id: Ia9f600ec0cc4be2d77ff08c0ae8951c90aec944f
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78264
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shawn Ku <shawnku@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
This reverts commit 5c35d30ffc.
Reason for revert: Here we need to confirm whether the issue in
mtl-staging-MTL.3323.92 has been improved in the QS sample
in the factory build.
BUG=b:287170545
TEST=Able to idle for more than 5+ hours without any hang.
Change-Id: I4517bbbefe11d95623d7e16a5e4bba2dd6f408e1
Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78320
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Mike Lee <mike5@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Confirmed with vendor, Elan touchscreen HID should set to "ELAN9004".
Correct Elan touchscreen HID to "ELAN9004" for karis.
BUG=b:294155897
TEST=Dump the SSDT on karis and check the HID had been modified.
Change-Id: I6ebb02540c894460388b9b9fe03f5c4031f8186d
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78266
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
The write to register 0x42 has no effect as at this point all
of the bits are read-only. Drop the line.
Change-Id: I7293e6eaa2d0bac5efe8316029bdecb04a5586e9
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78238
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Sean Rhodes