If IASL isn't installed, the genbuild script throws a confusing warning.
This can and should be ignored because toolchain.inc will find this and
provide a much better error message.
The trailing >/dev/null was probably intended to do this, but didn't
actually affect anything.
Adding quotes around the IASL command will make "" be the command that
tries to get run instead of `-v` when IASL isn't present. This will
always be a failure, whereas `-v` could theoretically be a valid
command.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ibff93db670766c4de21faa7553f2003450465407
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76857
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Similar situation happened last year when IoT FSP for ADL-S came out
before the Client FSP variant: https://github.com/intel/FSP/issues/83
It seems IoT FSP publishes the MemInfoHob.h file much later due to
legal reasons. Hack the missing file to get the builds using RPL-S IoT
FSP from repo working properly.
This change could be merged, subject for later revert (when the header
file is published).
Change-Id: Iec35db4573a3c3d011e4c1edf1c82a5c34438695
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76324
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
PchPcieClockGating and PchPciePowerGating UPDs are not yet available
in RPL-S IOT FSP. It also looks like those UPDs are not generally
available in all public RaptorLake FSP headers yet, so guard it
against SOC_INTEL_RAPTORLAKE to avoid build errors.
Change-Id: Iedac21bafa3428957e054fc8fefa38f9f776772d
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77337
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
This adds a Kconfig option to select memtest86+ version 6 as a secondary
payload and sets that as the default. The coreboot version 5 code may
still be selected and used if desired.
Compiling for 32 bit requires glibc from multilib installed, if the host
system is running on 64 bit, as header files, e.g. gnu/stubs-32.h, are
required from there. So introduce a new choice menu which allows to
choose between 32 and 64 bit.
By default, the stable 6.20 version is selected instead of the top of
the main branch.
TEST=Build both V5 and V6, boot them in QEMU
Signed-off-by: Martin Roth <gaumless@gmail.com>
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Change-Id: Ie0eedc25fcf37b925b072ca809c019a599a20392
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69277
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
The indentation resulted in the following error:
…/Documentation/soc/amd/psp_integration.md:22: ERROR: Unexpected indentation.
Alas, the line number refers to the embedded rst.
Change-Id: I9526d023af5207602c4a4cea7704b547ef1b7bf0
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77364
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
This binutils patch was pushed by the original author using the word
"loosing", which means "to release" instead of "losing", meaning to drop
or misplace.
I did not change the spelling of the commit message inside the patch so
that the patch can still be tracked easily, but wanted to fix the
mistaken spelling which appears when the patch is applied when building
the crossgcc toolchain.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I66fd596a79c9eb331f473d175180cf7bb5a38529
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77327
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
- Change delimiter characters to safe characters to keep the output
from getting mangled when imported into a spreadsheet.
- Change hyphens for statistics to asterisks for easier use in the
release notes.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I94f581d697f58cb29a662ac70ef9fd1d8c1e98ef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77332
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
- Print submodule updates the way we want it for the release.
- Change hyphens on stats to asterisks.
- Add asterisks before authors.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I23e39fa47fe418ee51fb957fcb5fc25b50950e38
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77331
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The -f|--fetch option is being added to download and verify the tarballs
without doing a build. This will be used specifically to archive the
toolchain tarballs for the release.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ia68dbdcbf2d0fa4bb433511dc5e2f980f6762204
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
We've had issues in the past where building with a sufficient number of
processors would expose a previously hidden timing issue in the build.
Those have frequently been in the path of a single chip or architecture,
so this adds a few different builds.
I'd like to have a representative sampling without increasing the build
time too much so maybe in the future, we can modify the clang build
targets to be different than the GCC targets.
These can be updated to different targets over time.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I51e39bc1ce6b9b7c257d0170ce3d2b5ab99d35df
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77329
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
The test-abuild target fails since the `scan-build` switch is missing a
dash. Fix it.
Change-Id: Iae10f639c43fed7709698e620e732cddce5658d8
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74240
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
scanbuild and ccache don't work together, so separate ccache from the
rest of the abuild options. All of the other tests get ccache, but
scanbuild never does.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: If057ed20c687ac8b501d20c6b4af91f8c0ab84b7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77326
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
When installing the python modules with pip3 as root, the installer
throws a lot of warnings about conflicts and recommends that it not
be run that way. This change installs the python modules as the
coreboot user instead. The --break-system-packages argument can now
be removed.
It takes along some other changes made to the coreboot home directory
which also don't need to be run as root, and now adds the .local/bin
directory into the path.
The trailing docker PATH configuration is discarded as cleanup - it
doesn't have any effect. Nothing uses it in the Dockerfile, and it
doesn't end up updating the path, which is set by /etc/profile.
Change-Id: Ie8273009bb527e267584bba84504191aa7294ca3
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76855
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The libfreetype6-dev has been a transitional package pointing at
libfreetype-dev for a while now. The libfreetype6-dev package is
currently out of date in debian sid, so it's a good time to switch
away from it.
TEST=Rebuild coreboot-sdk
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: If40e9eacf871d3840745ea18ec2ff5975cc62da7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77328
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Line is a duplicate, commented out. Drop it as it serves no purpose.
Change-Id: Id35bdea0915ca47cac4f38ede6ccbf2f2fb59f47
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77304
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Registering Clock Driver (RCD) is responsible for driving address and
control nets on RDIMM and LRDIMM applications. Its operation is
configurable by a set of Register Control Words (RCWs). There are two
ways of accessing RCWs: in-band on the memory channel as MRS commands
("MR7") or through I2C.
Access through I2C is generic, while MRS commands are passed to memory
controller registers in an implementation-specific way.
See JESD82-31 JEDEC standard for full details.
Change-Id: Ie4e6cfaeae16aba1853b33d527eddebadfbd3887
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
The default branch for the board-status repo was renamed to main, and
thus the -u option for board_status.sh no longer works as it tries to
push to master. Update the branch accordingly.
TEST: board_status.sh is able to upload results to review.coreboot.org
using the -u flag.
Change-Id: Ic90e95d8701e21c4ae30a7ac85560eebe7658d79
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77324
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
The EFER MSR is in the SMM save state and RSM properly restores it.
Returning to 32bit mode was only done so that fxsave was done in the
same mode as fxrstor, but this is no longer done.
See commit 1efca4d570 (cpu/x86/smm: Drop fxsave/fxrstor logic)
TESTED on qemu: the smihandler works fine.
Change-Id: Ie0e9584afd1f08f51ca57da5c4350042699f130d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68895
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Excluding the "recommended" packages reduces the size of the container
image from ~8.40GB to ~7.23GB.
Install the following packages in addition as they are useful for one or
the other case, or at some point even required:
* ca-certificates
* less
* neovim
* openssh-client
Change-Id: Ic38ba75765e3a0c21bbfe3f380880c9ac575d0d2
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76085
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
While Debian Sid provides GCC version 13, GNAT is still on version 12.
To keep them in sync, install GNAT 13 explicitly instead of the meta
package that is still referring to GNAT 12.
The coreboot toolchain including GNAT still compiles fine.
Change-Id: Ifb2b4c5fbaf3c0a8a78f6ebe244e2ccfec664b41
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
broadwell/pch/Kconfig is sourced if SOC_INTEL_BROADWELL is true. So
remove 'if SOC_INTEL_BROADWELL' condition and duplicated
'INTEL_LYNXPOINT_LP'
Change-Id: I9b5676fd232b47e9d5f89f7faffdfd5d2c76984e
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76699
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
While debugging lack of battery status under Windows, it was discovered
that the read/write flags in the args to the EC RAM 'ECRW' method were
not being correctly identified. Force set them from the R() and W()
methods which call ECRW() so those calls are processed properly.
TEST=build/boot Windows on google/drallion, verify battery status,
charging, etc are all reported properly.
Change-Id: I2a40b8d50ba65213813c781e53b56cc1a8b8debf
Signed-off-by: Coolstar <coolstarorganization@gmail.com>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72472
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
IOE_PMC support was not enabled on Meteor Lake platforms. This patch
adds the bare minimum hooks to initialize and allocate a memory region
for IOE operations. Additionally, this patch moves those IOE operations
to a newly included IOE-specific file, Previously, PMC was responsible
for these operations.
BUG=b:287419766
TEST=build and verified on google/rex.
Change-Id: I8bbc0b8a3e32dad5404c80bc7717ef07e3ec60b9
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77261
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
C1-state auto demotion feature allows hardware to determine C1-state
as per platform policy. Since platform sets performance policy to
balanced from hardware, auto demotion can be disabled without
performance impact.
Also, disabling this feature results soc to enter PC2 and lower
state in camera preview case and save platform power.
Note: C1 demotion heuristics used EPB parameter to balance between power
and performance, i.e. low threshold when EPB is low in-order to get C1
demotion faster and vice-versa. ChromeOS operates at default EPB=0x7
(low EPB) in both AC/DC, so in DC mode it gets more C1 demotion hits
than expected (similar to AC mode) and losing power respectively.
ref. https://review.coreboot.org/c/coreboot/+/76827
BUG=b:286328295
TEST=Code compiles and correct value of c1-state auto demotion is
passed to FSP. Also verified PC residency improvement ~10% in
camera preview case.
Change-Id: I1b2db634176f0072c535608c5600846a9086fef1
Signed-off-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Change-Id: Ic7d51037d527f95e8664ad04e328fc27901cacde
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71993
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Existing code did not include the HID over SPI for rex4es.
This CL corrects this issue.
BUG=None
TEST=Tested on Rex
Signed-off-by: Eran Mitrani <mitrani@google.com>
Change-Id: I02f7c4b68cfee2ebb202581c9f031af99ab4b6f9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77245
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Allow users of Alderlake N processors to use the microcode repository
and also add their related microcode blob to the list of microcodes
which should be included in the coreboot rom.
Change-Id: I11c9cb13fa81118bfcb819bad5fb39731c7e3e76
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Newer versions of Sphinx complain about the language being set to None,
so explicitly set it to 'en'. The syntax that is currently used to
enable custom CSS styling for tables [1] also no longer works, resulting
in the docs rendering without CSS. Fix this using the html_css_files
option instead.
TEST: The documentation builds and renders correctly with both Sphinx
1.8.3 in from the doc.coreboot.org Docker container and Sphinx 7.2.2
from distro packages.
[1] Commit a78e66e5f4: Documentation: Add static CSS file to fix tables
Change-Id: I036b1cad3cfa533c0c3a037bac649caa2d968d4b
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75466
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Fix the issue by adding the "ifeq" keyword which makes the extraneous
text a correct conditional directive.
Change-Id: Id8a8aa7acfdaeb0549f417fb013b2535a7298045
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77286
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Add data.vbt files for all variants supported by current brya, brask,
and nissa recovery images. Select INTEL_GMA_HAVE_VBT for all variants
which currently have a VBT file.
TEST=build/boot various brya variants (banshee, osiris, redrix)
Change-Id: Ic66f91e264d37c3742cb17994f637604d77a1576
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77144
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch removes unused CBMEM ID named
`CBMEM_ID_CSE_PARTITION_VERSION`.
BUG=b:285405031
TEST=Able to build and boot google/rex w/o any compilation error.
Change-Id: I83f53b7f64bdef62a8ee2061d5a9c9e22bc4b8a4
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77179
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch selects `SOC_INTEL_STORE_ISH_FW_VERSION` config to dump
the ISH version as part of the .final hook.
BUG=b:285405031
TEST=Able to build and boot google/rex_ec_ish. Verify the ISH version
is same as MFIT ISH version section.
> cbmem -c | grep "ISH"
[DEBUG] ISH version: 5.6.0.28821
Change-Id: I052af85ad836ab81ff6c510bb74e042b11940a65
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77178
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch implements `soc_is_ish_partition_enabled()` override to
uniquely identify the SKU type between ISH and non-ISH to conclude
if ISH partition is enabled and need to retrieve the ISH version from
CSE FPT by sending a HECI command.
BUG=b:285405031
TEST=Able to uniquely identify the ISH SKUs while booting
to google/rex_ec_ish to dump the ISH version.
Change-Id: I48358ad9e2e582e8b2274cbf4655de01f8792e6c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77177
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch uses the CSE firmware specific data to store Intel
ISH firmware related information. Sending an ISH partition version
information command on every boot cycle would impact the overall boot
performance.
This information is used by the auto-test framework to ensure the ISH
firmware update is proper for in-field devices.
BUG=b:285405031
TEST=Able to build and boot google/rex. Verified ISH FW version is
getting displayed across warm resets without impacting the boot time.
Change-Id: I0242c26dd90d834815799f54740d8147ff9d45b7
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This patch selects SOC_INTEL_STORE_CSE_FW_VERSION config by default
for CSE LITE SKU. It helps to dump the CSE RW firmware version which
further consumed by auto-test infrastructure to ensure CSE RW firmware
update is successful.
BUG=b:285405031
TEST=Able to build and boot google/rex.
Verified CSE RW FW version (for LITE SKU) is getting displayed without
impacting the boot time.
Change-Id: Iba5903c73c0a45b01e6473714e0d5f759c061825
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77175
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This patch introduces a CSE firmware specific data in order
to store Intel CSE and associated firmware related information which
requires a sync between Pre-RAM and Post-RAM phase.
This information will be used further to retrieve currently running
CSE RW firmware instead of fetching the version information by sending
a HECI cmd (which consumes 7ms-15ms depending upon the CSE operational
state).
Current implementation attempts to simply the CSE RW FW version store
and retrieval operations as below
* CSE sync in romstage (aka Pre-RAM) - Relying on .bss segment to store
the CSE info data in absence of real physical memory and sync back into
the CBMEM once available (after FSP-M exits).
* CSE sync in ramstage (aka Post-RAM) - Directly stored the CSE RW
version into the CBMEM (as CBMEM is online).
BUG=b:285405031
TEST=Able to build and boot google/rex. Verified CSE RW FW version
(for LITE SKU) is getting displayed without impacting the boot time.
w/o this patch:
10:start of ramstage 722,257 (43)
17:starting LZ4 decompress (ignore for x86) 723,777 (1,520)
w/ this patch:
10:start of ramstage 722,257 (43)
17:starting LZ4 decompress (ignore for x86) 723,777 (1,520)
Change-Id: Ia873af512851a682cf1fac0e128d842562a316ab
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77174
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Disable TPM support for CR50 TPM when using MrChromebox repo, since
it's not currently supported in edk2, and causes some boards (eg AMD
Zen-based) to failed to boot.
TEST=build/boot on google/frostflow
Change-Id: I64b5eb09d64eafd2bed400b7a7c97750cc368aed
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77270
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add Kconfig for passing a VBT file and GOP driver to edk2, and pass a
build param to use them along with the platform GOP driver. This allows
edk2 to initialize the display and change display modes, instead of
being limited to the single mode set by whatever display init method
coreboot might use (libgfxinit, FSP/GOP, VBIOS, etc).
TEST=build/boot multiple google boards spanning several platforms using
the edk2 GOP driver for display init.
Change-Id: I63a49df2411fe44b06eaee6d0fb9aab42ac8aedb
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77269
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
When cbfs_map()/cbfs_ro_map() fails, the caller may still want to know
the decompressed size of the CBFS file, for example, to print an error
message. Move the assignment earlier in the flow. Note that coreboot's
cbfs_map() is already doing the same.
BUG=none
TEST=emerge-geralt libpayload
BRANCH=none
Change-Id: I82c6b7e69c95bf597fa3c7d37dd11252893c01af
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77193
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Martin Roth