Commit Graph

50224 Commits

Author SHA1 Message Date
Elyes Haouas 7d67a19cfa util/amdfwtool/amdfwtool: Don't rewrite macros
Change-Id: Iea9dc65584c751e4d02524582b744ec9732e2c04
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-12 17:59:20 +00:00
Arthur Heymans b291dc8776 nb/intel/ironlake: Work around unused variable warning
It's not clear whether this variable should actually be used or not so
leave it be with a FIXME comment.

Change-Id: I4892600bfec55830acae56d2b293947c2d9ddd07
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69237
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-12 14:45:32 +00:00
Arthur Heymans e55aa0bc8f soc/intel/meteorlake: Fix set but unused variable
Clang complains about this.

Change-Id: Ibe1de3057c17b4aa8ecbd87fac598e43294584e3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66264
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-12 14:45:22 +00:00
Arthur Heymans d4dfc21f70 cpu/x86: Set thread local storage in C code
Doing this in C code is way easier to understand. Also the thread local
storage is now in .bss instead of the AP stack. This makes it more
robust against stack overflows, as APs stacks overflow in each other.

TESTED: work on qemu.

Change-Id: I19d3285daf97798a2d28408b5601ad991e29e718
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69435
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-12 14:23:51 +00:00
Arthur Heymans 407e00dca0 include/cpu/msr.h: transform into an union
This makes it easier to get the content of an msr into a full 64bit
variable.

Change-Id: I1b026cd3807fd68d805051a74b3d31fcde1c5626
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68572
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-12 14:23:35 +00:00
Arthur Heymans 0c9fa6f2ce mb/emulation/qemu-q35: Fix running qemu-i386 with SMM
Depending on whether qemu emulates an amd64 or i386 machine the SMM
save state will differ. The smbase offsets are incompatible between
those save states.

TESTED: Both qemu-system-i386 and qemu-system-x86_64 (v7.0.50) have a
working smihandler, ASEG and TSEG.

Change-Id: Ic6994c8d6e10fd06655129dbd801f1f9d5fd639f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55138
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-12 10:27:09 +00:00
Arthur Heymans 4c4bd3cd97 soc/intel/broadwell: Hook up PCI domain and CPU cluster ops to devicetree
Change-Id: I77a333827552741453d8b575f2a8009b3e1bf8f1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69301
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-12 08:56:18 +00:00
Kyösti Mälkki bd72bfece2 cpu/intel/socket_mPGA604: Drop non-working SSE2 disablement
The disablement of SSE2 was not honoured since there is explicit
select under CPU_INTEL_MODEL_F2X. The removed commentary originates
probably from ROMCC romstage implementation.

Change-Id: I7d9ac007406a82c498f3ed23568e2ff064504983
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69443
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-12 05:09:21 +00:00
Kevin Chiu 8e275af3ee mb/google/brya/var/gladios: Add GL9750 SD card reader support
BUG=b:239513596
TEST=emerge-brask coreboot

Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Change-Id: I7411e10348c36786000c6918b9b154b7329f3cd0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69436
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-12 03:34:58 +00:00
Kevin Chiu 02d4116fd6 mb/google/brya/var/gladios: Include GL9763E driver for eMMC support
Support GL9763E as a eMMC boot disk.

BUG=b:239513596
TEST=emerge-brask coreboot

Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Change-Id: I2b29309615df381f1e24f29fc048c6f9bf216b7f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69425
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-12 03:34:33 +00:00
Elyes Haouas 357c229173 sb/intel/i82801dx: Clean up includes
Change-Id: Ib8bfafe9b359856ccfb11a70ab5a6c1ffd453c54
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69440
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-11-12 03:33:14 +00:00
Michael Niewöhner 3504918b43 mb/clevo/l140mu: make use of the new clevo/it5570e ec driver
Hook up the new EC driver.

Tested:
 - Fn hotkeys work (brightness, display, volume, tp toggle, ...)
 - Display lid
 - Sleep/wake
 - Camera (including Fn toggle)
 - Bluetooth (both CNVi and PCIe card)
 - Wi-Fi (both CNVi and PCIe card)
 - CMOS options

Known issues:
 - Touchpad toggle needs OS setup; see CB:68791
 - UCSI is not implemented; see CB:68791

Change-Id: I6c4637936761cd62571b5d19fe2afd65560f49a0
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59850
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-11 22:43:28 +00:00
Michael Niewöhner dc3e7def5f mb/clevo/l140cu: make use of the new clevo/it5570e ec driver
Hook up the new EC driver.

Tested:
 - Fn hotkeys work (brightness, display, volume, tp toggle, ...)
 - Display lid
 - Sleep/wake
 - Camera (including Fn toggle)
 - Bluetooth (both CNVi and PCIe card)
 - Wi-Fi (both CNVi and PCIe card)
 - CMOS options

Known issues:
 - Touchpad toggle needs OS setup; see CB:68791
 - UCSI is not implemented; see CB:68791

Change-Id: I28ac401ada2945bb58fe862895458b10fed505fe
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68795
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-11 22:43:14 +00:00
Michael Niewöhner d6ac7a9a3a mb/clevo/l140cu: drop System76 EC
Drop System76 EC, since the ODM board does not use it. Clevo EC FW
support will be added and hooked up cleanly in the follow-up changes.

Change-Id: I06abbde238be6d25842472a6a82159413ab52ef5
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59816
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-11 22:43:01 +00:00
Michael Niewöhner e1e65cb0f1 ec/clevo/it5570e: add driver for EC used on various Clevo laptops
This adds a driver for the ITE IT5570E EC in combination with Clevo
vendor EC firmware. The interface is mostly identical on various laptop
models. Thus, we have implemented one common driver to support them all.

The following features were implemented:
 - Basics like battery, ac, etc.
 - Suspend/hibernate support: S0ix, S3*, S4/S5
 - Save/restore of keyboard backlight level during S0ix without the need
   for Clevo vendor software (ControlCenter)
 - Flexicharger
 - Fn keys (backlight, volume, airplane etc.)
 - Various configuration options via Kconfig / CMOS options

* Note: S3 support works at least on L140CU (Cometlake), but it's not
        enabled for this board because S0ix is used.

Not implemented, yet:
 - Type-C UCSI: the EC firmware seems to be buggy (with vendor fw, too)
 - dGPU support is WIP

An example of how this driver can be hooked up by a board can be seen in
in change CB:59850, where support for the L140MU is added.

Known issues:

 - Touchpad toggle:
   The touchpad toggle (Fn-F1) has two modes, Ctrl-Alt-F9 mode and
   keycodes 0xf7/0xf8 mode. Ctrl-Alt-F9 is the native touchpad toggle
   shortcut on Windows. On Linux this would switch to virtual console 9,
   if enabled.  Thus, one should use the keycodes mode and add udev
   rules as specified in [1]. If VT9 is disabled, Ctrl-Alt-F9 mode could
   be used to set up a keyboard shortcut command toggling the touchpad.

 - Multi-fan systems
   The Clevo NV41MZ (w/o dGPU) has two fans that should be in-sync.
   However, the second fan does not spin. This needs further
   investigation.

[1] https://docs.dasharo.com/variants/clevo_nv41/post_install/

Testing the various functionalities of this EC driver was done in the
changes hooking up this driver for the boards.

Change-Id: Ic8c0bee9002ad9edcd10c83b775fc723744caaa0
Co-authored-by: Michał Kopeć <michal.kopec@3mdeb.com>
Co-authored-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Co-authored-by: Michael Niewöhner <foss@mniewoehner.de>
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-11 22:42:46 +00:00
Sean Rhodes 064c6ced40 ec/starlabs/merlin: Rename the Cezanne EC code
This EC code is for the Byte, a Cezanne Mini PC. The EC is different
to the Cezanne StarBook Mk VI. Rename it to `-desktop`, so the laptop
variant becomes the primary.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I25f812cb1c6cefca1ebbe3bee5d20cf521dd60af
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68319
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-11 18:24:45 +00:00
Felix Held 9405dd066e drivers/intel/fsp2_0/hand_off_block: remove unneeded line breaks
Since the characters per line limit was increased from 80 to 96, some
line breaks can be removed to improve code readability.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I92aa3fec8c8caba143e418efc999ec4a7c5d93c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69461
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-11 18:02:37 +00:00
Felix Held dafc6194a0 soc/amd/root_complex: don't skip reporting IOAPIC resource in !hob case
When no HOB list is found, not only adding the resources reported by the
FSP were skipped, but also adding the GNB IOAPIC resource was skipped.
Fix this bug by moving the reporting of the GNB IOAPIC resource before
the resources reported in the FSP HOBs to not skip the IOAPIC resource
when there's no HOB list.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9174c8d7e5e94144187d27210e12f2dca3a6010f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69460
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-11 17:45:18 +00:00
Kevin Chiu 88cf831ed1 mb/google/brya/var/gladios: use i2c1 for TPM support
This change sets DRIVER_TPM_I2C_BUS to the i2c 1 bus for TPM for the
gladios variant.

BUG=b:239513596
TEST=emerge-brask coreboot

Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Change-Id: Id6f2bf2a79df883bcb70171051cec4c577ca3bc4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69424
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-11-11 16:04:58 +00:00
Nicholas Chin 81827aad3c drivers/usb/gadget.c: Add support for EHCI debug using the WCH CH347
The WCH CH347 presents a USB CDC serial port on interface 4 while in
operating modes 0, 1, and 3. Mode 0 also presents a UART on interface
2 but this is ignored for compatibility with the other modes. Mode 2
uses vendor defined HID usages for communication and is not currently
supported. Like the FT232H the data format is hard coded to 8n1.

Tested using a CH347 breakout board and a Dell Latitude E6400.

Change-Id: Ibd4ad17b7369948003fff7e825b46fe852bc7eb9
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68264
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-11-11 13:33:34 +00:00
Kyösti Mälkki 458751c2d5 aopen/dxplplusu: Add early GPIO settings
Required for 2nd COM port to work.

Change-Id: Ib211e9c4b487fadec3d3487f9d745f44d8ca4579
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52815
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-11 12:42:34 +00:00
Arthur Heymans a83c502d5a util/amdfwtool: Add more instances some types in BDT
Some hardware uses more instances.

Change-Id: Ie4ed2ce0d077013b450df99a88e904c8658cfc2d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68121
Reviewed-by: Marvin Drees <marvin.drees@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-11 00:41:54 +00:00
Arthur Heymans 1f05c8044e util/amdfwtool: Add new types
These are used on newer platforms.

Change-Id: I20dc77fb6f83dc813e3da5fe30f8f52068fc4662
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68119
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-11-11 00:40:22 +00:00
Martin Roth e440403683 vc/amd/fsp/mendocino: Update FSP UPD signatures to MNDCNO
The FSPM and FSPS UPD signatures hadn't been updated from their cezanne
origins.  Change them to MNDCNO_M/S.

BUG=b:240573135
TEST=Build & boot, see new signature in boot log.

Change-Id: I9e4fcf7a9bf802aaba88f3dccf6da064c5686e96
Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66604
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2022-11-11 00:39:20 +00:00
Jonathan Zhang d5d9b280de acpi/acpi.c: Fix einj generation pointer arithmetics
Without a cast the aritmetics of

tat = einj + sizeof(acpi_einj_smi_t)

is the same as

tat = (uintptr_t)einj + size(acpi_einj_smi_t) * size(acpi_einj_smi_t)

So it overshoots the intended offset by a lot.

This issue only came apparent because now einj is in the small IMD
region which is close to TSEG. With the wrong aritmetics the tat
pointer ended up inside TSEG which is not accessible from the OS
causing exceptions.

TEST: observe that tat pointer is inside the small IMD below
TSEG (0x78000000 on our setup).
"acpi_create_einj trigger_action_table = 0x77ffe89c"

Change-Id: I3ab64b95c33eef01b2048816a21e17855bcb2f54
Signed-off-by: Arthur Heymans <arthur.heymans@9elements.com>
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69326
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2022-11-11 00:36:40 +00:00
Elyes Haouas aba1c945cd /: Remove "ERROR: "/"WARNING: " prefixes from log messages
It is no longer necessary to explicitly add "ERROR: "/"WARNING: " in
front of every BIOS_ERR/BIOS_WARN message.

Change-Id: I22ee6ae15c3d3a848853c5460b3b3c1795adf2f5
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-10 21:31:18 +00:00
Kyösti Mälkki 1d3c2e6572 arch/x86/ioapic: Reduce API exposure
Change-Id: I6ff18e5ede0feda65f81c064394febd3eebc5247
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55316
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-10 19:21:44 +00:00
Kyösti Mälkki 71c6487cf1 sb/intel/i82870: Use register_new_ioapic()
Commentary about mixing LAPIC IDs and IOAPIC IDs was wrong,
remove it. The only platform affected is aopen/dxplplusu with
i82801dx southbridge.

Change-Id: I1276a2050cabaaf07f740c2490d92c48bd5801fa
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58407
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-10 19:19:23 +00:00
Kyösti Mälkki d165357ec3 sb,soc/intel: Use register_new_ioapic_gsi0()
Change-Id: I6b0e4021595fb160ae3bf798468f4505b460266f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55314
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-10 19:10:42 +00:00
Kyösti Mälkki c0457358f6 sb,soc/intel: Use acpi_create_madt_ioapic_from_hw()
Change-Id: I9fd9cf230ce21674d1c24b40f310e5558e65be25
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55311
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-10 19:09:34 +00:00
Kyösti Mälkki 0ea8f89e40 arch/x86: Add register_new_ioapic()
Using this I/O APIC IDs will be assigned incrementally
in the order of calling. I/O APIC ID #0 is reserved for
the I/O APIC delivering GSI #0.

Change-Id: I6493dc3b4fa542e81f80bb0355eac6dad30b93ec
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55313
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-10 19:08:57 +00:00
Kyösti Mälkki c7da027e75 ACPI: Add acpi_create_madt_ioapic_from_hw()
Read I/O APIC ID and vector counts from hardware.

Change-Id: Ia173582eaad305000f958c5d207e9efaa06d8750
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55310
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-10 19:08:22 +00:00
JingleHsuWiwynn 014901bd9b soc/intel/xeon_sp: Move SMBIOS type 4 override functions from mainboard
to soc

Move SMBIOS type 4 override functions from mainboard to soc so that all
xeon family cpus share same functions without implementing again.

Tested=On OCP Deltalake, dmidecode -t 4 shows expected info.

Signed-off-by: JingleHsuWiwynn <jingle_hsu@wiwynn.com>
Change-Id: I17df8de67bc2f5e89ea04da36efb2480a7e73174
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69363
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-11-10 19:06:41 +00:00
Tim Chu 323e5a84eb src/include/smbios: Add definition for smbios type 4 and type 9
Add definition for smbios type 4 and type 9

Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: I559995b0204f8e5bdeef2c0f8b394f9011d72240
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-11-10 19:05:51 +00:00
Jan Dabros 3709186b2b mb/google/skyrim: Enable SOC_AMD_COMMON_BLOCK_I2C3_TPM_SHARED_WITH_PSP
Skyrim platforms have I2C3 controller which is shared between PSP and
X86. In order to enable cooperation, PSP acts as an arbitrator. Enable
SOC_AMD_COMMON_BLOCK_I2C3_TPM_SHARED_WITH_PSP, so that proper driver is
binded on the OS side.

BUG=b:241878652
BRANCH=none
TEST=Build kernel and firmware. Run on skyrim and verify TPM
     functionality.

Signed-off-by: Jan Dabros <jsd@semihalf.com>
Change-Id: I2a3de8cb2b9241e2d81e02df49f317ac0408d5bb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-11-10 18:56:23 +00:00
Venkat Thogaru 38ea9e3ef4 mb/google/herobrine: Update comment of modem status info
Updated comment as per guidelines.

BUG=b:232302324
TEST=none

Signed-off-by: Venkat Thogaru <quic_thogaru@quicinc.com>
Change-Id: I6a925477a926e7e9d54e42d662768536318ec8e0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69296
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
2022-11-10 17:28:05 +00:00
Kacper Stojek 76d2b6699d util/inteltool: Add support for Elkhart lake
Document: 614109, 601458
Tested on: Protectli vault_ehl (VP2420)

Signed-off-by: Kacper Stojek <kacper.stojek@3mdeb.com>
Change-Id: I54948741082ca1072642046f64539a4c15ddb578
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68474
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2022-11-10 16:24:49 +00:00
Fred Reitberger c989d3cd10 mb/amd/chausie/ec.c: Enable WLAN
Enable WLAN power and deassert the various radio disables.

TEST=boot chausie

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I2d21905001fa776c0d5c864d83dcd697e3febe0a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2022-11-10 15:52:36 +00:00
Fred Reitberger fdfd63be3a mb/amd/chausie: Correct naming of EC FW
Change the EC FW CBFS filename prefix to a more accurate "ec/"

TEST=build and boot chausie

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Ib9ee24ca06b29c74cc0a91f9e4789df00ba1ba53
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69276
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2022-11-10 15:52:04 +00:00
Frank Chu 369dee5938 mb/google/brya/var/marasov: use RPL FSP headers
To support an RPL SKU on marasov, marasov must use the FSP for RPL.

Select SOC_INTEL_RAPTORLAKE for marasov so that it will use the RPL
FSP headers for marasov.

BUG=b:254365935
BRANCH=None
TEST=FW_NAME=marasov emerge-brya intel-rplfsp
coreboot-private-files-baseboard-brya coreboot chromeos-bootimage

Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: I7874420c0fb51b9cc616cd979ffc9349c381602e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69367
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-11-10 15:50:46 +00:00
Frank Chu ad00d847f2 mb/google/brya/var/marasov: Generate SPD ID for supported memory parts
Add supported memory parts in mem_parts_used list, and generate SPD ID
for these parts.

DRAM Part Name                 ID to assign
MT62F512M32D2DR-031 WT:B	0 (0000)
H9JCNNNBK3MLYR-N6E		1 (0001)
MT62F1G32D4DR-031 WT:B		4 (0100)
H9JCNNNCP3MLYR-N6E		5 (0101)

BUG=b:254365935
BRANCH=None
TEST=run part_id_gen to generate SPD id

Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: Ifa0637b47d0017cdb9e26ed32328f4405c0df3f7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69311
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-11-10 15:50:04 +00:00
Frank Chu 8d4cb09048 mb/google/brya/var/marasov: Update devicetree setting for marasov
update devicetree setting per the schematic

BUG=b:254365935
BRANCH=None
TEST=Built successfully

Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: Ifa4cb18b8e1a7b162f505ff12612ef808fb7061a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69364
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-10 15:49:37 +00:00
Arthur Heymans 961e09c631 soc/nvidia/tegra124: Fix building with clang
This kind of allocation without '=' is not working with clang.

Change-Id: I2d3e9eb44c3e0e25e5a67c5386e5ddde1487cc74
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63063
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-10 15:33:32 +00:00
Arthur Heymans 1b2c03b9d8 soc/sifive/ux00ddr.h: Remove set but unused variables
It looks like this code was not finished so it's left commented out
for now.

Change-Id: I442a42e297f2968dd2c824a93a9a1e2bc74ea2f4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63074
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-10 15:32:33 +00:00
Ritul Guru f3e4cec919 drivers/spi: Add support for Macronix SPI ROM MX77U25650F
Change-Id: I8fedea1d566f0c35a9e028d4b2bb939592bd5f74
Signed-off-by: Ritul Guru <ritul.bits@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69381
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-11-10 15:14:26 +00:00
Caveh Jalali 21552aee3f ec/google/chromeec: Fix USB_PD_PORTS response data type
The EC_CMD_USB_PD_PORTS host command returns a
struct ec_response_usb_pd_ports, not a
struct ec_response_charge_port_count.

Luckily, both structs have the same memory layout, so this is simply a
name change.

BUG=b:258126464
BRANCH=none
TEST=none

Change-Id: I0d7710ca8a45f0ea3939f58bbba6bab31ff41919
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69370
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-10 15:10:25 +00:00
Caveh Jalali 2320c03087 ec/google/chromeec: Simplify KEYBOARD_BACKLIGHT error handling
Simplify the implementation of setting the keyboard backlight PWM
value. Host command stubs typcially don't need to examine the host
command's return value as stored in cmd_code because that level of
detail is not very interesting. Higher value error codes are returned in
actual result structures.

This host command can return EC_RES_ERROR for out of range PWM values
which is already a generic error and unlikely to happen since we already
limit the range to 0..100 here. Finally, none of the callers in coreboot
check the return value.

BUG=b:258126464
BRANCH=none
TEST=none

Change-Id: If17bc4e31baba02ba2f7ae8e7a5cbec7f97688c5
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69369
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-10 15:09:48 +00:00
Caveh Jalali b456a96361 ec/google/chromeec: Fix keyboard_backlight call
The EC_CMD_PWM_SET_KEYBOARD_BACKLIGHT command does not return data, so
don't specify a result buffer.

BUG=b:258126464
BRANCH=none
TEST=none

Change-Id: I5b9a0d228e187a9337498246a3b9ed8db07b95c7
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69368
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
2022-11-10 15:08:05 +00:00
Rob Barnes a3148ca504 google/chromeec: Add ACPI method for EC Panic
Add an ACPI method to handle EC_HOST_EVENT_PANIC (bit 24) events.

EC panic is not covered by the standard (0-F) ACPI notify values.
Arbitrarily choosing B0 notify, which is in the 84-BF device specific
ACPI notify range.

This will be a no-op until the kernel driver is also updated to handle
this event.

BUG=b:258195448
BRANCH=None
TEST=Observe event with modified cros_ec_lpc driver

Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: Iafa642c1c50f9a0083a8e618e1eabec9a7ce39b4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69391
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-10 15:07:09 +00:00
Martin Roth 2204cee6e9 configs: Build test STB features on google skyrim
- Update the google_skyrim.with_binaries to test printing the STB
entries.
- Add a new saved config to test building without video, building
using an x86 verstage, and STB_SPILL_TO_DRAM

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Idddcf2441b91b79575e5dfed1cc56d207234205b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68928
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
2022-11-10 12:51:15 +00:00