Moved a lot of code from i915io.c to intel_dp.c with specific function calls
Change-Id: Ib2ed52b4f73ee0076e2dd68a26541e5bbe1366bc
Reviewed-on: https://gerrit.chromium.org/gerrit/63950
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/4429
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Depending upon the values decoded from edid, the function decides the appropriate bits to
be set in flags parameter (Important for fastboot to work correctly in kernel)
Change-Id: I3b0f914dc2b0fd887eb6a1f706f87b87c86ff856
Reviewed-on: https://gerrit.chromium.org/gerrit/64265
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/4423
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Also, used this attribute in the calculation of htotal and other registers
Added intel_dp_* functions for m,n registers and dimension register calculations
Change-Id: I99dd7156700d59b0b4c85e34c9aa1c6408c7f31a
Reviewed-on: https://gerrit.chromium.org/gerrit/64001
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/4422
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Works fine with all three panels with the change of 6 bits per color.
Change-Id: Ia47d152e62d1879150d8cf9a6657b62007ef5c0e
Reviewed-on: https://gerrit.chromium.org/gerrit/63762
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/4402
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Despite calling romstage memory CAR in this case, the variables actually
do live in SRAM on the Exynos CPUs. However, in order to share as much
generic code as possible, we're using the same infrastructure here.
Change-Id: I85173c37099a25f3e55980e88120401826cdf29c
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/62188
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
Tested-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: http://review.coreboot.org/4394
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Empirical testing shows that 0x5 is the optimal setting for DTLE DATA /
EDGE on Peppy.
Change-Id: I273a3a68be97b3eb7c2ee2071e5de1ef7bf7f2d9
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/65717
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/4476
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Allow DTLE DATA / EDGE registers to be configured in board-specific
devicetree.
Change-Id: I82307d08c9cf73461db3ac7fb875a4fe70d6f9ea
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/65716
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/4475
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Some mainboards will need to have this set.
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Change-Id: I4732a9af822a60b5050d03d2ac4bb7cbd6c723d0
Reviewed-on: https://gerrit.chromium.org/gerrit/65722
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Stefan Reinauer <reinauer@google.com>
Commit-Queue: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/4474
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This is causing hangs in depthcharge (again?) so for now
turn that port off so the resulting coreboot images are
at least useful.
Change-Id: I32c7774a95b0020b97105e0fa42c21ccb617c718
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/65615
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4467
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
The SMI handler code was setting S3 wake events when going
into S5 and enabling a key press to wake the system.
Change-Id: I6413ef1341e0149187df9f4f7e0c314d4c9e9c6e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/65323
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4459
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
If the firwmare is flashed and the MRC cache is blown away
then it is not possible to resume.
Right now this can be inferred from the event log but it can
be made very clear by adding a unique post code for this event.
1) boot falco
2) flash firmware
3) suspend and then resume
4) check for post code 0xef in log
0 | 2013-08-08 16:27:47 | Log area cleared | 4096
1 | 2013-08-08 16:27:47 | ACPI Enter | S3
2 | 2013-08-08 16:27:55 | System boot | 48
3 | 2013-08-08 16:27:55 | Last post code in previous boot | 0xef | Resume Failure
4 | 2013-08-08 16:27:55 | System Reset
5 | 2013-08-08 16:27:55 | ACPI Wake | S5
Change-Id: I7602d9eef85d3b764781990249ae32b84fe84134
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/65259
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4458
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
These can typically be set in the devicetree but we need a way to
override those values with a Kconfig setting so as not to expose
the Vendor ID before the product has launched.
Change-Id: Ib382e6d9359d24b128c693a657ffde52604efad3
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/65310
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4455
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Boot on falco and look in /sys/firmware/log for
the string "PCIe Root Port 1 ASPM is enabled"
Change-Id: Ie2111e4bb70411aa697dc63c0c11f13fbe66c8d8
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/65315
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4454
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
The PCIe root port has ASPM settings/workarounds that are only applied
based on the value of an undocumented bit in PCI config register 0x32C.
If that bit is not set for some reason then the settings are not applied.
This devicetree config option will force the ASPM settings for each port
based on the bit map.
Change-Id: I40b08ca9a0ef52742609bac72fb821454a373799
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/65314
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4453
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
The default ME output is quite verbose and not all that useful
unless you are actively debugging the ME and then you can enable
the CONFIG_DEBUG_INTEL_ME option.
This commit silences the firmware capabilities and the MBP output.
Change-Id: I2b8abcb34ae0d00d9a38d029979e84ee0d0ca287
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/65252
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4452
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
CLKOUT for PCIE ports 1-5 and CLKOUT_XDP are not used
and can be disabled.
I couldn't test this directly without a scope so instead I
used a modified commit that also disabled PCIe Port 0 and
saw that that correctly disabled the WLAN port.
Change-Id: I0f996e90f0ae42780de3a0c8dc5db00ec600748b
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/65251
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4451
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This message allows unused clocks to be disabled based on a
devicetree setting in each mainboard.
Change-Id: Ib1988cab3748490cf24028752562c64ccbce2054
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/65250
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4450
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
The original ME code was assuming that the only type of messages
it would send were MKHI type and so it had some embedded checks
for that header and that type of message.
In order to support ICC messages this needs to change to handle
different header types, so now the header will be sent first
and then the data will follow, rather than the two both being
sent in the same low-level function.
This change has no real affect on the system, subsequent commit
will add new ICC messages.
Change-Id: I52848581e49b88c0a79e8bb6bda2a179419808a3
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/65249
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4449
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
When the EC requests the host to throttle (for charging or thermal
related reasons) the package power consumption will be limited.
Right now this is set at 12W but that is somewhat arbitrary and may
need tuning.
1) define the THRT method in \_TZ scope for EC to call
2) enable SCI events for throttle start and stop
3) define the power limit at 12W and set it in NVS
1) Enable CONFIG_ACPI_DEBUG=y in the kernel
2) Enable the Debug object event in acpi module
acpi.debug_layer=0x7f acpi.debug_level=0x2f
3) Using EC console generate host event for throttle start
> hostevent set 0x20000
4) Check dmesg for throttle start events
ACPI: Execute Method [\_SB_.PCI0.LPCB.EC0_._Q12] (Node ffff8801002c5988)
[ACPI Debug] String [0x12] "EC: THROTTLE START"
[ACPI Debug] String [0x10] "Enable PL1 Limit"
5) Using EC console generate host event for throttle stop
> hostevent set 0x40000
6) Check dmesg for throttle stop events
ACPI: Execute Method [\_SB_.PCI0.LPCB.EC0_._Q13] (Node ffff8801002c59b0)
[ACPI Debug] String [0x11] "EC: THROTTLE STOP"
[ACPI Debug] String [0x11] "Disable PL1 Limit"
Change-Id: I39b53a5e8abc2892846bcd214a333fe204c6da9b
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/63989
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4416
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Two new events possible from the EC for starting and stopping throttle.
These are handled in a per-board method that is defined under the
thermal zone. This is not quite where I wanted it but the scoping
rules in ACPI don't let me have a defined external object in the
same scope.
Change-Id: I766f07b4365b29df3daa8e45e88f7c38c645c287
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/63988
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4415
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
When the edid data structure changed a while ago, it caused hangs on snow
which were fixed by adding those missing members. Unfortunately we didn't
realize that pit needed the same fix.
Change-Id: I81780b8135b99b2e24af723e703b9befff7b5ef0
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/63646
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/4389
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
An issue was observed using a specific vendor's TPM in that it
chokes on access to registers that are not explicitly defined in the
PC client specification. The previous driver used generic access
functions for reading and writing registers. However, issues come
to play when reading from the status register. It read it as a 32-bit
value, but that read address 0x1b which is not defined in the spec.
Instead of using generic access functions for the tpm registers
provide explicit ones. To that end provide more high level wrapper
functions to perform the semantic access required.
Change-Id: I781b31723f819e1387d7aa25512c83780ea0877f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/63243
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4388
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
That speed is used with U-Boot instead of the more conservative 500 KHz.
Change-Id: Ie9d79db3b52b88c1f3bfec1745634ae6bdc9f4ee
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/63193
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/4386
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Some registers and bit fields were wrong, but the difference is mostly
academic since the code that uses them are never called.
Change-Id: I0ce5e1529cdda1a4973765af8c31b79130b1111c
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/63189
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/4385
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
The divisor mask had been set to 0xff, but the bitfield is 4 bits wide.
Change-Id: Id8a205c80ca2fb0b6f0d86a0c3be4bba9527c0b5
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/63188
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/4384
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This functions are by definition changing the data pointed to by their
arguments, so they shouldn't by const.
Change-Id: Id29b3f76526aba463f8bb744f53101327f9c7bde
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/63777
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/4400
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
The timer code was supposed to be using the mct, and also using the monotonic
timer infrastructure instead of the get_timer function. This change had been
made for the 5250 but not yet for the 5420.
Change-Id: I03a4fbb434f2346761f28fb6bd2218b526f2a4a2
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/64159
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/4418
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This code was left over from U-Boot and was superceded by the MCT.
Change-Id: Ia85e3b7281dcdd4740238dddd0dfc6f0ba2c94da
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/63778
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/4401
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
When the const was removed from write function arguments, a related bug in the
5250 code was fixed so that it would still compile. Unfortunately, that same
change needed to be made to the 5420.
Change-Id: If15057c92422de91dc8e35dbd8b5c978bfae122a
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/64154
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/4417
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
The code generally intended to make the pointer const instead of the thing it
pointed at, but it had const backwards. Sometimes both the pointer and the
data could be const, but sometimes there were writes where only the pointer
should be.
Change-Id: Ifcd5495769b86b47d7b583cce63ed5c2158bec4e
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/63775
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/4397
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
The cache.h header uses standard int types but doesn't include stdint.h itself.
Change-Id: If470978164b0cd1f05c27c2c8eda365133cc47ff
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/63190
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/4387
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Now that the rtd2132 device has the full settings the
panel timings need to be implemented. Sadly, the Tx timings
in the rtd2132 aren't 1:1 with the panel's Tx timings. Below
is the table equivalent:
RTD2132 | Falco Panel
--------+------------
T1 | T2
--------+------------
T2 | T8+T10+T12
--------+------------
T3 | T14
--------+------------
T4 | T15
--------+------------
T5 | T9+T11+T13
--------+------------
T6 | T3
--------+------------
T7 | T4
--------+------------
Change-Id: I10a3ad475d6b9485a707eb49e31afd197fc8d24d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/65858
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/4472
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
It has been disseminated that the RTD2132 chip
needs to be fully programmed for settings to take affect.
Most of the settings are note documented very well and
present themselves as magic values. Also, the wait time
for starting the sequence needs to be bumped from 2ms to 60ms.
Lastly, expose all the known settings through devicetree.
Change-Id: I9eeea9c4a13ec20b8ce1c5297e43c4dd793d90e5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/65857
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/4471
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
When we go through the resume path, there shouldn't ever be a need to
initialize the PS/2 keyboard. The OS is going to reinitialize it
anyway, and it just slows the resume.
Verified Code flow in normal boot/S3 resume with print statements.
Verified Keyboard was correctly disabled and flushed by booting
to recovery mode screen while pressing keys on the integrated
keyboard.
Change-Id: I48bdca2fa2cc0c965401d10fef75cadb09d2e1e9
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/63648
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Shawn Nematbakhsh <shawnn@chromium.org>
Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/4396
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Add a function to disable and clear the keyboard controller.
Verified Code flow in normal boot/S3 resume with print statements.
Verified Keyboard was correctly disabled and flushed by booting
to recovery mode screen while pressing keys on the integrated
keyboard.
Change-Id: I3e1f011c3436fee5ce10993c6c26a3c8597c6fca
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/63627
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Shawn Nematbakhsh <shawnn@chromium.org>
Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/4395
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
- prints hex and ascii
- detects duplicate all zero lines
Change-Id: I557fed34f0f50ae256a019cf893004a0d6cbff7c
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/62655
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: Stefan Reinauer <reinauer@chromium.org>
Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: http://review.coreboot.org/4392
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
The hexdump function was added to libpayload recently, but its source file was
never added to the Makefile so it wasn't compiled or linked in.
Change-Id: Ic3c12a5b8a6ea631b83c10a6e4210544ff00b5bf
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/64878
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/4439
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
The PWM is controlled externally from the APU.
Change-Id: Ia5130d7616991a78dfde44043a60a32cee4f145c
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/61513
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: Ronald G. Minnich <rminnich@chromium.org>
Tested-by: Ronald G. Minnich <rminnich@chromium.org>
Reviewed-on: http://review.coreboot.org/4363
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
What gets written into the parade is highly mainboard-dependent.
So the parade_writes array needs to be there.
Change-Id: Ia382d9bf1929e67b7c14d7a09f5461b71866a16b
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/61486
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: Ronald G. Minnich <rminnich@chromium.org>
Tested-by: Ronald G. Minnich <rminnich@chromium.org>
Reviewed-on: http://review.coreboot.org/4362
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
When the board is in S3 and S5 the WLAN_DISABLE_L signal
can leak power into the WLAN power well since the GPIO
controlling WLAN_DISABLE_L is in the suspend well. Therefore,
drive WLAN_DISABLE_L low to avoid the power leak.
This is a clone of a Falco change:
I1a0df80dd47fdbd535aca7a9d49253794c480606.
Change-Id: I625dfbb228d1f293b880a52dfe552842d55a17d1
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/63220
Reviewed-by: Dave Parker <dparker@chromium.org>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/4383
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
... based on the EDID detailed timing values for
pixel_clock and link_clock.
Two undocumented registers 0x6f040 and 0x6f044 correspond to link_m and link_n
respectively. Other two undocumented registers 0x6f030 and 0x6f034 correspond
to data_m and data_n respectively.
Calculations are based on the intel_link_compute_m_n from linux kernel.
Currently, the value for 0x6f030 does not come up right with our calculations.
Hence, set to hard-coded value.
Change-Id: I40ff411729d0a61759164c3c1098504973f9cf5e
Reviewed-on: https://gerrit.chromium.org/gerrit/62915
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/4381
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This code is left over from what the VBIOS did; It is redundant.
Change-Id: I321c867c81ec8b4d5e10f8b51b872cecb3082d97
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/62290
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/4380
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Turn on the pei_data flag that will instruct the reference code
binary to route all USB ports to the XHCI controller on resume and
disable the EHCI controller(s).
Change-Id: I2f2ed853a6d17f90ea524bc516f3e78079222739
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/63798
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4404
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
The linux kernel will unconditionally route all USB
ports to the XCHI controller at boot. The EHCI controller
can then be disabled, and it should be left disabled
by the reference code when this is done.
However not all OS may do this unconditional route,
so provide an option to the reference code binary to
enable this behavior.
Change-Id: Iedf5af54182bf109cd1119c1999e46300665d41e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/63797
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4403
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
SATA is routed to PIRQG which should be interrupt 22
and not interrupt 21. The kernel uses MSI with this
device so this is only seen when booting with pci=nomsi
Change-Id: Ic90ca2c561fc4c53ec1d395c05872222c65ff98a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/63796
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4398
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
The EHCI driver defines a maximum transfer timeout of two seconds. The
comments state that during tests the maximum amount of required transfer
time was for the SCSI TEST_UNIT_READY command on certain devices. We
have now observed a USB device (Patriot Memory 13fe:3100) that can NAK
this command for slightly more than two seconds. It will also completely
fail if the timeout hits, since it gets confused by the subsequent CSW
retry/recovery mechanism and starts producing babble errors. This patch
increases the timeout to three seconds to circumvent this problem.
To test, boot a Falco from a red-black RageXT USB stick.
Change-Id: I3c4fef468fb16eacc5a487d76d025a78fb450e27
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/63095
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Sameer Nanda <snanda@chromium.org>
Reviewed-on: http://review.coreboot.org/4379
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Furquan Shaikh