This patch provides an option for non-chrome devices to make use of
FSP-T for performing cache-as-ram initialization. Majority of IOTG users
are using FSP-T for CAR implementation and aren't able to select FSP_CAR
Kconfig from SoC without conflicting with existing CAR config.
TEST=Ensure that both the Chrome platform and non Chrome OS platform
can select either CAR implementation based on Kconfig options
FSP_CAR or CAR_NEM_ENHANCED. By default Chrome platform choose
CAR_NEM_ENHANCED Kconfig and non Chrome platforms choose
FSP_CAR by default.
Change-Id: If565b649fe1c2abdbcf0a740c15db7253c084ae7
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
According to CNL PCH BIOS spec (570374) 2.4.1, DMI cycle decoding needs
to be programmed before it gets locked. Update lpc programming to add
decode programming on DMI side as well. Also enabled io port 0x200
decoding by default.
BUG=b.70765863
TEST=Apply changes and add chromeos EC decoding in mainboard
devicetree.cb, then read back IO port in depthcharge cli and check
that return is not zero.
Change-Id: I6b8f393c92cbd0632fed86212ae384ff53c9f8c3
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22970
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch sets the ACPI FADT flag ACPI_FADT_LOW_PWR_IDLE_S0
if S0IX is enabled for the platform.
TEST= Boot to OS and check the ACPI_FADT_LOW_PWR_IDLE_S0 flag
is set in FACP table.
Change-Id: Ibb43d5c8024dcdf753416e4bd2a457991cc7a433
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/23095
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
All boards and chips that are still using LATE_CBMEM_INIT are being
removed as previously discussed.
If these boards and chips are updated to not use LATE_CBMEM_INIT, they
can be restored to the active codebase from the 4.7 branch.
chips:
cpu/intel/socket_mFCBGA479
northbridge/intel/i82830
Mainboards:
mainboard/rca/rm4100
mainboard/thomson/ip1000
Change-Id: I9574179516c30bb0d6a29741254293c2cc6f12e9
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/22032
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
All boards and chips that are still using LATE_CBMEM_INIT are being
removed as previously discussed.
If these boards and chips are updated to not use LATE_CBMEM_INIT, they
can be restored to the active codebase from the 4.7 branch.
chips:
northbridge/intel/i3100
southbridge/intel/i3100
superio/intel/i3100
cpu/intel/socket_mPGA479M
Mainboards:
mainboard/intel/truxton
mainboard/intel/mtarvon
mainboard/intel/truxton
Change-Id: Ic2bbdc8ceb3ba0359c120cf4286b0c5b7dc653bb
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/22031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
All boards and chips that are still using LATE_CBMEM_INIT are being
removed as previously discussed.
If these boards and chips are updated to not use LATE_CBMEM_INIT, they
can be restored to the active codebase from the 4.7 branch.
chips:
northbridge/intel/i5000
Mainboards:
mainboard/supermicro/x7db8
mainboard/asus/dsbf
Change-Id: I6614c0033b4439d196f26819998d3f85e6d11c00
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/22030
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
All boards and chips that are still using LATE_CBMEM_INIT are being
removed as previously discussed.
If these boards and chips are updated to not use LATE_CBMEM_INIT, they
can be restored to the active codebase from the 4.7 branch.
chips:
northbridge/intel/i855
Mainboards:
mainboard/lanner/em8510
Change-Id: Ic9ba0ba7e2b6e602a5749cc531dd705c49e3f08d
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/22029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
All boards and chips that are still using LATE_CBMEM_INIT are being
removed as previously discussed.
If these boards and chips are updated to not use LATE_CBMEM_INIT, they
can be restored to the active codebase from the 4.7 branch.
chips:
soc/intel/sch
Mainboards:
mainboard/iwave/iWRainbowG6
Change-Id: Ida0570988a23fd0d13c6fcbe54f94ab0668c9eae
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/22027
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
All boards and chips that are still using LATE_CBMEM_INIT are being
removed as previously discussed.
If these boards and chips are updated to not use LATE_CBMEM_INIT, they
can be restored to the active codebase from the 4.7 branch.
chips:
soc/dmp/vortex86ex
Mainboards:
mainboard/dmp/vortex86ex
Change-Id: Iee7b6005cc2964b2346aaf4dbd9b2d2112b7403f
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/22026
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
All boards and chips that are still using LATE_CBMEM_INIT are being
removed as previously discussed.
If these boards and chips are updated to not use LATE_CBMEM_INIT, they
can be restored to the active codebase from the 4.7 branch.
chips:
cpu/amd/geode_gx2
northbridge/amd/gx2
southbridge/amd/cs5535
Mainboards:
mainboard/amd/rumba
mainboard/lippert/frontrunner
mainboard/wyse/s50
Change-Id: I81c130f53bbfa001edbfdb7a878ef115757f620c
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/22025
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Add the option to use the lz4 compression method
to compress payloads.
Also sets LZ4 as the default compression method.
Change-Id: Ic712f984f791d268440c8463eaea0d246aa31d99
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/15817
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The Primary to Sideband Bridge (P2SB) is the interface to Private Con-
figuration Registers (PCR) including GPIO configuration. Of course,
access is restricted to Intel partners and criminals, so the PCI device
is hidden from the OS. Probably we only need to fetch the SBREG_BAR
address and can hide the PCI device again after that.
Change-Id: Ic121a09f021708aab82ae4b9d76d6c3c6fb884fa
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/19588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
GCC includes `sched.h` after poisoning calloc(). This results in a
build failure with Musl libc. We work around the issue by including
`sched.h` earlier and throw around some void pointers so we only
have to do it in one place.
Change-Id: I1d5462eb9a448147a95dd4ec50361b3f5a28910c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/22786
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Looks like we were unnecessarily dragging this around for some time now.
GCC's installation manual doesn't mention libelf as a requirement and a
build of crossgcc-i386 doesn't show any sign of it being used.
This also fixes a lot issues on non-GNU distributions that were intro-
duced by switching to the elfutils version of libelf.
Change-Id: Iff308a9bed9ae3842557d251b75d1faadfafe0da
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/22773
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
In the buildgcc script, there is a check that the tools required are
installed. When a tool is missing, a message is output suggesting an
installation method, e.g. `sudo apt-get install foo` on debian-based
systems.
When run on a true, vanilla debian system, the error message provides
only a generic hint because the `please_install()` function fails to
detect the OS kind. Detection is based on definition of `ID_LIKE` in
`/etc/os-release` yet such systems only define `ID` to `debian`.
This commit closes the detection gap. Tested on debian 9 (stretch).
Change-Id: I3c867837e9157bee13010bd0a005028c369ce55f
Signed-off-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com>
Reviewed-on: https://review.coreboot.org/23231
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Some Dock events only need to happen based on the Dock Id (which
functions as a presence detect GPIO).
Inspired by vendor bios DSDT.
This fixes undock ACPI events being issued when pulling out the power
when docked or undocked (but still generates one when forcibly
undocked)
Tested on X200: pull power and see if undock events are generated in
dmesg.
Change-Id: I1eef971d49508bcd94d5d1cf2b70395b7cd80b1c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22919
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kevin Keijzer <kevin@quietlife.nl>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
If the DRAM does *not* actually overlap the PCI space, the remap code
notices it is the case, but for some reason proceeds with the remapping,
attempting to remap a negatively sized chunk. Bummer.
With a single 1024M (two ranks of 512M) module:
Nothing to remap
Mem remapping enabled
Remapstart 5120(MB)
Remapend 6144(MB)
Top of RAM 1024MB
New top of RAM 2560MB
Wrote remap map a0101
Mem remapping enabled
Remapstart 4096(MB)
Remapend 2560(MB)
New top of memory is at 2560MB
Needless to say, subsequent ram_resource() ruins the memory map for the
OS -- Linux won't boot without a mem= argument and memtest quickly.
TEST=memtest and Linux boot on HP t5550 with 1024M of memory
Change-Id: Ic221723a26c5d1a03bf34c7722b0abe115f456ba
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-on: https://review.coreboot.org/22271
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This is required for Flashrom to work well.
Change-Id: Id756d86a7f3b34f816ea7a7ed78f159512f550d5
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-on: https://review.coreboot.org/22258
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
They both have a device id of 0x3c. The former is part of the PCI chip set
accessible via port 0x3f0 while the latter is a standalone LPC chip accessible
via 0x2e/0x4e depending on strapping.
They're not register compatible: the VT82C686 only provides a FDC, LPT and part
of UARTs.
The VT82C686 documentation suggests it has revision 0x00 while the VT1211
datasheet indicates 0x01. Nevertheless, the VT1211 I happen to have hs a
revision of 0x02. Thus the revision is probably not good enough to tell one
from the another.
Change-Id: Ic7529c84724c8d6b9eb75b863f1bceef5e4b52b5
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-on: https://review.coreboot.org/22254
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The `secimage` utility uses OpenSSL to calculate HMAC, which it does in
a rather unorthodox way, using deprecated `HMAC_CTX_init` API and
repeated calling of `HMAC_Init_ex` without a clear reason. The former
causes build errors with OpenSSL 1.1 while the rest of the
`HmacSha256Hash` function is confusing and overly complex.
Make `HmacSha256Hash` use a single OpenSSL API call. Test passed:
resulting signed binary remains identical.
Change-Id: Ib23c0ad96f9d8cc30ad357de8c0b0ba967c7d724
Signed-off-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com>
Reviewed-on: https://review.coreboot.org/23069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This source file was mostly copied from ga-945gcm-s2l but had
different IO decode ranges.
Change-Id: I54cb165000fad6984edf13fb33519fb9c9f0350f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23134
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Things cleaned up in this patch:
* Add macros for the GENx_DEC registers;
* replace many magic numbers by macros;
* remove many writes to DxxIP since they were 'setting' reset default
values;
* fix some comments about decode ranges.
Change-Id: I9d6a0ff3d391947f611a2f3c65684f4ee57bc263
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/21065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Use the variable `device` instead of `dev` in the predicate of
the if condition, as `dev` is not changed in the for loop.
The for loop was added in the following commit.
commit 8fed77ae4c
Author: Scott Duplichan <scott@notabs.org>
Date: Sat Jun 18 10:46:45 2011 -0500
ASRock E350M1: Configure SB800 GPP ports to support onboard pcie nic
Reviewed-on: http://review.coreboot.org/44
The assumption that the devices are ordered in the tree seem to
hold in this case (although it is not ensured) and therefore at
least with the ASRock E350M1 no (visible) change is experienced as
the children are all of type `DEVICE_PATH_PCI`.
Change-Id: Iaa2fa13305dbe924965d27680cd02fe30c2f58a5
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/2562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add code to support the board ASUS AM1I-A. Tested with multiple payloads
and OSes with satisfactory results. S3 suspend/resume works fine with
Linux but has issues with Windows (an exception is thrown). However,
after manually rebooting, Windows resumes the suspended session.
* Tested with: SeaBIOS 1.11 + Linux 4.10 - OK
* Tested with: tianocore vEDK2017 + MS Windows 8.1 - OK
* Tested with: FILO 0.6.0 - hangs after showing the banner
Details are going to be published on the board's status page.
Change-Id: I3d9432849560df81536bbb2ce4c87cd265b820f7
Signed-off-by: Gergely Kiss <mail.gery@gmail.com>
Reviewed-on: https://review.coreboot.org/23002
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Due to the lack of a datasheet, defaults are shown as
"not available (NA)" in the register dump.
Change-Id: I6baaf5dd95453fb1265425f357ea16c710c006ba
Signed-off-by: Gergely Kiss <mail.gery@gmail.com>
Reviewed-on: https://review.coreboot.org/23084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
GPIO 90 is being used as a GPIO. The IOMUX register is set correctly,
but these additional registers need to be set to use it as a GPIO.
- Split structures into variant specific versions. These will be
moved into the variant tree in a follow-on patch
- Set GENINT_DISABLE bit
- Disable interrupts for this GPIO.
BUG=b:71867096
TEST=Build and boot grunt. Verify registers are set correctly.
Change-Id: I4b8d12720167b298ee6e0acf80edf414539975b0
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/23228
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The GPIOs that are being set low had the wrong value getting set.
FCH_GPIO_OUTPUT_VALUE was being set instead of FCH_GPIO_OUTPUT_ENABLE.
BUG=b:70234300
TEST=Build and boot Grunt
Change-Id: I16792b76252506a43aac92738b04096ae3fde01c
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/23224
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Grunt and Kahlee touchpads are on different i2c busses; I2CC and I2CD,
respectively.
Since grunt is the 'baseboard', put its configuration under baseboard, and
include it from the grunt variant.
BUG=b:71820409
TEST=Boot grunt to kernel, use evtest to test trackpad.
TEST=Boot kahlee to kernel, use evtest to test trackpad.
Change-Id: I1aeacf9a840342e73c1e219a825b39a124b4dd57
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/23232
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Grunt and Kahlee have different audio codecs.
Create a new audio .asl for the baseboard for grunt's codec, link
to it from the grunt mainboard, and move the kahlee codec table
from the baseboard mainboard to its own .asl in variant/kahlee.
Note, we can't use the generic drivers due to the PCI scope
expectation. The AMD I2C are not PCI devices.
BUG=b:69397774
TEST=Codec driver loads. Check dmesg.
Change-Id: I1cc245357d1f3d444e5a5012466eaa5d75d637eb
Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
Signed-off-by: Marc Jones <marcj303@gmail.com>
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/23226
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move the apci/ to the baseboard and move mainboard.asl to
each variant.
BUG=b:71873651
TEST=build
BRANCH=none
Change-Id: I8a829f2946e4b280cd78574eb8dbda6c2a9a1028
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/23229
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
The ACPI unique identifier (_UID) should be unique.
This doesn't actually matter much for Linux, though, since the kernel
can handle it when the BIOS doesn't get this right.
See:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=b4b6cae2f36d92b31788f10816709d5290a1119a
b4b6cae2f36d ACPI / platform: use ACPI device name instead of _HID._UID
Change-Id: I8b1b3143174584a93f3d45bf482b8922b3f0ec12
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/23233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
This reverts commit 0f5651584ebb8e2ccfa151275bfd2f70e74bae9b.
This is not the correct fix for the heap allocator.
It looks like the root cause is in the buffer size of the
deallocate function.
Change-Id: I33c479a30d89a665677d3e4914194ae8136504af
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/23245
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chris Ching <chingcodes@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Meowth uses GPD_2 as a dedicated lan_wake pin, so GPD_2 must
be set to use NF1 instead of gpio.
BUG=b:64395641
BRANCH=none
TEST=none
Change-Id: Iadf7158a792dfae0ea5e824d197a558524cdb5fd
Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org>
Reviewed-on: https://review.coreboot.org/23222
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Intense PC uses FCBGA1023 socket, not rPGA989. Correct the socket
in the devicetree.
Change-Id: Ie657af2f51dfb7add90b19b26c0c37d312d59821
Signed-off-by: Hal Martin <hal.martin@gmail.com>
Reviewed-on: https://review.coreboot.org/22762
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Enable the UART via SMSC SIO1007 SuperIO, this allows you to see boot
boot messages from coreboot over the integrated RS-232 port (requires
use of included dongle).
Change-Id: I11a4c532ed73a0cf27d6e7bef6e04035c3942567
Signed-off-by: Hal Martin <hal.martin@gmail.com>
Reviewed-on: https://review.coreboot.org/22737
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
The code is based on autoport and that for 8470p.
Tested:
- CPU i5-3437U
- Slotted DIMM 8GiB
- Soldered RAM 4GiB from Hynix (There may be more models here)
- Onboard USB2 interfaces (digitizer, wlan slot, wwan slot, camera)
- Mini pci-e on wlan slot
- On board SDHCI connected to pci-e
- USB3 ports
- USB3 hub on dock (connected to USB3 port 1)
- NVRAM options for North and South bridges
- S3
- TPM1 on LPC
- Linux 4.13.13-1 within Debian GNU/Linux testing, loaded from
SeaBIOS, or Linux payload (Heads)
Not work:
- An "NFC" device connected to LPC
Not implemented yet:
- Detecting the model of Soldered RAM at runtime, and loading
the corresponding SPD datum (3 observed) from CBFS
Change-Id: Iba9c361591697e6a2b3b7b485f7f1649c2a83524
Signed-off-by: Bill XIE <persmule@gmail.com>
Reviewed-on: https://review.coreboot.org/22972
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
We check for NULL from the return of function acpi_device_path
before passing it to acpigen_write_scope to avoid NULL pointer
dereference.
Change-Id: I997461c9b639acc3c323263d304333d3a894267c
Found-by: Klockworks
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/23094
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
According to Intel document #559100 KBL EDS v2.8, section 7.2
DC specifications, the IccMax setting for KBL-U, KBL-U42 and
Celeron/Pentium are different. This patch overrides the IccMax
settings for KBL-U/R/Y since device tree could not handle all
KBL-U/R combinations when multiple SKUs are adopted in a project.
Besides, it is inefficient to maintain the same code for all
variants. Hence, place it in the common code so that all variants
could leverage the benefits.
+----------------+-------------+---------------+------+-----+
| Domain/Setting | SA | IA | GTUS | GTS |
+----------------+-------------+---------------+------+-----+
| IccMax(KBL-U/R)| 6A(U42) | 64A(U42) | 31A | 31A |
| | 4.5A(Others)| 29A(Celeron) | | |
| | | 32A(i3/i5) | | |
+----------------+-------------+---------------+------+-----+
| IccMax(KBL-Y) | 4.1A | 24A | 24A | 24A |
+----------------+-------------+---------------+------+-----+
BUG=b:71369428
BRANCH=None
TEST=Remove icc_max setting from devicetree & emerge-fizz coreboot
chromeos-bootimage & Ensure the KBL-U42, KBL-U22 and Celeron
SKUs are identified correctly and IccMax settings are passed
to FSPS correctly.
Change-Id: I291462b73d3fbd17f17975de7fd77dc48ca99251
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/23060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The EC does enable bluetooth on wifi cards and BDC at the same time.
Check the new Kconfig to support bluetooth on wifi in case no BDC
is installed and the BDC detection fails.
Change-Id: I23f14c937252a296dc543db49ec9e093e7e24604
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/21578
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Fizz has external Lan on PCIE port.
The Lan device on PCH is not used.
BUG=b:70889517
Change-Id: I99894bedec14a44724ac7c22d0c894132a795b78
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/23180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch adds the EC_GOOGLE_CHROMEEC_SWITCHES option so that we
use the common switch.c file
Change-Id: I93a2ba63015db17989c89ce1b5897de6a93e201f
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/23131
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Subrata Banik