Commit Graph

46957 Commits

Author SHA1 Message Date
Frans Hendriks a02b77a96b IASL: Correct warning message for IASL missing dependency
Warning for _SRS includes _SRS.
Warning for _DIS includes must have _SRS twice.

Remove requirement _SRS for _SRS is present.
Removed second _SRS for _DIS is present.

BUG=N/A
TEST=Verify correct message on built of facebook FBG1701

Change-Id: I1be740354b159e931e41323aef14e160cc09af19
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>´
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63250
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-08 14:44:31 +00:00
Werner Zeh f2234422e9 soc/intel/apollolake: Correct enum for PrimaryVideoAdaptor FSP parameter
Commit 1a4496e79f (soc/{apl,glk}: Allow to select the primary graphics
device) adds code to set the FSP parameter 'PrimaryVideoAdaptor' based
on the enum description of the FspmUpd.h for Apollo Lake.

Unfortunately, the comment in the header file does not match the
implementation in the FSP and hence setting PrimaryVideoAdaptor to
'GPU_PRIMARY_IGD' will be treated as if the selection was
'GPU_PRIMARY_PCI'. This in turn leads to Linux gfx driver issues for
earlier driver implementations.

This commit corrects the enum values for the FSP parameter to match the
implementation.

TEST=Boot into Linux on mc_apl1 and verify that graphics works.

Change-Id: Iedbc144fa809f6d4587f5223b235ee95579c48f7
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62889
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-04-08 14:43:45 +00:00
Subrata Banik 01bf0020d2 soc/intel/common/cse: Show CSE device slot and function number properly
This patch fixes a problem where the `is_cse_devfn_visible` function is
unable to show the CSE device slot and function number properly. 

BUG=b:211954778
TEST=Able to display CSE device slot and function number properly as
below:

Before:
[DEBUG]  PCI: 00:16.0 final
[WARN ]  HECI: CSE device 00.0 is disabled
[WARN ]  HECI: CSE device 00.0 is disabled
[WARN ]  HECI: CSE device 00.0 is disabled
[WARN ]  HECI: CSE device 00.0 is disabled
[WARN ]  HECI: CSE device 00.0 is disabled

With this code changes:
[DEBUG]  PCI: 00:16.0 final
[WARN ]  HECI: CSE device 16.1 is disabled
[WARN ]  HECI: CSE device 16.2 is disabled
[WARN ]  HECI: CSE device 16.3 is disabled
[WARN ]  HECI: CSE device 16.4 is disabled
[WARN ]  HECI: CSE device 16.5 is disabled

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I76a634c64af26fc0ac24e2c0bb3a8f397a65d77b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-04-08 14:42:27 +00:00
Subrata Banik 96527da2da soc/intel/cse: Allow calling all functions associated with `cse_final`
This patch fixes a problem where `cse_final` only calls into 1 function
from available `notify_func` lists.

BUG=b:211954778
TEST=Able to execute `cse_final_end_of_firmware` function as part of
`cse_final` call.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I04d8c9c1213ddeb9ed85473e62fcca298c0d5172
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-04-08 14:42:00 +00:00
Joey Peng c0c40b94e3 mb/google/brya/var/taniks: Enable Genesys L1 max entry delay
The workaround causes the eMMC controller to not enter its L1
during the boot process

BUG=b:220079865
TEST=Build FW and run stress exceed 2500 cycles.

Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: I2a5888e943c1ebf83a54f9b172f986f8b13d9b6a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63131
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-07 20:48:18 +00:00
Sridhar Siricilla 52479c7919 soc/intel/common: Update CSE sub partition update
The patch adds support in the CSE Sub partition update procedure
to use GET_BOOT_PARTITION_INFO HECI command output to create the
region device for CSE RO and CSE RW. The GET_BOOT_PARTITION_INFO
HECI command provides CSE's RO and RW boot partition information.

Existing code relies on FMD file to get the CSE's boot partition's
(CSE RO and CSE RW) start and size details. This change make
independent of FMD file declaration with respect to CSE RO and CSE RW.

TEST=Build and verify the CSE RO and CSE RW region device information
through code instrumentation. Also, did boot test on Kano system.

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Ie9a83b77ab44ea6ffe5bb20673e109a89a148629
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-07 20:48:03 +00:00
Felix Held 6e296b3773 MAINTAINERS: lower maintenance level of super I/O and superiotool
I don't really get around to review super I/O or superiotool patches any
more, so lower the maintenance level of those. If anyone else wants to
step up as new maintainer for those two, feel free to do so.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id7bd3c68c1adc0db82dab078291918742b453d4c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63417
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-04-07 20:40:52 +00:00
Kyösti Mälkki 4ff218aa71 ChromeOS: Add DECLARE_x_CROS_GPIOS()
Change-Id: I88406fa1b54312616e6717af3d924436dc4ff1a6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-07 20:38:12 +00:00
Akihiko Odaki f0be9e3472 ec/google/chromeec: Initialize device_path subid
Signed-off-by: Akihiko Odaki <akihiko.odaki@gmail.com>
Change-Id: I910998a5555319cf9840493a31df4934054e08ce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63384
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-07 16:20:59 +00:00
Lean Sheng Tan e8df93af91 soc/intel/alderlake: Hook up PAVP to Kconfig
Expose configuration of Intel PAVP (Protected Audio-Video Path, a
digital rights protection/management (DRM) technology for
multimedia content) to Kconfig.

Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I5a364a9781642eb366e5e502a4ee69008c19bcd6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63304
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-07 16:20:21 +00:00
Lean Sheng Tan 4b45d4c802 soc/intel/alderlake: Hook up VrPowerDeliveryDesign to devicetree
The FSP needs to program VrPowerDeliverDesign configuration per
platform according to the platform capabilities to avoid incorrect
electrial/power parameters. This value is an enum of the available
power delivery segments that are defined in the Platform Design
Guide.

Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I74859e6735e59a15084a9e690b43f68341862833
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63303
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-07 16:19:56 +00:00
Teddy Shih 369b9ad787 mb/google/dedede/var/beadrix: Update PCIe and SATA pins for low power consumption
To achieve low power consumption, we disable unused PCIe and SATA
pins at beadrix/overridetree.cb according to baseboard/devicetree.cb
and mainboard schematic. Original measured beadrix board's power
consumption is about 250 mW. After we disable unused PCIe and SATA
pins, as well as, enable the other low power MUX CL (3487086: USB
MUX: Update low power mode of MUX anx7447 used as MUX only |
https://chromium-review.googlesource.com/c/chromiumos/platform/ec/
+/3487086), the measured power consumption achieves about 110 ~ 116
mW, as well as, meets Google battery life for 14 days in the suspend
state and Intel low power consumption about 116 mW.

BRANCH=dedede
BUG=b:204882915
TEST=on beadrix, measured power consumption meets Intel power
consumption.

Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com>
Change-Id: I79ec524c5ce8f2a79da4aeba084786fb9dac17af
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62776
Reviewed-by: Teddy Shih <teddyshihau@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Super Ni <super.ni@intel.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Ivan Chen <yulunchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-07 15:31:57 +00:00
Kenneth Chan 0fd3c38d84 mb/google/guybrush: allow MKBP devices and disable TBMC device
Enable MKBP (Matrix Keyboard Protocol) interface for all guybrush family
to use for buttons and switches. Disable TBMC (Tablet Mode Switch
device), as it is not needed anymore.

BUG=b:227240985
BRANCH=guybrush
TEST=manual test on Dewatt:
     Volume Up/Down and Power buttons, Tablet Mode switch

Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Change-Id: Ic9980f2b5bf10b12f2bd666212b5bce925dc323d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63394
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-07 15:28:40 +00:00
Jeff Daly 380fcfb39d soc/intel/denverton_ns/chip.c: add soc_acpi_name function
Intel common SoC code uses SoC-specific soc_acpi_name function to
generate ACPI tables, add this to Denverton

Signed-off-by: Jeff Daly <jeffd@silicom-usa.com>
Change-Id: I5f50733656ca7724caf8a6570bcb21f7b761c3ce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com>
2022-04-07 14:44:44 +00:00
Jeff Daly dc5d3f368b soc/intel/denverton_ns: add common device function macros
Add device function macros for Denverton similar to other SoCs

Signed-off-by: Jeff Daly <jeffd@silicom-usa.com>
Change-Id: I75daaf4907515f80a10c003eb473bbe557a42acc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60990
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com>
2022-04-07 14:44:06 +00:00
Rex-BC Chen 29cad5a59e soc/mediatek/mt8186: Disable unused power
To save the power consumption, we disable the unused power of
optional components in coreboot.

BUG=none
TEST=the value of power consumption is as expected.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ic0c7c2d1b6a4c26980a3029b60051ab1406406ea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-04-07 14:43:36 +00:00
Arthur Heymans a552cfc981 drivers/amd/agesa/romstage.c: Move timestamp and console init up
Follow-up commits move this to a common place.

Change-Id: I26a37f9384a581a8a750efccc2100a5c6a6f0f85
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-04-07 10:59:29 +00:00
Reka Norman 1a8ecb6438 mb/google/brya/var/nereid: Add WLAN power sequence
There are currently two issues related to the WLAN power sequencing on
nereid:
- If the EN pin GPP_B11 is not high during cold boot, the SoC gets stuck
  in S3.
- During warm reboot, if we only assert RST without pulling the power
  low, then the kernel crashes.

As a workaround while we investigate these issues, we pull the EN high
in S5, then actively drive it low in bootblock and high in romstage to
make sure it goes low during warm reboot.

BUG=b:227694137, b:225261075
TEST=Cold boot succeeds, and there's no kernel crash during warm reboot.

Change-Id: I1ca46d9649eff3f96a0e77db594d87288b29a83a
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63368
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
2022-04-07 08:15:14 +00:00
Reka Norman 07bb783c4b mb/google/brya/var/nereid: Enable pen garage
BUG=None
TEST=evtest works:
Select the device event number [0-14]: 9
Input driver version is 1.0.1
Input device ID: bus 0x19 vendor 0x1 product 0x1 version 0x100
Input device name: "PRP0001:00"
Supported events:
  Event type 0 (EV_SYN)
  Event type 5 (EV_SW)
    Event code 15 (SW_PEN_INSERTED) state 1
Properties:
Testing ... (interrupt to exit)
Event: time 1649153020.275201, type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 0
Event: time 1649153020.275201, -------------- SYN_REPORT ------------
Event: time 1649153025.848689, type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 1
Event: time 1649153025.848689, -------------- SYN_REPORT ------------
Event: time 1649153028.383195, type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 0
Event: time 1649153028.383195, -------------- SYN_REPORT ------------
Event: time 1649153080.869155, type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 1
Event: time 1649153080.869155, -------------- SYN_REPORT ------------

Change-Id: I0d5134737fc758a43e1fff95e9f2a20200991bb1
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63370
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-04-07 08:14:58 +00:00
Reka Norman a6de947a6b mb/google/brya/var/nereid: Configure descriptor for either Type-C or HDMI
Some bytes in the descriptor need to be set differently for Type-C and
HDMI. To allow using a single firmware variant for both cases, update
the descriptor at runtime based on fw_config. This is a temporary
workaround while we find a better solution.

The byte values were determined by changing the following CSE strap and
comparing the generated descriptors:
Type-C: TypeCPort2Config = "No Thunderbolt"
HDMI:   TypeCPort2Config = "DP Fixed Connection"

The default value before updating the descriptor is Type-C, but this was
chosen arbitrarily.

BUG=b:226848617
TEST=Type-C and HDMI both work on nereid with fw_config set correctly.

Change-Id: I2cc230e3bd35816c81989ae7e01df5d2c152062e
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63366
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sam McNally <sammc@google.com>
2022-04-07 08:14:37 +00:00
Reka Norman e790f929bd soc/intel/alderlake: Add support to update descriptor at runtime
On nereid, we need to update the descriptor based on fw_config (see
the follow-up patch), so add support to update the descriptor at
runtime. This is a temporary workaround while we find a better solution.

This is basically adding back the configure_pmc_descriptor() function
removed in CB:63339, just making it generic and allowing it to update
multiple bytes at once.

BUG=b:226848617
TEST=With the following patch, Type-C and HDMI work on nereid.

Change-Id: I43c4d2888706561e42ff6b8ce0377eedbc38dbfe
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63365
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sam McNally <sammc@google.com>
2022-04-07 08:12:20 +00:00
Sridhar Siricilla d7cdeee74d soc/intel/alderlake: Remove ALDERLAKE_A0_CONFIG_PMC_DESCRIPTOR Kconfig
The patch removes Kconfig CONFIG_ALDERLAKE_A0_CONFIGURE_PMC_DESCRIPTOR
code which updates PMC descriptor for an intermediate ADL-P SoC
stepping A0. Since intermediate ADL-P SoC is no longer supported and no
board is selecting the Kconfig, so remove the code that updates PMC
descriptor.

TEST=Build and boot Gimble board

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I2a629353a4194a7505655346dcab4ef53059e0b7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63339
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-07 08:11:43 +00:00
Kyösti Mälkki 662353ac3e ELOG: Refactor watchdog_tombstone
The symbol watchdog_tombstone is not really about ChromeOS
but ELOG instead. This prepares for furher move of the
watchdog_tombstone implementation.

Change-Id: I8446fa1a395b2d17912a23b87b83277c80828874
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63300
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-04-06 23:42:56 +00:00
Arthur Heymans 24a20e4d21 mb/ti/beaglebone/board.fmd: Use 'FLASH' as device name
FLASH is often used when accessing FMAP base and size from
fmap_config.h so it's handy to be consistent with all other boards.

Change-Id: Ibba938c72d42ac74dcea8e8e6478ddae510d8c03
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63349
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-06 23:10:06 +00:00
Chris.Wang ec7a932aa2 mb/google/skyrim/var/baseboard: Set Clk request for WLAN/SD/SSD device
Setting the clock source depends on clock request pin for WLAN/SD/SSD
device. Also turn off the unused (CLKREQ#3) clock sources.In skyrim,
clock source 0/1/2 are routed for WLAN/SD/SSD device.

BUG=b:227297986
BRANCH=none
TEST=Build

Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I21fb912b69f59717eb4e84c379f706a0257a9ed1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-06 17:41:41 +00:00
Kyösti Mälkki 4fdd84e716 ChromeOS: Promote variant_cros_gpio()
The only purpose of mainboard_chromeos_acpi_generate()
was to pass cros_gpio array for ACPI \\OIPG package
generation.

Promote variant_cros_gpio() from baseboards to ChromeOS
declaration.

Change-Id: I5c2ac1dcea35f1f00dea401528404bc6ca0ab53c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58897
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-06 17:40:50 +00:00
Sridhar Siricilla afe5562ca3 soc/intel/(cnl, jsl, tgl): Enable SOC_INTEL_COMMON_BASECODE
The patch SOC_INTEL_COMMON_BASECODE Kconfig for Comet Lake, Jasper Lake
and Tiger Lake SoCs. It allows access to intelbasecode/debug_feature.h
for Comet Lake, Jasper Lake and Tiger Lake SoCs.

TEST=Build code for Brya

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Ie55ded673c8fa0edf2ca6789b15771bd2e56c95e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-06 17:34:25 +00:00
Sridhar Siricilla fad76f33a9 mb/google/brya: Enable dynamic debug capability for brya family
The patch enables dynamic debug capability for Brya family of boards.

BRANCH=MAIN
BUG=b:153410586
TEST= Verified the CSE firmware update functionality on Brya

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I51b0e0bb4392d3fbdb50577d3644491ab90a33c3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61381
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2022-04-06 17:34:11 +00:00
Sridhar Siricilla f5e94b6e72 soc/intel/alderlake: Enable debug driver for Alder Lake platform
The patch enables dynamic debug capability driver for Alder Lake
platform.

BUG=b:153410586
TEST= Build code for Brya

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Ic4df3d7f3d6585bd37c632b1a3f0a47c94b63697
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62652
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-04-06 17:33:54 +00:00
Sridhar Siricilla 2c2706ccef soc/intel/common: Add support to control coreboot and Intel SoC features
The patch adds a framework to control coreboot and Intel SoC features
dynamically. BIOS reads control information from OEM Section in the
Descriptor Region and control the developer selected features.
With the feature, debug team can control the selected SoC and coreboot
features without rebuilding coreboot.

In order to enable the feature, SOC_INTEL_COMMON_BLOCK_DEBUG_FEATURE has
to be selcted from mainboard.

The OEM section starts from offset:0xf00 till end of the Descriptor
Region(0xfff).

BUG=b:153410586
BRANCH=None
TEST=Verified CSE firmware update functionality on brya

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I5ba40926bd9ad909654f152e48cdd648b28afd62
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2022-04-06 17:32:31 +00:00
Michał Kopeć bd656b4e4c superiotool/ite: add IT8625E EC registers
Add support for dumping ITE IT8625E Environmental Controller registers.

Values as per "IT8625E Preliminary Specification V0.3 (For D Version)".

Change-Id: I68aad90097206c6b8ef40075530c00809d9511e2
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63310
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-04-06 16:28:53 +00:00
Sean Rhodes 36b6e79f1c ec/starlabs/merlin: Add EC related files for Cezanne boards
Add EC memory layout and Q events for AMD Cezanne based boards, "Byte"
and "Fighter", which both use the ITE 5570E.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I3f837263d24e6b642cf33fd2995d8c90529706f6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62994
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-06 16:21:31 +00:00
Sean Rhodes e8b090c509 ec/starlabs/merlin: Correct Q event for CPU DN SPEED
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ieea1c8d0923f6ea6b13cf76525c9c4c686a92c40
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-06 16:21:03 +00:00
Sean Rhodes f03c372a6e mb/starlabs/labtop: Remove subsystem device ID
Remove the subsystem device ID for HDA devices, so that the correct
Intel [8086:xxxx] is used. This was an old workaround for Windows
that is no longer required with a new driver.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I50c03a2df06af3ef1939afd0739e083a9056557f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63348
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-06 16:20:51 +00:00
Uwe Poeche e9b417c0a0 soc/intel/ehl/fsp_params: Set Intel Speed Step (Eist) from devicetree
This patch provides the set value for intel speed step in devicetree
for FSPS. Before that in case of not set value in device tree the
default value of disabled was overwritten by default enabled of FSP.

Test: mainboard/siemens/mc_ehl/variants/mc_ehl1
Check status of Bit 16 in MSR 0x1a0 after boot.

Change-Id: I0a5ef4968a27978116c21ce35b3818c6b36e086f
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63352
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-06 16:20:27 +00:00
Arthur Heymans ca74d7e65b drivers/intel/fsp1_1: Rename hob finding functions
The hob finding functions are never looped over so there is no point
for the 'next' inside their name.

Change-Id: I18e452d313612ba14edda479d43f2797f6c84034
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63204
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-06 16:20:06 +00:00
John 2bcc5f39c1 soc/intel/common: Add IOE SBI access for TCSS functions
Meteor Lake has the IOE Die for TCSS. This change adds IOE SBI access
for TCSS pad configuration and Thunderbolt authentication.

BUG=b:213574324
TEST=Build platforms coreboot images successfully.

Change-Id: I324242a018fb47207dd426fc8acd103f677d5cab
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63128
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-04-06 16:19:36 +00:00
John 848b42558c soc/intel/common: Abstract the common TCSS functions
This change abstracts the common TCSS functions for pad configuration
and Thunderbolt authentication.

BUG=b:213574324
TEST=Build platforms coreboot images successfully.

Change-Id: I3302aabfb5f540c41da6359f11376b4202c6310b
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62723
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-04-06 16:19:18 +00:00
Kyösti Mälkki 740eee5eec ChromeOS: Drop filling ECFW_RW/RO state in CNVS
This field was never meant to be filled out by coreboot, because it
can't know what the right value for this will be by the time the OS
is running, so anything coreboot could fill in here is premature.

This field is only read by the chromeos-specific `crossystem` utility,
not by kernel code, so if one does not run through depthcharge there'll
be many more broken assumptions in CNVS anyway.

Change-Id: Ia56b3a3fc82f1b8247a6ee512fe960e9d3d87585
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63290
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-06 09:31:25 +00:00
Kyösti Mälkki e50bb8fc9e ChromeOS: Add legacy mainboard_ec_running_ro()
Motivation is to have mainboard_chromeos_acpi_generate()
do nothing else than fill ACPI \OIPG package.

Change-Id: I3cb95268424dc27f8c1e26b3d34eff1a7b8eab7f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58896
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-04-06 09:21:46 +00:00
Zheng Bao 487d04540b amdfwtool: Add a macro to set explicitly second gen for old SOCs
It is more reasonable than getting the value from memset.

For the reserved bits, keep them as they were for old SOCs.

Change-Id: I65caa11e835d2ff52bec4b8904057bbced434891
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-05 17:45:58 +00:00
Chris.Wang ac43324211 mb/google/guybrush/var/dewatt: Correct samsung part number value in SPD data
The value at offset 329 should be:
0x4B -> "K" not 0x48 -> "H" in ASCII code.

BUG=b:224884904
TEST=Build, confirm the part number is matched the corresponding parts

Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I35dc5f036a29cdf4763389b6425df99ff63bbfa0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63354
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Robert Zieba <robertzieba@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-04-05 16:45:49 +00:00
Robert Zieba 39e6cc5981 mb/google/guybrush/var/dewatt: Override SPD file for Samsung parts
K4U6E3S4AB-MGCL and K4UBE3D4AB-MGCL require special SPD files. This
commit overrides the default SPD files used for these parts

BUG=b:224884904
TEST=Verified that Dewatt SKU1 and SKU3 boot with changes

Signed-off-by: Robert Zieba <robertzieba@google.com>
Change-Id: Ibd08f109765933640ea3d0ad442873c30fa14bc4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63282
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-04-05 14:51:32 +00:00
Robert Zieba 255b1fb38b util/spd_tools: Add ability to override SPD file for parts
This commit adds the ability to override the SPD file that is used for a
specific part.

BUG=b:224884904
TEST=Verified that generated makefile uses specified SPD file and that
it remains unchanged when this capability is not used

Signed-off-by: Robert Zieba <robertzieba@google.com>
Change-Id: I078dd04fead2bf19f53bc6ca8295187d439adc20
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63281
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-04-05 14:50:56 +00:00
Varshit B Pandya be1a050772 soc/intel/alderlake: Add HID for DPTF Battery Participant
HID is defined in Intel Dynamic Tuning revision 1.3.13 (Doc no: 541817)

BUG=b:205928013
TEST=Build, boot brya0 and dump SSDT to check BAT1 device HID

Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: Ie1fff53f938a5f13423e360c24c7181fa7613492
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63316
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-04-05 14:49:07 +00:00
Varshit B Pandya 170a76caa7 drivers/intel/dptf: Add support for Battery participant
As per Intel Dynamic Tuning revision 1.3.13 (Doc no: 541817) add
support for TBAT device under \_SB.DPTF

BUG=b:205928013
TEST=Build, boot brya0 and dump SSDT to check TBAT device

Device (TBAT)
{
    Name (_HID, "INTC1061")  // _HID: Hardware ID
    Name (_UID, "TBAT")  // _UID: Unique ID
    Name (_STR, "Battery Participant")  // _STR: Description String
    Name (PTYP, 0xC)
    Method (_STA, 0, NotSerialized)  // _STA: Status
    {
        Return (0x0F)
    }
}

Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: I9104318fd838f30253ab1eeac4e212b3b917f516
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63315
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-04-05 14:48:47 +00:00
Angel Pons 1e124b94fc drivers/wifi/generic/acpi.c: NULL-check pointers before dereferencing
Checking whether a pointer is NULL after it has been dereferenced makes
zero sense. Make sure the `wifi_ssdt_write_properties()` function never
gets invoked with a NULL argument for the `dev` parameter, and simplify
the logic around the `is_cnvi_ddr_rfim_enabled` variable accordingly.

Change-Id: I3fbc9565e7e9b4e1c14a68f6a5fd779577045236
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63340
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-04 23:56:15 +00:00
Sean Rhodes 32ec4526a0 ec/starlabs/merlin: Remove comment about OPWE
OPWE offset didn't exist, but it does now so remove the comment about
this.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I4a1310c779002dfb00d01a22437ea223bb406609
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-04 21:54:45 +00:00
Sean Rhodes 32528976ff mb/starlabs/lite: Add Lite Mk IV variant
Tested using upstream edk2:
* Windows 10
* Ubuntu 20.04
* MX Linux 19.4
* Manjaro 21

No known issues.

https://starlabs.systems/pages/starlite-specification

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Id1cf2846a139004e9bec7bb27e9afe07b7e6f64f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-04 21:54:24 +00:00
Frans Hendriks ae2b79037f src/mb/facebook/monolith: Remove IGNORE_IASL_MISSING_DEPENDENCY
CB:63244 solved the missing dependency on _PRS

The config IGNORE_IASL_MISSING_DEPENDENCY can be removed.

BUG=N/A
TEST=build facebook monolith and verify no IASL warning is reported.

Change-Id: I0d7c99e69d56aa8ebe08b52c91ef800390263185
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63245
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-04 19:09:15 +00:00