There is no board named X11SSH+-TF.
Change-Id: Ide01a8d59c09747dfe7d59fd9e17bd5194fb14e4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35445
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
In interactive payloads, the USB stack's poll procedure is implicitly
called from the UI loop. Since all USB control transfers are handled
synchronously, polling hubs with these slows the UI significantly down.
So switch to interrupt transfers that are done asynchronously and only
perform control transfers when the hub reported a status change.
We use the interrupt endpoint's max packet size instead of the theo-
retical transfer length of `(bNrPorts + 1) / 8` as Linux' code mentions
hubs that return too much data.
Change-Id: I5af02d63e4b8e1451b160b77f3611b93658a7a48
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/18499
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Add SKU#18 to config power sequence below:
GPIOs related to power sequnce are
GPIO_67 - EN_PP3300
GPIO_117 - FULL_CARD_POWER_ON_OFF
GPIO_161 - PLT_RST_LTE_L
1. Power on: GPIO_67 -> 0ms -> GPIO_117 -> 30ms -> GPIO_161
2. Power off: GPIO_161 -> 30ms -> GPIO_117 -> 100ms -> GPIO_67
3. Power reset:
- keep GPIO_67 and GPIO_117 high and
- pull down GPIO_161 for 30ms then release it.
BUG=b:134854577,b:137033609
BRANCH=octopus
TEST=build
Change-Id: I58e07518f6daaf608684c9fa1b1c88fc592ea117
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35442
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This change adds SPD files for Drallion. Use spd_index
matrix to correspond mem_id. This can save the dummy spd index
to reduce the size of SPD.bin.
BUG=b:139397313
TEST=Compile successfully
Change-Id: I2f7e75fdbca4183bcd730e40fef4bfe280ab900b
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35346
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
../bd82x6x/early_usb.c: While ibexpeak needs an equivalent of this
code, it is not currently hooked up.
../common/gpio.c: Already linked in common/Makefile.inc
Change-Id: I980601e2302f2c412e823fef5fb9a69b9e151322
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35437
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Found by Coverity Scan #1405310
Change-Id: I53146e7fc402500effc63ce276ecfce4d72a4f7f
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35433
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some T430s variants have a Thunderbolt controller wired to PCIe port
The controller hotplugs itself to the chipset when a downstream device
is hotplugged into it, so the hotplug capability should be enabled on
PCIe port #5.
TODO: find the correct gpio pin to detect the Thunderbolt controller
at runtime.
There are 3 variants of mainboard for Thinkpad T430s: Basic type
(Wistron LSN-4 11263-1), Boards with an additional discreet GPU,
Boards with an additional TB controller (Wistron LSN-4 11271-1),
each of which has a different schematic.
The gpio27 on the last type is set as set as GPIO-INPUT, compared
with GPIO-OUTPUT-HIGH on the basic type boards.
Change-Id: I61f41db100f398069e50e2da8a378b3a8d1c84bf
Signed-off-by: Bill XIE <persmule@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31631
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This Kconfig symbol is set at a default of 36 in cpu/x86 and is now
only used in the romcc bootblock to set up caching to upgrade the
microcode. It's not mainboard specific.
Change-Id: I29d3a8308025e586a823603f8d6edafd30cb9d95
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35436
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fix regression after commit
21160a7 Add definition for ENV_ROMSTAGE_OR_BEFORE to <rules.h>
Builds with VBOOT_STARTS_IN_ROMSTAGE=y would evaluate
ENV_ROMSTAGE_OR_BEFORE incorrectly for verstage-class.
Follow-up changes for CBMEM console and timestamps, where
defined(__PRE_RAM__) tests are replaced, are likely to have
caused regressions such that VBOOT console and timestamps
are missing.
Change-Id: Idc274409c495efea95eeecd0538b2f8b847970ad
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35408
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
For pcengines/apu2 variants we do not even send
DRAM ready message to PSP.
Possibly some GFX/DRM depends of running PSP but
these devices are headless. And we don't support
fTPM inside PSP either.
Reduces blob footprint in SPI from 466 KiB to 234KiB.
Change-Id: I803722171cba9b3601fb0b4a2c0e984566f435ab
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31075
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Move it above 'AGESA' to increase the maximum
continuous free space in CBFS from 5.3 MiB to 5.8 MiB.
Also fixes build for cases where CBFS_SIZE < ROM_SIZE,
thus allowing FMAP regions.
NOTE: Due to off-by-one error in binaryPI, offset
0xFFFA0000 that amdfwtool advertises fails
for xHCI firmware loading.
Change-Id: Ic78520f4248f0943769e66a8825911c0ddcc368c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
To support gpio reset SoC, we need to pass the reset gpio parameter to
BL31.
BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui and ATF(BL31) can get this parameter.
Change-Id: Iefa70dc0714a9283a79f97d475b07ac047f5f3b0
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31605
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
As discussed on the mailing list and voted upon, the coreboot project
is going to move the majority of copyrights out of the headers and into
an AUTHORS file. This will happen a bit at a time, as we'll be unifying
license headers at the same time.
Additional cleanup - Unify "Inc" to "Inc." and "LLC." to "LLC"
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ie03a3ce1f6085494bd5f38da76e2467970cf301a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35430
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
We generally try to stay away from ascribing attributes to (future)
devs. "Rookie guide" refers to the reader, while "tutorial" refers
to the material.
In the same spirit, move from "lessons" to "parts". It's not school :-)
Change-Id: I11a69a2a05ba9a0bc48f8bf62463d9585da043ec
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35425
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
It's been some time and there are 1420 new commits. Including one that
allows reproducible builds \o/ and one that breaks building with empty
$(CC) :-/
Change-Id: I5e81d5a2f1018481b9103fc5a1f4b8c72fb9deec
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30679
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
send_heci_reset_req_message() is defined in multiple places,
hence move it to common code.
TEST=Verified on CMLRVP/Hatch/Soraka/Bobba/Dragon Egg boards.
Change-Id: I691fc0610356ef1f64ffa7cc4fe7a39b1344cc16
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35228
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set BL31 platform to mt8183 to link with ARM Trusted Firmware.
BUG=b:80501386
BRANCH=none
Test=Boots correctly on Kukui with more patches in ATF.
Change-Id: Ia988d2b4ed646027c04c7c6ff0e50ed7a0b14da3
Signed-off-by: kenny liang <kenny.liang@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This change overrides USB port settings for kohaku.
Some port settings are same with baseboard, but I'd like to describe all
settings here to be aware of current setting and usage of USB ports on
kohaku.
BUG=none
BRANCH=none
TEST=built and measured SI of USB ports internally
Change-Id: I5ac05485d1cd94416e5a0aecf7fa6769bd7c9e84
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35236
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This adds SATA parameters for SpinUp, HotPlug and TestMode to the
Skylake FSP 2.0 interface.
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I7ba67879b78c2cb0fd0b0ce832140b213edd5884
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35186
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Make microcode lib available in bootblock. Now that microcode.c is compiled
in bootlock no need to include it explicitly, hence remove its references.
Change-Id: I419da6af70222902e3ca39fc2133d5dc8558e053
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35278
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the 8086:041e integrated graphics controller.
Adding the definition makes the Intel HD 4400 graphics
recognized by inteltool.
It is found on the ark page of e.g. the Intel i3-4130 CPU.
Change-Id: I6d6b2eaa7cc5aa3912592ed3fcb73751b224eede
Signed-off-by: Christoph Pomaska <sellerie@aufmachen.jetzt>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34588
Reviewed-by: Mimoja <coreboot@mimoja.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Every vga init implementation needs to cache the framebuffer state
to be able to fill the lb_framebuffer struct later on in the
fill_lb_framebuffer call. Showing the bootsplash afterwards
guarantees to have the same interface into all the vga drivers.
This is by far from ideal, as it only allows for a single driver at
compile-time and should be adapted in the future.
It was tested on the wip razer blade stealth using vgabios @ 1280x1024
and also in Qemu @ 1280x1024.
By default the qemu framebuffer will be initialized in 800x600@32.
This can be overwriten by configuration by setting
CONFIG_DRIVERS_EMULATION_QEMU_BOCHS_{X,Y}RES .
Change-Id: I4bec06d22423627e8f429c4b47e0dc9920f1464e
Signed-off-by: Johanna Schander <coreboot@mimoja.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34599
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The PCO_HDA0 device contains the "ATI" vendor ID 0x1002 and was
incorrectly added to this file. It isn't anticipated that the
device will need special handling, so remove it from the list
of supported IDs.
Change-Id: I306a806dc510e3a4ee3d9c0663306dc93b1d936d
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Information based on superiotool dump.
Change-Id: I24ae9b1a7eab3095518341354544efe613912a6a
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35386
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Enables and configures GPIOs in the NCT6791D chip. The values for
registers taken from the superiotool dump.
Change-Id: I5968a6c20cc013697d64bfbe4fc2e7b2390b72b0
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35378
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Angel Pons