Commit Graph

37677 Commits

Author SHA1 Message Date
Martin Roth a266299490 util/docker: Update agent-root to node-root for jenkins
Jenkins has changed the name of the build directory, so it's not
currently building out of memory, it's writing to the SSD. This
changes the build back to tmpfs.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Iefcf53757862feb2025aa5696f9f5dbce9dd70dd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46803
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-10-27 10:09:06 +00:00
Martin Roth 7d520ff98f util/docker: Add tests to coreboot-sdk build process
This tests some of the basic targets that coreboot-sdk needs to be
able to run.

I was running most of these tests manually after creating the sdk
image, but adding it into the Dockerfile makes sure they get run.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I0d4a2ad82042733a7966edb8ccf927676618977c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46802
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-10-27 10:08:45 +00:00
Martin Roth ebeec5aed3 util/docker: Update coreboot-sdk consolidate coreboot build
Because docker saves a container for every run command, by breaking
the coreboot build into 3 commands, it greatly increased the size of
the docker containers needed.  When combined as one run command, the
coreboot repo that is downloaded, along with the coreboot test build
are deleted before the container is created.  Since those directories
are deleted in a later run command, they don't even make it into the
final container, and just force coreboot-sdk users to download extra
data for no reason.

While splitting the build may help with debugging failures when
creating the docker container, that debugging can be done locally by
splitting up a working copy.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ia28ee4e22c0a76dc45343755c45678795308adca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46801
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-10-27 10:07:20 +00:00
Martin Roth b86d2b0935 util/docker: Update coreboot-sdk to set python2 as default
Even though both python2 and python3 are now installed to the SDK, the
default python program is not.  This sets the default to python2.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I4220c316df86cb2481143a79fadb70fc734e6879
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46800
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-10-27 10:06:17 +00:00
Martin Roth bd8e6dd2ca util/docker: Update coreboot-sdk with additional tools
- cscope: Run cscope targets
- ctags: Run ctags targets
- pbzip2: Allow compression on all cpu cores

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I31ca45fcc5880f2b0346ca3f7d36a71ae18da979
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-10-27 10:06:00 +00:00
Angel Pons 99af210456 mb/google/auron: Prepare devicetree for PCH split
Tested with BUILD_TIMELESS=1, all variants remain identical.

Change-Id: I2b088b36c8e9ff9cbd47d625b14fc45ebd96532a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46702
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-27 10:05:35 +00:00
Martin Roth ce19f4f8ad util/testing: Remove test for util/broadcom/secimage
util/broadcom/secimage was removed in commit aea00f496b, so don't
try to test it anymore.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ibcc018a6b8ed4ecd407f2dc374cec62900920a92
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46805
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-10-27 10:05:15 +00:00
Ren Kuo 12b376c87f mb/google/dedede/var/magolor: Configure I2C high and low time
Configure the I2C bus high and low time for all enabled I2C buses.

BUG=b:168783630
TEST=Measured the I2C bus frequency reduce to 387 KHz.

Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Change-Id: I9f5b81815f86db7bdcea95a95b9c9b235b4a34b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46613
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-27 06:13:43 +00:00
Jonathan Zhang 8f594b7319 cpu/x86/mtrr: fix OVERFLOW_BEFORE_WIDEN
Integer handling issues:
Potentially overflowing expression "1 << size_msb" with type "int"
(32 bits, signed) is evaluated using 32-bit arithmetic, and then
used in a context that expects an expression of type "uint64_t"
(64 bits, unsigned).

Fixes: CID 1435825 and 1435826

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: If859521b44d9ec3ea744c751501b75d24e3b69e8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46711
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-27 06:13:32 +00:00
Kevin Chiu bd21476f99 mb/google/kukui: change Jacuzzi followers LCMID to fixed value
The LCM ID is not really used on Jacuzzi followers and the reference
design expects ADC to return 0. However, there were hardware design
issues so the returned value became unexpected numbers.

 - Juniper and Kappa returns 1.
 - Burnet and Esche returns 1 on normal boot, and 0 on recovery boot.
 - Cerise and Stern usually returns 0, and sometimes 1.

To fix that, we are changing LCM ID to fixed value for Jacuzzi followers.

BUG=b:170916885,b:171365301
BRANCH=kukui
TEST=1. emerge-jacuzzi coreboot
     2. check burnet/esche skuid correctly

Change-Id: I3b43b9153315ec65e9168c4e84ea844dff14d446
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46442
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-10-27 04:15:46 +00:00
Nick Chen 955ce24afc mb/google/volteer: Add a DPTF policy for Eldrid
1. Enable dptf feature and remove fan control part from overridetree.cb
2. Update tcc offset to 5
3. Follow thermal validation and update PL2 max_power to 51

BUG=b:167931578, b:170357248

Signed-off-by: Nick Chen <nick_xr_chen@wistron.corp-partner.google.com>
Change-Id: I99e429b90ed7de08385fe51ca742865b1266eef9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45860
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-26 15:24:04 +00:00
Jakub Czapiga 43439f6d49 lib/edid: Add missing name descriptor presence flag
EDID parser internal flag c->has_name_descriptor
was never set. It was causing decode_edid() function
to return NON_CONFORMANT instead of CONFORMANT even when
EDID frame was correct.

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: Ifdc723b892a0885cfca08dab1a5ef961463da289
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46694
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-26 13:28:41 +00:00
Julius Werner 11298542cd cbfstool: Don't build unneeded commonlib sources
These sources are built but not used by cbfstool. The only .c file in
commonlib/ it really needs is fsp_relocate.c. Get rid of the others.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I6ebbb4161874f6279b6dbaffe7c3144226a6f9b9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46253
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-26 06:59:53 +00:00
Julius Werner 4a30d42c4a vboot: Disable vboot functions in SMM
SMM does not have access to CBMEM and therefore cannot access any
persistent state like the vboot context. This makes it impossible to
query vboot state like the developer mode switch or the currently active
RW CBFS. However some code (namely the PC80 option table) does CBFS
accesses in SMM. This is currently worked around by directly using
cbfs_locate_file_in_region() with the COREBOOT region. By disabling
vboot functions explicitly in SMM, we can get rid of that and use normal
CBFS APIs in this code.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I4b1baa73681fc138771ad8384d12c0a04b605377
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-10-26 06:58:54 +00:00
Nico Huber d9e543a5f9 libpayload/keyboard: Use `bool` as return type
Use `bool` whenever `0` was used to indicate an error. The mixing of
different types for return values was mildly confusing and potentially
dangerous with the i8042 API close by that uses `0` for success.

Change-Id: I876bb5076c4921f36e3438f359be8ac4c09248cc
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46723
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-26 06:57:47 +00:00
Nico Huber f56d65266c libpayload/curses: Use <stdbool.h>
Change-Id: I35ef7c55fc6bcfb9c51a711a8e238f0970fd4ad4
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-26 06:57:21 +00:00
Nico Huber bfa46e25e0 libpayload: Add <stdbool.h>
Change-Id: I972c78c5da4136bc61e78fcbb52d7d162cc1b698
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46721
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-26 06:57:06 +00:00
Stefan Reinauer 3a7825983c ectool: Don't ignore fgets return code
Change-Id: I12dc449e06dee31b4b0811ab23c6e8635cf31512
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46667
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-26 06:56:56 +00:00
Stefan Reinauer 9d50efe19d ectool: Add newline to warning message
Cosmetic fix:

$ sudo ./ectool -p
Cannot get EC ports from /proc/ioports, fallback to default.EC RAM:

Change-Id: Icc2b5bbbbfe7685e4fe512af029ce00b33a26daa
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-26 06:56:49 +00:00
Stefan Reinauer f3b1a53858 inteltool: Only use real graphics devices
Right now IGD is hard coded to 0:2.0 and if that
device is there, it is blindly used, even if it is
not a graphics device. Look at the PCI class to make
sure we're not using the wrong device.

Change-Id: Ia7f52071bd202e2960faba0f46e4fa5e14ad65f8
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46673
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-26 06:56:36 +00:00
Stefan Reinauer 91893ee785 inteltool: initial Hewitt Lake support
Change-Id: Ifed43d058c70f75d88e9f4b2b07527782ebcbac5
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-26 06:56:26 +00:00
Elyes HAOUAS 28b68ae4fe soc/amd/picasso/acpi: Convert to ASL 2.0 syntax
Change-Id: I1cabe0f55ec55a84f8e9028565be69c9dd997e7c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-26 06:56:00 +00:00
Jakub Czapiga 466a378b9a tests: Add lib/imd-test test case
Implement unit tests for src/lib/imd.c module.

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Signed-off-by: Anna Karas <aka@semihalf.com>
Signed-off-by: Jan Dabros <jsd@semihalf.com>
Change-Id: I3902f8638669440144064ce0e3756918338f4068
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46457
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-26 06:55:46 +00:00
Jakub Czapiga 05fa5b2450 tests: Add test region and symbol macros to <tests/test.h>
Some modules require and operate on memory regions and symbols.
This macros systematize how they are defined in testing code.

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I314028c201732416bb3d5446a4c8585e055073e3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46684
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-10-26 06:55:40 +00:00
Karthikeyan Ramasubramanian 468c46df25 Revert "soc/intel/jasperlake: Allow mainboard to override chip configuration"
This reverts commit 5acea15d63. This
change got accidentally merged. There is no need for mainboard to
override chip configuration.

BUG=None
TEST=Build and boot Drawlat to OS.

Change-Id: I166ba7e5ee50a6329032eae8e17b9a554b094e2e
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46653
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-26 06:55:18 +00:00
Karthikeyan Ramasubramanian b11b731e80 Revert "mb/google/dedede: Add mainboard acpi support for GPIO PM configuration"
This reverts commit 214c719eed.
CB:45857 overrides the GPIO PM configuration if Cr50 does not support
long interrupt pulse width. More recent Cr50 Firmware versions support
long pulse width and hence the GPIO PM can take the default
configuration.

BUG=None
TEST=Build and boot Drawlat to OS. Ensured that 200 iterations of
suspend/resume sequence, warm and cold reboot cycles each are
successful.

Change-Id: I8e3be42cd82fd3ae919d23d6f19c84a90b9c737a
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46652
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Evan Green <evgreen@chromium.org>
2020-10-26 06:55:09 +00:00
Tim Wawrzynczak 7c80de6328 ec/google/chromeec: Update ec_commands.h
This change copies ec_commands.h directly from the Chromium OS EC repo
at SHA edd8b73e8, with the exception of changing the copyright header
to SPDX format.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I97bdb12dd561bd95746cc2761397aa7406326e12
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45937
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-26 06:54:54 +00:00
Tim Wawrzynczak ba4a4909a8 sconfig: Split up sconfig-generated static.h
Currently sconfig generates a `static.h` to accompany
`static.c`. However, some payloads may decide they would like to consume
the FW_CONFIG macros as well. The current state of `static.h` makes this
impossible (relying on `device/device.h`).

This patch splits up `static.h` into 3 files: `static.h,
`static_devices.h`, and `static_fw_config.h`. `static.h` simply includes
the other two `.h` files to ensure no changes are needed to other
code. `static_devices.h` contains the extern'd definitions of the device
names recently introduced to sconfig.  `static_fw_config.h` contains the
FW_CONFIG_FIELD_* macros only, which makes it easily consumable by a
payload which wishes to use FW_CONFIG.

Also refactor the generation of all these output files, as the code was
getting messy.

Change-Id: Ie0f4520ee055528c7be84d1d1e2dcea113ea8b5f
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45667
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-10-26 06:54:16 +00:00
Morgan Jang 8ae391d199 arch/x86/smbios: Populate SMBIOS type 7 with cache information
SMBIOS has a field to display the cache size, which is currently
set to UNKNOWN unconditionally, multiply the cache size of L1 and L2
by the number of cores.

TEST=Execute "dmidecode -t 7" to check if the cache information
is correct for Deltalake platform

Change-Id: Ieeb5d3346454ffb2291613dc2aa24b31d10c2e04
Signed-off-by: Morgan Jang <Morgan_Jang@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46068
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-26 06:54:04 +00:00
Elyes HAOUAS 8ccc8fdf26 sb/amd/*/*/pci_devs.h: Reduce the difference
Also add missing <device/pci_def.h>

Change-Id: I227f0c2a4ccb486f1d5560e3f64bc6208a456d68
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45894
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2020-10-26 06:53:28 +00:00
Elyes HAOUAS 0141f0d6b8 sb/amd/*/*/smbus.h: Make 'smbus.h' uniform
Reformat 'smbus.h' files and add missing <stdint.h>.

Change-Id: If78f483ca8ad2e3cffe60e22948dc8150cce3664
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45892
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2020-10-26 06:53:18 +00:00
Johnny Lin e61391738f mb/ocp/deltalake: Override coreboot log level via VPD
Tested=On OCP Delta Lake, log level can be changed via VPD.

Change-Id: I36d4b01b6fb6acc726749641df089cb3f9a4dc3e
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45326
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2020-10-26 06:53:06 +00:00
Michael Niewöhner e874b1c179 cpu/intel/common: implement the two missing CPPC v2 autonomous registers
This implements the two missing registers for the CPPC Hardware
Autonomous mode (HWP) to the CPPC v2 package.

The right values can be determined via Intel SDM and the ACPI 6.3 spec.

Test: dumped SSDT from Supermicro X11SSM-F and checked decompiled
version

Change-Id: I7e2f4e4ae6a0fdb57204538bd62ead97cb540e91
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46463
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Matt Delco <delco@chromium.org>
2020-10-26 06:52:08 +00:00
Michael Niewöhner 6f1754d090 soc/intel/icl: enable common CPU code
Enable CPU_INTEL_COMMON to make common CPU code available to CNL, which
gets used in CB:45535 and CB:45536 for CPPC entries generation.

Note: This also retrieves the VMX Kconfig and enables it by default,
like done for SKL and CNL already.

Since FSP always set the feature config lock, SET_IA32_FC_LOCK_BIT gets
selected statically by the SoC to reflect this in menuconfig.

Change-Id: I58e86021687fc0a836324f70071f7ea80242b3cb
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45826
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-26 06:51:53 +00:00
Michael Niewöhner a64b4f4548 mb/*,soc/intel: drop the obsolete dt option `speed_shift_enable`
The dt option `speed_shift_enable` is obsolete now. Drop it.

Change-Id: I5ac3b8efe37aedd442962234478fcdce675bf105
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46462
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-10-26 06:51:42 +00:00
Michael Niewöhner d5a45470c8 soc/intel/skl: replace conditional on dt option reading CPUID for CPPC
Check ISST (Intel SpeedShift) availability via CPUID.06H:EAX[7], instead
of relying on the devicetree option `speed_shift_enable`, that is going
to be dropped.

Test: GCPC and _CPC entries still get generated on Supermicro X11SSM-F

Change-Id: I5f9bf09385627fb6a1d8e566a80370f7ddd8605e
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46461
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-26 06:49:40 +00:00
Michael Niewöhner 6267cc523b soc/intel: drop unneeded ISST configuration code
The code configuring ISST (Intel SpeedShift Technology) sets the ISST
capability bits in CPUID.06H:EAX. It does *not* activate HWP (Hardware
P-States), which shall be done by the OS only.

Since the capability is enabled by default (opt-out), there is nothing
to do for us in the enabled-case. Practically speaking, there is no
value at all in disabling the capability, since one can configure the
OS to not enable HWP if that is desired.

The two other bits for EPP and HWP interrupt that were set by the code
are not set anymore, too. It was tested, on three platforms so far
(CML-U, KBL-H, SKL-U), that these are set as well by default in the
MSRs reset value (0x1cc0).

To reduce complexity and duplicated code without actual benefit, this
code gets dropped. The remaining dt option will be dropped in CB:46462.

Test: Linux on Supermicro X11SSM-F detects and enables HWP:
[    0.415017] intel_pstate: HWP enabled

Change-Id: I952720cf1de78b00b1bf749f10e9c0acd6ecb6b7
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46460
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-26 06:49:22 +00:00
Benjamin Doron 0310279411 util/intelp2m: Fix typos
Change-Id: I7210fb44ed54d365181ca23c6b92d2269dc8a697
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45007
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-26 06:49:03 +00:00
Nico Huber 308c1b7976 console/init: Drop CONSOLE_LEVEL_CONST
We limited the configurability of the debug level to stages that have
a `.data` section. This is not really a requirement, because a `.bss`
section should suffice and we always have that now.

We want to make the debug level configurable early but also want to
avoid calling get_option() early, as an error therein could result
in no console output at all. Hence, we compromise and start using
get_option() from the second console init on.

TEST=Booted QEMU once with `debug_level=Debug` and once with
     `debug_level=Notice`. On the second boot, most messages
     vanished for all stages but the bootblock.

Change-Id: I11484fc32dcbba8d31772bd0b82785f17b2fba11
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45765
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-26 06:48:45 +00:00
Sheng-Liang Pan e836d11214 mb/google/volteer/var/voxel: enable GPP_D17 for FCAM_PWR
Enable front camera power in ramstage.

BUG=b:169170677
BRANCH=volteer
TEST="emerge-volteer coreboot" compiles successfully.

Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: I8b5a9a8333ed518883aa3664a115a4ba2e8a0218
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46618
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: YH Lin <yueherngl@google.com>
2020-10-26 06:48:12 +00:00
Frans Hendriks 4622a2fe82 security/tpm/tspi/crtm: Add line break to debug messages
Add line break at debug messages.

Tested on Facebook FBG1701

Change-Id: Idbfcd6ce7139efcb79e2980b366937e9fdcb3a4e
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46659
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-26 06:47:20 +00:00
Eric Lai 6c02ca6962 mb/google/octopus/var/fleex: Add goodix touch pad support
Add goodix touch pad as below:
HWID : GXTP7288
CID : PNP0C50
I2C address : 0x2C
I2C speed : 400Khz
HID Descriptor Address : 0x20

BUG=b:171351666
BRANCH=octopus
TEST=build image and verify goodix touch pad working.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Idb4f8d3aff09712dcc98c8ae0c9ae30dc4049e29
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46614
Reviewed-by: Marco Chen <marcochen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-26 06:47:10 +00:00
Patrick Rudolph 90f01ece00 soc/intel/common/block/smbus: Add define for I2C_EN
Change-Id: Iecccc363f492985555019f2390bd53472a000ba9
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-26 06:46:59 +00:00
Patrick Rudolph 2c70708a78 soc/intel/common/block/smbus: Add Cannonpoint PCH-H PCI ID
This is required to make sure the defined SMBUS_BASE address is valid
even after PCI enumeration.

Tested on Prodrive Hermes.

Change-Id: Ibd40e556fd890000836d23682d4e9e3aa5200c54
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46562
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-26 06:46:39 +00:00
Tim Chu 5ec02680eb mb/ocp/deltalake: Use BMC version to represent ec version
In deltalake, there's no embedded controller and BMC version is
used to represent ec version.

TEST=Build with CB:45138 and CB:46070
Execute "dmidecode -t 0" to check if the firmware version is correct

Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: I388efd749170f0ebbb4dd4d32199675d92cc018e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46071
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-26 06:46:29 +00:00
Tim Chu 278ad21fa9 src/drivers/ipmi: Add function to get BMC revision
Provide a way to get BMC revision.

Tested=On OCP Delta Lake, function can get BMC revision well.

Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: Iaaa4e8bf181a38452b53c83a762c7b648e95e643
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46070
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-10-26 06:46:17 +00:00
Amanda Huang cbcd8a02fc mb/google/octopus/var/fleex: Add new SKU for LTE touch
New SKU ID 5 is used for LTE touch SKU. This patch does LTE power off
for LTE sku and only use Wifi SAR table for non-LTE sku.

BUG=b:168001586
BRANCH=octopus
TEST=Check no SAR table can be loaded with sku id 4 and 5.

Change-Id: Ic0405d3e52aa813bbb1f350966a9e2825e595ce4
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46643
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-26 06:45:13 +00:00
Frank Wu fc66ab6959 mb/google/zork/vilboz: Enable SAR proximity sensor STH9324
BUG=b:161759253
BRANCH=firmware-zork-13434.B
TEST=emerge-zork coreboot chromeos-bootimage
firmware log:
\_SB.I2C2.SEMTECH SX9324: SAR Proximity Sensor at I2C: 02:28
kernel log:
INFO kernel: [   11.238644] sx932x i2c-STH9324:00: initial compensation success

Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I6294ce291365443dd1c4550ba75cb7f33481b889
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45565
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-26 06:44:58 +00:00
Elyes HAOUAS 92f46aaac7 src: Include <arch/io.h> when appropriate
Change-Id: I4077b9dfeeb2a9126c35bbdd3d14c52e55a5e87c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45404
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-26 06:44:40 +00:00
Eric Lai f209b18df3 mb/google/zork: Update style of check on cbi return values
Since google_chromeec_cbi_get_board_version and google_chromeec_cbi_get_fw_config both call cbi_get_unit32 and return 0 as success, non-zero as failure. Let's add more readability for the false condition.

BUG=None
TEST=check with empty CBI value

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ia49ac1ee35302f8f6afe8c0eb8e13afdf36c5b2b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46566
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-26 06:44:02 +00:00