access instead. That fails if the flash chip is not mapped completely.
If the read function is set in struct flashchip, use it for verification
as well.
This fixes verification of all SPI flash chips >512 kByte behind an
IT8716F flash translation chip.
"MX25L8005 found at physical address 0xfff00000.
Flash part is MX25L8005 (1024 KB).
Flash image seems to be a legacy BIOS. Disabling checks.
Verifying flash... VERIFIED."
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Harald Gutmann <harald.gutmann@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3070 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
readcnt==0 saves 10 seconds with the unconditional 10us delay, reducing
programming time for SST25VF016B to 40-45 secs.
Signed-off-by: Ronald Hoogenboom <hoogenboom30@zonnet.nl>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3068 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
are already in use, the patch uses 'R' (for release) and, of course,
'--version'.
Signed-off-by: Bernhard Walle <bernhard.walle@gmx.de>
Acked-by: Ulf Jordan <jordan@chalmers.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3067 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
patch is tested on actual hardware.
As per datasheet the ID should be 0x886? for those chips.
Not mentioned in the datasheet, but sensors-detect says
0x8853 is also possible. Also, the ASUS A8V-E Deluxe
(W83627EHF) has an ID of 0x8854 (verified on actual hardware).
So assume all 0x88?? IDs to mean W83627EHF/EF/EHG/EG.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3063 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
I have test that on my board, it works ;)
Signed-off-by: Bingxun Shi <bingxunshi@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3062 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Due to the automatic nature of this update, I am self-acking. It worked in
abuild.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3053 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
After the patch [...] The line length is still below 80 characters.
Signed-off-by: Bernhard Walle <bernhard.walle@gmx.de>
Acked-by: Torsten Duwe <duwe@lst.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3045 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Straight from the data sheet, not tested.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3036 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
exactly the same ID. Improve model number printing.
Add EN29F002(A)(N)B support while I'm at it.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Markus Boas <bios@ryven.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3031 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
The continuation ID code does not go further than checking for IDs of
the type 0x7fXX, but does this for vendor and product ID. The current
published JEDEC spec has a list where the largest vendor ID is 7 bytes
long, but all leading bytes are 0x7f. The list will grow in the future,
and using a 64bit variable will not be enough anymore.
Besides that, it seems that the location of the ID byte after the first
continuation ID byte is very vendor specific, so we may have to revisit
that code some time in the future.
(Suggestion for a new encoding:
Use a two-byte data type for the ID, the lower byte contains the only
non-0x7f byte, the upper byte contains the number of 0x7f bytes used as
prefix, which is the bank number minus 1 the vendor ID appears in.)
Add support for EON EN29F002AT.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3030 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
(JEP106W), adds some device IDs and provides information about
non-conforming IDs.
The EON change is left to the patch adding EON chips.
This patch should have no effect on code generation.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3029 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
page size. Fix that. Page size is uniform 256 bytes for SPI.
A sector/block size field in struct flashchip would be nice, though.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3027 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
output is specified.
Pretty-print the chip status register (including block lock information)
for ST M25P family and Macronix MX25L family chips.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3026 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
M25P64, M25P128 to flashrom. ST M25P80 support is already there.
Not tested, but conforming to data sheets and double checked.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3012 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
with multiple possible opcodes from linear numbering at the end (_1, _2)
to include the opcode at the end (_60, _c7). That way, you only have to
take a short look at the data sheet and choose the right function by
appending the opcode listed in the data sheet.
No functional changes.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ward Vandewege <ward@gnu.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3009 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
PC97317 has SID = 0xdf. PC87371/PC97371 do not seem to exist.
Signed-off-by: Ulf Jordan <jordan@chalmers.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2999 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Also, s/0xFF80/0xFFC0/ in the Acorp 6A815EPD board-enable, as per
http://www.linuxbios.org/pipermail/linuxbios/2007-December/027750.html
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2997 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2995 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- Add missing contributors to the README.
- Drop obsolete -D option from manpage.
- Only list contributors who added non-trivial amounts of code as copyright
holders (and do not list those who merely provided register dump support
for Super I/Os). Those contributors are still listed in the README,
of course. See discussion in the thread starting at
http://www.linuxbios.org/pipermail/linuxbios/2007-October/025516.html
- Make a function static.
- Fix incorrect URL in code comment. Drop obsolete comments.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2992 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Attached is a patch that enables AMD Geode CS5536 chipset support. I
have tested it successfully on a MSM800 board from digital logic.
Signed-off-by: Lane Brooks <lbrooks@mit.edu>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2967 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Carl-Daniel Hailfinger