Commit Graph

48382 Commits

Author SHA1 Message Date
garmin chang 4e8a1ec565 soc/mediatek/mt8188: Add PLL and clock init support
Add PLL and clock init code, frequency meter and APIs for raising little
CPU/CCI frequency.

For usb clock setting, we also implement mt_pll_usb_clock_setting() to
enable usb clock for all ports.

TEST=build pass
BUG=b:233720142

Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
Change-Id: I03cb5a4c6fa5ddad7da6f955d0c6d0b3395503e9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65751
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-07-13 10:40:37 +00:00
Harsha B R c4ed1e82bb mb/google/nissa: Remove GPP_B11 PAD configuration
Remove the pad configuration for GPP_B11
as this is not used in Nereid/Nivviks

BUG=b:227694137

Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Change-Id: I3a213ffece75b9a706b96dc142a7e35c8b5973f6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65623
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-07-13 10:39:54 +00:00
Kapil Porwal 7581730b65 soc/intel/meteorlake: Use double digit GPIO pad numbers
Google uses two digit GPIO pad numbers for internal GPIO references
and Intel has updated their GPIO naming schemes too (see the GPIO
implementation worksheet #641238) so use double digit GPIO pad numbers.
Format -
"GPP_%c%02d", gpio_group, gpio_pad_num

e.g.
GPP_A0 -> GPP_A00,
GPP_V2 -> GPP_V02,
GPP_C9 -> GPP_C09 etc.

BUG=b:238196741
TEST=Able to build meteorlake based google/rex.

Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: Ieb7569c1a35b08c0970a604ec7b4b91e6179dd28
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65719
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-07-13 08:41:13 +00:00
Kapil Porwal a42ad2822b vc/intel/fsp2_0: Update partial headers to MTL.FSP2253.00
Update partial headers to MeteorLake FSP v2253.00

Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: If2d6c80bd35afd68588fef57e38064c5b1e1a888
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65707
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-07-13 08:40:39 +00:00
Felix Singer bb53f3091c docs/infra/services: Add Gerrit SSH host keys and fingerprints
Change-Id: Ic687594517e9dc8a7f3ea7047a5ec4448ed5a043
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65615
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
2022-07-12 22:41:33 +00:00
Felix Held 229f466891 doc/index: document the correct way to spell coreboot
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8e0c96dc4b68e60f9a36afb361c4d1c6f9742c31
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
2022-07-12 22:14:06 +00:00
Paul Menzel 42a7cd0d99 soc/samsung/exynos5420: Use int instead of char for count variable
This micro optimization of using unsigned char instead of unsigned
integer actually generates one more instruction.

    .LVL296:                                                        .LVL296:
    .L198:                                                          .L198:
            .loc 1 912 16 is_stmt 1 discriminator 1 view .LVU1740           .loc 1 912 16 is_stmt 1 discriminator 1 view .LVU1740
            uxtb    r2, r3                                        |         cmp     r7, r3
            cmp     r7, r2                                        <
            bhi     .L199                                                   bhi     .L199
            .loc 1 916 1 is_stmt 0 view .LVU1741                            .loc 1 916 1 is_stmt 0 view .LVU1741
            add     sp, sp, #36                                             add     sp, sp, #36
            .cfi_remember_state                                             .cfi_remember_state
            .cfi_def_cfa_offset 20                                          .cfi_def_cfa_offset 20
            @ sp needed                                                     @ sp needed
            pop     {r4, r5, r6, r7, pc}                                    pop     {r4, r5, r6, r7, pc}

Fix it, so nobody can copy that.

Change-Id: If5ffeacc7ac3c53a82b260cfb81ef7debc40034a
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65731
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-07-12 22:12:19 +00:00
Tim Crawford 5c2b5fcf2f util: Allow installing to a build root
Modify util Makefiles to allow installing to a build root specified by
DESTDIR. Allows using the `install` target for packaging.

Change-Id: I3a31ea0fde9922731e1621dcc8f94b2c1326c93c
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60540
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-07-12 22:11:35 +00:00
Rex-BC Chen 13c8d024c2 soc/mediatek: Add mt_pll_set_usb_clock() to enable usb clock
There are clock settings for usb in mt8195 and mt8188, so we add a new
function which is implemented in pll.c to do this.

TEST=build pass
BUG=b:233720142

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I40b358b197541bc5281645879553340059829db3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65750
Reviewed-by: Yidi Lin <yidilin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-07-12 14:40:48 +00:00
kewei.xu 2680eec0cd soc/mediatek/mt8188: Add I2C driver support
Add I2C controller drivers.

TEST=build pass
BUG=b:233720142

Signed-off-by: kewei.xu <kewei.xu@mediatek.corp-partner.google.com>
Change-Id: I7d19df3571e5588c7b20d9c7f26fa177b2221851
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-07-12 14:40:14 +00:00
Tony Huang 132b6d20e8 mb/google/dedede/var/shotzo: Update GPIO GPP_S2/S3 pin definition
Based on latest schematic:

Set GPP_S2 DMIC1_CLK/ GPP_S3 DMIC1_DATA to NC.

BUG=b:235303242
BRANCH=dedede
TEST=build

Change-Id: I4044cb7ba963153e1e478294dbf960fb79b97b5c
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65665
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2022-07-12 14:39:43 +00:00
Tony Huang 6cfe2624a2 mb/google/brya/var/agah: Disable thunderbolt interface
Agah doesn't support TBT interface so disable it in devicetree, for
fitimage configuration is at chrome-internal:4846869.

BUG=b:224423318
TEST=Build and check DUT boots.

Change-Id: I1eb43e86de5debf24ebde6eace14fe04bad5e5b1
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65699
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-12 00:48:52 +00:00
Frank Wu e3ed9cacaa mb/google/brya/var/banshee: Update VR domain settings
Update the VR domain settings based on the request of internal team.

- IA ac_loadline from 2.3mOhms to 2.4mOhms.
- IA dc_loadline from 2.3mOhms to 2.28mOhms.
- GT ac_loadline from 3.2mOhms to 3.13mOhms.
- GT dc_loadline from 3.2mOhms to 2.94mOhms.

BUG=b:237044562
BRANCH=firmware-brya-14505.B
TEST=FW_NAME=banshee emerge-brya coreboot chromeos-bootimage

Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I665665ab8e3bcd6d4643f8b954b86fad3ef78ccd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65522
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-07-11 14:07:14 +00:00
Paul Menzel 5c41bd67bc soc/samsung/exynos5420: Add space between comment markers and comment
Change-Id: Ica9014ee077ea416fdb4c7316c9619cf81fca510
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65730
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-07-11 13:41:31 +00:00
John Zhao b57d172fbb soc/intel/meteorlake: Align TCSS functions through SBI
This change aligns the Meteor Lake TCSS functions of pad configuration
and Thunderbolt authentication through the sideband access.

BUG=b:213574324
TEST=Build platforms coreboot images successfully.

Change-Id: I393f6e1c7d322878cbb684cd95bfa2477195b23a
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-07-11 13:41:14 +00:00
Patrick Rudolph 3c4750166f soc/intel/common/block/pmc/pmclib: Use same loglevel as print_num_status_bits
Use same log level as print_num_status_bits to make sure the
status bits are properly prefix and the newline is added.

Change-Id: Ib33798eec7cba601d0d49646c5fc429de5268417
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65715
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-07-11 13:40:58 +00:00
Michał Żygowski 0feffd109f mb/msi/ms7d25: Properly handle CnvDdrRfim parameter
CNVi DDR RFIM feature should be reported via _DSM function. Add the
generic WiFi device which will generate the proper ACPI code and
pass the CnviDdrRfim parameter to FSP by SoC driver.

TEST=Connect to WiFi network on Ubuntu.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ice2abe972f38dd819f7f0103f7b9a697096f1cd9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63835
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-11 09:02:30 +00:00
Michał Żygowski 1c3b443505 mainboard/msi/ms7d25: Add USB macros and port designation comments
Add the comments about port designation after mapping the root hub
ports to board connectors. Add macros reflecting the length of the
USB signal traces.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ib2e842ef240ab25e2a9f7fa2e0766206fde7943d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2022-07-11 09:01:21 +00:00
Michał Żygowski 6db287a5d9 mainboard/msi/ms7d25: Add default vboot configuration
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I9590a33e828906de083cb23c8b647ed2da0750ee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64222
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-11 09:00:32 +00:00
Michał Żygowski ffec028b54 mainboard/msi/ms7d25: Add FIVR configuration
Reflect the vendor's firmware FIVR settings.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I97b3b4f9470267961c138fea70703606373f6d52
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64051
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-11 08:59:51 +00:00
Michał Żygowski ee52f23936 mainboard/msi/ms7d25: Fill board-specific SMBIOS data
Add board connectors and headers descriptions to SMBIOS. Specify
type 1 and type 2 fields as in vendor firmware.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ie64be21ff302274769b77550c29e58d4ea1376d1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64050
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-11 08:59:22 +00:00
Michał Żygowski ba9b2b7465 mainboard/msi/ms7d25: Add NCT6687D configuration
TEST=Boot Ubuntu 22.04, load nct6687 kernel module and use lm-sensors
to display information about sensors on the SIO EC.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I55445a94f0de3510324b12558c4343e819412ac0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63928
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-11 08:58:41 +00:00
Michał Żygowski f0f8a5fda8 mainboard/msi/ms7d25: Enable PTT
Original firmware ships with PTT enabled by default on poweron.
PTT takes priority over SPI/LPC TPM so enable the CRB interface
until coreboot implements a way to select the interface and adapt
the API to handle any TPM detection.

TEST=Boot the board and see PTT is detected by Windows and Linux

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I74dc2c4245388a9f134b27e313ef26124b952594
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63834
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-11 08:55:36 +00:00
Michał Żygowski ed8216d42d mb/msi/ms7d25: Configure HD Audio
Apply correct configuration of HD Audio.

TEST=Launch ubuntu 20.04 and launch a YouTube video, check if
microphone detects an input in the system sound settings.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I6acc22aa58f6cc99df1d48d651122e74fe08ec02
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63723
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-11 08:54:56 +00:00
Michał Żygowski c354f31b30 mb/msi/ms7d25: Configure PCIe Root Ports
Add the full PCIe root port configuration. Proper initialization of
the root ports depends on the correct GPIO programming including
virtual wires. Do not program the CLKREQ signals in coreboot to let FSP
detect and configure CLKREQ pads. Otherwise the CLKREQ pads are
reprogrammed by FSP despite having GpioOverride=1. The pads that
should not be touched by coreboot are left commented in the board GPIO
file. CLKREQ reprogramming caused undefined behavior when ASPM and
Clock PM was being enabled by coreboot on PCIe endpoints of CPU PCIe
x4 slot (coreboot printed a lot of exceptions and simply halted).

TEST=Boot the MSI PRO Z690-A DDR4 WiFi with all PCIe/M.2 slots
populated and check if they are detected and functional in Linux.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I50199d2caf54509a72c5100acb770bf766327e7f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63656
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-11 08:53:47 +00:00
Felix Singer c2d1588623 mb/lenovo/haswell: Convert to variant setup
In preparation to CB:63514, make use of the variant concept and convert
the existing T440p mainboard into a variant.

Change-Id: I3c7e06607135ce0a62c158e296b51e5311234505
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63513
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-07-10 23:38:16 +00:00
Martin Roth 851435e379 Documentation/Infra: Update Jenkins doc with 2 new builders
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Id7683b8d5b33632aa1234fea82aa58dadc4c115d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64807
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-07-10 22:21:48 +00:00
Dtrain Hsu b1d26b4839 mb/google/brya/var/kinox: Override tdp pl1 value
Override tdp pl1 value to 30W in CPU MSR.

BUG=b:238268367
TEST=Boot to Chrome OS and check cpu log show "CPU PL1 = 30 Watts".

Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: Ibbd5ecc4b87ede5a62799020c741e5bff2952144
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65695
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-07-09 18:02:25 +00:00
Jeremy Soller 9c147c81dd ec/system76/ec: Hide ACPI device S76D
Hide the device so that Windows does not warn about a missing driver.

Tested on system76/lemp10:

- EC functionality remains functional on Linux 5.18.6 and Windows 10.
- Windows 10 does not report the device in Device Manager.

Change-Id: Iffcb873b85e077535d4de5806d01ba309f46c017
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64700
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-09 17:59:04 +00:00
Arthur Heymans 211d322878 */fsp/exit_car: Push stack address into %esp
Fixes: 5315e96abf ("arch/x86/postcar: Use a separate stack for C execution")
Resolves:
https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/
thread/TGIWAKZKELJRAEMKJNYRJ55MX2CXYNCV/
Link: https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/
thread/2JC3GNJSGXUD6DRVUY7O2O3W6OM3E2MY/

5315e96abf broke platforms using FSP-M to tear down CAR. It was pushing
the value at '_estack' into %esp rather than the address '_estack'.

Change-Id: Ie1fc70bd60fe3a2519ffb71625a35630fa732ff6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65716
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-07-09 17:05:19 +00:00
Jack Rosenthal 0636da3108 mb/google/brya/var/ghost4adl: Update GPIO table
Based on comments on CL:65534, update the non-early GPIO table.

These are cases where Arbitrage wasn't able to find a useful
heuristic, or the memory straps, where Arbitrage sees them as NC in
the schematic.

BUG=b:234626939
BRANCH=firmware-brya-14505.B
TEST=emerge-ghost coreboot

Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I6e00892243cd6af99dc1921ee3fc712f6cbb58c7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65710
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-08 21:40:17 +00:00
Jack Rosenthal 341ece9680 mb/google/brya/var/ghost4adl: Add early GPIO table
Customize brya baseboard early GPIO table to add mem straps for
ghost4adl, change I2C bus for TPM to pins H6/H7, and remove pins which
are not used on ghost4adl (E16, H13).

BUG=b:234626939
BRANCH=firmware-brya-14505.B
TEST=emerge-ghost coreboot

Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I126a66fc5d24fbefec99abf87862c55b50c5e398
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65534
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-08 21:39:40 +00:00
Elyes Haouas 72b4196d81 soc/intel/apollolake/meminit.c: Remove unuseful comment
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Ia81b4397c92f100abad9b1e974bbebfe49008439
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65700
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-07-08 15:41:54 +00:00
Elyes Haouas 07498031be mb/google/guybrush: Remove duplicated include
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I19cd9360a2571e8b88b1ed1005ce8564bdacb297
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65698
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-07-08 15:41:40 +00:00
Elyes Haouas 23bce8b09f soc/amd/common/block/lpc/lpc.c: Remove duplicated include
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Idd214893f304ce767633ffbf905f47a5092c2ee4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65697
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-07-08 15:41:24 +00:00
Michał Żygowski d3b8321563 superio/nuvoton/nct6687d: Add ramstage driver and ACPI
TEST=Boot MSI PRO Z690-A WIFI DDR4 with SP1, KBC and EC exposed
to OS via ACPI. Configure SP1, ACPI, KBC and EC devices via
devicetree.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ia489a39956c1448c7f11845ecc9e1df83ccb25ff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63927
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-08 15:40:31 +00:00
Michał Żygowski 6cf9b8f8ac mb/msi/ms7d25: Enable displays
Add VBT from vendor firmware v5.24 and configure display outputs in
devicetree.

TEST=Boot TianoCore UEFIPayload and notice the UEFI Shell on the
connected display via HDMI or DisplayPort on rear panel.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ide560ade5e29844c2f4310639fe5b76ba91865be
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63507
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2022-07-08 15:32:09 +00:00
Michał Żygowski 02db6b4049 mb/msi/ms7d25: Add correct memory init configuration
Tested with 4x KINGSTON KF3600C17D4/8GX DIMMs.

TEST=Include the microcode from vendor firmware and FSP blob from
Intel R&DC. Boot the platform and see ramstage is executing.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I98b9c77d791d18640cb05c133cb0bf14ad22dcdb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63503
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2022-07-08 15:31:44 +00:00
Reka Norman bb1a0e82d7 soc/intel/apollolake: Fix incorrect GPE number
BUG=None
TEST=None

Signed-off-by: Reka Norman <rekanorman@chromium.org>
Change-Id: I2eb6e94e5d87bb19b11e27461e2b5bdaee9d59bd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65691
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-08 15:30:47 +00:00
John Su 71139b2048 mb/google/brya/variants/felwinter: Add fw_config to control TBT PCIe RP0
Use USB4 fw_config to enable TBT PCIe RP0.

BUG=b:237619214, b:237623610
TEST=emerge-brya coreboot chromeos-bootimage

Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: Ie3e51a0f30e0c9d20127c017436813d4ede95639
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65696
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-07-08 15:30:13 +00:00
Reka Norman 8bbc5ba0ae soc/intel/common/pch: Fix incorrect GPE number
BUG=None
TEST=None

Change-Id: I7a4081f0f57e0faa968ad142debdc40a9e26dc9b
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65690
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-08 15:28:59 +00:00
Reka Norman b146c7a7c0 mb/google/nissa: Don't put WLAN into D3cold
On nissa, WLAN should be a wake source, so don't put it into D3cold
during suspend.

BUG=b:233325709
TEST=Wake-on-WLAN works on nereid

Change-Id: Iddd5fa8db05b85d2c799f679d664876109187d0c
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65688
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-07-08 15:28:41 +00:00
Michał Żygowski 6297df85d6 soc/intel/alderlake: Hook-up public Alder Lake microcode
CPUIDs and Engineering Samples decoding based on DOC #618427.

Keep MICROCODE_BLOB_UNDISCLOSED for PCH-N SKUs as microcode
blobs are still missing.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ibb1337e5cbf5b82fdaceb7eb4661d708a32ff0ad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65564
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-07-08 15:28:20 +00:00
V Sowmya 44c3759c22 mb/google/nissa: Enable Cnvi BT Audio Offload feature
This patch enables Cnvi BT Audio Offload feature and also
configures the virtual GPIO for CNVi Bluetooth I2S pads.

BUG=b:233834597
TEST=Verified BT offload feature on Nivviks P1.

Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: Iffbd08351d083d2b550f309994af931bceb257d9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-07-08 07:22:49 +00:00
V Sowmya aed31a49a5 mb/google/nissa: Confiure the unused virtual Cnvi BT GPIOs to NC
Configure the unused virtual CNVi BT GPIOs to NC since we
are using BT over USB mode for Nissa.

BUG=b:233834597
TEST=Verified BT offload feature on Nivviks P1.

Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: Id84823b9ad921ebd7ff773d6cce581563613745f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65669
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-07-08 07:22:33 +00:00
V Sowmya 0f7580e5cc mb/google/nissa: Disable the Package C-state demotion
Disabling the Package C-state demotion feature for nissa baseboard
as a work around to the S0ix issue and also this doesn't have any
impact on the power and performance measured and verified by the
PNP team.

This feature will be enabled after its functionality is verified with no
issues and also based on its impact on PNP.

BUG=b:235005582
TEST=Boot and verify that S0ix issue is resolved.

Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I4d586b962c27b86ee75651dcd655bc0868504646
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65664
Reviewed-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-07-08 07:22:25 +00:00
V Sowmya 4be8d9e80d soc/intel/adl: Add support to configure package c-state demotion
This patch adds the support to enable/disable package c-state demotion
feature from the devicetree based on mainboard requirement.

BUG=b:235005582
TEST=Build and boot to verify that the right value has been passed to
the FSP.

Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I9e254988bc3d20b9f9e42a605cc0ebd419ab49ad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65663
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-07-08 07:22:03 +00:00
Arthur Heymans 1793eb4c8a lib/fit.c: Don't align memory regions to 1MB
Aligning the "memory" ranges in devicetree is supposedly only needed on
very old arm32 kernels. So let's get rid of it.

Incidentally this fixes smaller than 1MB memory regions where the size
would end up being 0.

Change-Id: Ibbf5e331c79ed4ae3ed8dd37bf7a974d2412ce12
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65607
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-07-08 00:00:24 +00:00
Wonkyu Kim 25c2075388 soc/intel/common/graphics: Add another Meteor Lake device ID
Add 0x7d55 as another ID for Meteor Lake graphics controllers.

TEST=Boot with MTL silicon to check coreboot log for DID2
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Iea01f6d4f2469fc0eeac73a3f1c4b9af1f39463c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
2022-07-07 23:59:37 +00:00
Eric Lai b858f2e5c9 mb/google/brya/var/ghost4adl: Update the PCIE and USB setting
Based on latest schematic to update the PCIE and USB setting.

BUG=b:237659398
BRANCH=firmware-brya-14505.B
TEST=emerge-ghost coreboot

Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I97989b7a8d9104379ffb0b454d7248d49855f680
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65584
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
2022-07-07 23:59:09 +00:00