Commit Graph

48382 Commits

Author SHA1 Message Date
Elyes Haouas ab304bc091 sb/amd/common: Fix some white spaces issues
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I04951bf142fc4061960f42ad7ae702a70215e658
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65906
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-07-17 22:03:02 +00:00
Elyes Haouas 4c15211a78 sb/amd/pi: Fix some white spaces issues
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I90278683bc22d87364453f316c05afe4cd96b383
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-07-17 22:02:37 +00:00
Elyes Haouas 7d89264cdf sb/amd/agesa: Fix some white spaces issues
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I1497c7589570b8ff3873149a0fb212bad96ad432
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-07-17 22:01:20 +00:00
Elyes Haouas 644a67c116 cpu/amd/pi/00730F01/update_microcode.c: Fix some white spaces issues
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I420b9506381758c63b88435a915672507e8bc465
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-07-17 21:59:39 +00:00
Elyes Haouas 68fc51faf2 soc/amd/common: Fix some white spaces issues
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I54438978db13ba00188e53239f7034d1b258e912
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-07-17 21:59:05 +00:00
Elyes Haouas f9b535eecf nb/amd: Fix some white spaces issues
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: If8b2db7ff816b9953e9bb767f0f406417e297386
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-07-17 21:57:31 +00:00
Elyes Haouas 76c63231d9 drivers/amd/agesa: Fix some white spaces issues
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I0a11d303d2e2c83cb72773656f5caedec666dc66
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65898
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-07-17 21:55:47 +00:00
Elyes Haouas 558d731a4c sb/amd/*/*/smbus_spd.c: Fix some white spaces issues
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I47ee16f2d4be34c42b2e7f9fa4c3a72a7a95967f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65897
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-07-17 21:54:55 +00:00
Elyes Haouas ba9deba362 sb/amd/*/*/sata.c: Fix some white spaces issues
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I4c5dffb32e1ed858e93f95ed17eac894a9100501
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65896
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-07-17 21:53:49 +00:00
Elyes Haouas 833582640c soc/amd/*/include/soc/iomap.h: Fix some white spaces issues
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I7b6e41fa3b7cd8c8f7327c690212ec4990e8baf5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65895
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-07-17 21:53:24 +00:00
Elyes Haouas 8833d65fc8 sb/amd/*/*/smbus.h: Fix some white spaces issues
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I18120ba93140e2dced7c8d9aafa34a834d1df842
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65894
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-07-17 21:52:55 +00:00
Elyes Haouas 693f7c10bf nb/amd/*/*/pci_devs.h: Fix some white spaces issues
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I9261c89b8a15f1ea2f5883481a1cdb7fc8664bb0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65893
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-07-17 21:52:28 +00:00
Elyes Haouas f63edd98a6 nb/amd/agesa/*/dimmSpd.c: Fix some white spaces issues
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Icfd36e0ee524e0e2dc1dd6b0ee39a5c1ae31f4ea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65892
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-07-17 21:45:20 +00:00
Elyes Haouas 3adfde9c6a nb/amd/agesa/*/northbridge.c: Fix some white spaces issues
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: If7cac72e0bbdefdb4b6e2697df69a061a23e8684
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65891
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-07-17 21:43:14 +00:00
Elyes Haouas f58c787db5 nb/amd/agesa/*/acpi_tables.c: Fix some white spaces issues
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Ia92acfa006ae44fc2969a92b4b21a2c27e0f01be
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65890
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-07-17 21:42:45 +00:00
Elyes Haouas a69311d057 mb/amd/*/irq_tables.c: Fix some white spaces issues
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Ifc915e2825724fdaac67d259e1af2079893492a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65889
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-07-17 21:42:20 +00:00
Elyes Haouas 1163d14d3e mb/amd/persimmon/mainboard.c: Fix some white spaces issues
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I490a7f0c9cb32ca1ea246c14b72852814553214f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65905
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-07-17 21:41:53 +00:00
Paul Menzel b6daf297b3 commonlib: compiler.h: Improve wording in comment
It probably was supposed to be *making these names conistent …*, but
short that a little, and add a missing article.

Change-Id: If88ff6d7b0a61aa83d5822b5e1c0b5b4c9d3bb3c
Fixes: ac136250b2 ("commonlib: Substitude macro "__unused" in compiler.h")
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65884
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-17 21:39:29 +00:00
Elyes Haouas 24f4e97dd4 nb/intel/sandybridge/raminit_mrc.c: Use semicolon instead of comma
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I15d7e2f30b054d14009761006a2f89f45e001118
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65838
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-07-17 21:34:52 +00:00
Elyes HAOUAS 6c42fa20f6 cpu: Get rid of unnecessary blank line {before,after} barce
Change-Id: I9b710d279da6db9125519f58ecba109a4d9fa8e3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61554
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-07-17 18:57:54 +00:00
Elyes HAOUAS f551784830 src/drivers/intel/i210: Remove unuseful 'return' in void function
Change-Id: Id33ef66e7388df2173ee8888265ed4379f05a93e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-07-17 18:56:22 +00:00
Elyes HAOUAS c2f1202151 security/intel/txt/common.c: Remove unuseful "else" after "return"
"else" is unuseful after a "break" or "return".

Change-Id: I7273b9af46a2310c9981ffd20afe2c8c7e061479
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60910
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-07-17 18:54:31 +00:00
Elyes HAOUAS 55be012ffd drivers: Get rid of unnecessary blank lines {before,after} brace
Change-Id: Ic1b38e93d919c1286a8d130700a4a2bfd6b55258
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61557
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-07-17 18:45:23 +00:00
Elyes HAOUAS 8765c09a63 include/device/device.h: Remove unneeded blank line after '{'
Change-Id: I3e439a293c6b4a806cae7c6a56d28e61f7e57044
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61555
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-07-17 18:42:05 +00:00
Eran Mitrani f39e29624a include/acpi: Add macros & definitions for resources types and flags
These enums & macros will be used to report resources with acpigen_*
functions (Currently those resources are reported in northbridge.asl,
but follow-up CLs will remove this file and add the need acpigen code).

BUG=b:148759816
BRANCH=firmware-brya-14505.B
TEST='emerge-brya coreboot chromeos-bootimage' builds correctly.
Tested on an Anahera device which successfully boots to ChromeOS
with kernel version 5.10.109-15688-g857e654d1705.

Change-Id: I5b95c9b8370db63537eb48b640ad8f0e750efd69
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65768
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-16 23:21:03 +00:00
Tim Crawford fc9f88292d mb/system76: Correct HID names for touchpad devices
Use correct HID names instead of the CID names for the touchpad devices.
Drop the now unneeded UID for the gaze15 TP devices.

Tested on a gaze15 with a Synaptics device. Windows does not crash on
boot and the touchpad is still detected as an I2C HID device.

Change-Id: I5b6ab1a23ce667754d0c5757062385a721c5113f
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65723
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-07-16 23:18:56 +00:00
David Wu a08d5a8086 mb/google/brya/var/osiris: Add wifi sar table
1. Add wifi sar table for osiris
2. Set EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG

BUG=b:234951991
TEST=build FW and checked SAR table can load by WiFi driver.

Cq-Depend: chrome-internal:4871098
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I301dce3229a24dd72b12b84d9eb7606abe10cbba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65869
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
2022-07-16 23:16:21 +00:00
Tim Crawford 205e7f676d mb/system76/oryp5: Configure dGPU GPIOs in bootblock
Configure the dGPU power and reset pins in bootblock instead of
ramstage. This fixes a conflict with our downstream driver, which
configures these pins to enable dGPU power in romstage. Behavior remains
unchanged without the driver as the dGPU is left powered off.

Change-Id: Ica5ad5adc20fc2629d913b76a5a781fbd59a569d
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65801
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-07-16 22:55:54 +00:00
Varshit B Pandya 4060df41b2 drivers/intel/dptf: Correct UID for TBAT device
As per Intel Dynamic Tuning Spec revision 1.3.13, section 14.1.2 TBAT
_UID should match the _UID implemented for battery device ACPI object
for OS

_UID for TBAT is currently set to "TBAT" but should be 1.
Battery device is define at src/ec/google/chromeec/acpi/battery.asl

Setting _UID to 1 because right now ChromeOS is the only user
of DPTF driver

TEST: Build and boot brya0

Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: I1e4474e59cf01f937fbd51e5b674a609f0c47625
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65605
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-07-16 22:54:38 +00:00
Tim Crawford 86f410479c mb/system76/oryp5: Reset HDA before configuring
The oryp5 has several issues with audio output after a reboot:

- The device is not in GNOME sound settings
- The device is in GNOME sound settings, but there is no audio output
- The speaker output is significantly louder than normal

Reset the audio codec to resolve these issues.

Tested on Pop!_OS 22.04 with Linux 5.17.15.

Change-Id: I42f642820bba82142ff370930f0a25e9d1025588
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65733
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-07-16 22:53:01 +00:00
Fred Reitberger 475e2824a8 soc/amd/[cezanne,picasso,sabrina]/Kconfig: Add PSP_APOB_DRAM_SIZE config option
The APOB in sabrina is larger than in cezanne/picasso and no longer
fits in the previously allocated 64K space for it. Other symbols are
placed immediately after the APOB region and end up corrupting the APOB
data on sabrina.

Add a Kconfig option to specify the APOB size in DRAM to reserve enough
memory and increase the size for sabrina to 128K

TEST=Timeless builds are identical for mandolin/majolica for PCO/CZN.
Build chausie and verify symbols do not overlap _apob region
BUG=b:224056176

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Ia5dbacae67ff02fc8a6ec84b9007110ca254daa3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-07-16 22:52:21 +00:00
Tim Crawford 8de0e369e3 ec/system76/ec: Provide charging thresholds by default
Battery charging thresholds are a firmware implementation and not
dependent on any hardware. It is expected that all boards using System76
EC firmware will select this option, so enable it by default.

Leave it disabled on clevo/cml-u, which didn't have it selected.

Change-Id: Id99d36eaf055a76b9e1eb732174017651de299a5
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65714
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-07-16 22:48:06 +00:00
Eran Mitrani 311223ac38 mb/google/brya/var/brya: fix comment for I2C connections
For brya, I2C1 is cr50, and I2C3 is Touchscreen

BUG=None
BRANCH=firmware-brya-14505.B
TEST=None

Signed-off-by: Eran Mitrani <mitrani@google.com>
Change-Id: Id564d5ede43e745c607ddfd851ff03557d76ddec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65793
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-07-16 22:46:09 +00:00
Varshit B Pandya d9bc689276 driver/wifi: Remove unused function wifi_emit_dsm
As part of this CL https://review.coreboot.org/c/coreboot/+/61020
this function was decoupled and support for new DSM was added.
This function is no longer used so remove it.

Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: Iad9dca8e50bad87178dfcc1951276703721d5f60
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65850
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-16 22:44:09 +00:00
Ritul Guru c58f674411 soc/amd/picasso: Add MP2 I2C0 and I2C1 controller ACPI devices
This change is to allow AMD MP2 I2C OS driver to access
I2C0/1 devices when MP2 firmware is loaded.

Change-Id: Iaf25eb4dcf949e4b512ec0e86dbe5ccbc91c3d24
Signed-off-by: Ritul Guru <ritul.bits@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65673
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-16 22:43:07 +00:00
Christian Walter 106def9645 soc/intel/xeon_sp: Make gsi_bases platform independent
This commit makes gsi_bases platform independent. It introduces two new
Kconfigs which set if there are IIO APICs on other devices than the PCH
or not, and where they do start.

Change-Id: I40db4a8fd90572757687f35bbd8eebd7229fc75a
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65531
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-15 12:06:32 +00:00
Christian Walter b1a4c62130 soc/intel/cannonlake: Update VR config for Coffee Lake
This is based on the following Intel documents:
* 570805
* 570806
* 572062
* 571264

Change-Id: I199415902d26fa5341ef3212a9169836ea4df74a
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-07-15 12:06:04 +00:00
Stanley Wu cedaf72b8d mb/google/nissa/var/pujjo: Remove unsupport HDA device setting
Pujjo only support RTL1019 amp device, remove MX98360A device setting

BUG=b:238716919
TEST=Build and boot on pujjo

Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: I92ba66e8656ea36511f88cf867f51ba95168592e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65818
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-07-15 12:05:48 +00:00
Tim Wawrzynczak 17c77f5a86 mb/google/brya/var/agah: Disable ASPM for dGPU
Since ASPM is not verified as fully functional yet, and the board is
still in development, this patch disables ASPM for the dGPU.

BUG=b:236676400
TEST=boot to OS in agah, lspci -vvv shows ASPM is disabled

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I525eeb18c57d45fd55335b63a59262066afc9567
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-07-15 12:05:07 +00:00
Yu-Ping Wu fcfc572947 util/xcompile/xcompile: Define GCOV_${TARCH}
When payloads analyze the coverage using gcov (or lcov), the gcov
version must match the CC version. Otherwise gcov would fail to parse
the .gcno files.

Therefore, define GCOV_${TARCH} in xcompile, so that payloads don't need
to do tedious string manipulations to find the right gcov path.

Change-Id: If2fc329810c463a3d2c56deaf4e4a3fc3c0a3ed9
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
2022-07-15 05:59:38 +00:00
Mark Hsieh 69bf58d30e mb/google/nissa/var/joxer: Update Joxer config to latest schematic
init overridetree.cb based on the latest schematic.

BUG=b:237628218
TEST=USE="project_joxer emerge-nissa coreboot"

Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I22778cc2582abdc2e62d98c6b049a0fa4dd467e6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65662
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-07-14 23:13:15 +00:00
Sridahr Siricilla 096ce1444e soc/intel/alderlake: Support PCIe hardware compliance test mode
The validation process verifies that hardware components comply with
the standard hardware specifications. For instance, PCI express
implementation must comply with the hardware PCIe specification
requirements: Electrical, Configuration, Link Protocol and Transaction
Protocol. To perform these tests the hardware must be configured in a
particular state: some feature related to power management need to be
turned off, hot plug should be enabled...

This patch sets the appropriate FSP Updateable Product Data flags to
get the hardware in the proper configuration:
- Enable PCIe hotplug on all ports
- Set clock sources to run free
- Set the FSP compliance test mode flag

BUG=b:235863379
TEST=Compilation with and without the flag
     Verify code path with instrumentation

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Change-Id: Ic07b9276121dfbd273a8f63a1f775ddbd3566884
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65114
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-07-14 23:12:36 +00:00
Jeremy Compostella 1dc080fc1d soc/intel/common: Introduce SOC_INTEL_COMPLIANCE_TEST_MODE
This config can be used to make coreboot configure the hardware to
meet compliance tests requirements. SoCs which support compliance
testing features should set the
SOC_INTEL_SUPPORTS_COMPLIANCE_TEST_MODE flag.

BUG=b:235863379
TEST=Successful compilation

Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Change-Id: Iec760ae89e2b892ef45e6750e823ab5a8609d0fa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-07-14 23:12:14 +00:00
Johnny Li 188ed2b691 mb/google/volteer/eldrid:add new generic DDR4 SPDs for Eldrid
Update DDR4 SPDs to Eldrid to include the following:

DRAM Part Name    ID to assign
H5AG36EXNDX019    0 (0000)

BUG=b:236739240
BRANCH=Volteer
TEST="FW_NAME=eldrid emerge-volteer coreboot" and verify it builds successfully.

Signed-off-by: Johnny Li <johnny_li@wistron.corp-partner.google.com>
Change-Id: I2c372fa40899aa750d335825cf3880bc52a612a7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65819
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-14 23:11:39 +00:00
Johnny Li 837ee21b25 mb/google/volteer/eldrid: Add new DDR4 part H5AG36EXNDX019
Hynix H5AG36EXNDX019 is used by the volteer variant Eldrid. Add it to the DDR4 parts list and regenerate the SPDs using spd_gen.

BUG=b:236739240
BRANCH=Volteer
TEST="util/spd_tools/bin/spd_gen memory_parts.json ddr4" and verify it builds successfully.

Signed-off-by: Johnny Li <johnny_li@wistron.corp-partner.google.com>
Change-Id: I3383dfa4e87571d920144d204270cdf646a19abf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65817
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-07-14 23:11:19 +00:00
Arthur Heymans efd2720e47 arch/x86: Mark prepare_and_run_postcar noreturn
This moves the die() statement to a common place.

Change-Id: I24c9f00bfee169b4ca57b469c089188ec62ddada
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65812
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-07-14 23:10:30 +00:00
Arthur Heymans 84b2f9f5b8 lib/program_loaders.c: Mark run_ramstage with __noreturn
This allows the compiler to optimize out code called after run_ramstage.

Also remove some die() statements in soc code as run_ramstage already
has a die_with_postcode statement.

Change-Id: Id8b841712661d3257b0dc67b509f97bdc31fcf6f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65811
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-07-14 23:10:17 +00:00
Cliff Huang b95a821576 mb/intel/adlrvp: remove I2S2 GPIO settings
It turns out that there is no device connected to I2S2.
This patch clarifies the GPIO settings device association and remove
unnecessary configuration.

GPP_A8  -> default: GP-in ; set to NF1: SRCCLKREQ7#
GPP_A9  -> default: NF1: ESPI_CLK
GPP_A10 -> default: NF1: ESPI_RESET#

BRANCH=firmware-brya-14505.B

Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I7a575f495d841fe0bf6fd86a84caeee064f6904b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2022-07-14 23:09:53 +00:00
Tim Crawford 59e03ebf4c mb/system76: TGL-U: Disable AER for CPU PCIe RP
Disable PCIe Advanced Error Reporting on the CPU root port to prevent
some SSDs from timing out on S0ix suspend. AER results in the drive not
being able to switch from D3 back to D0.

    nvme 0000:01:00.0: can't change power state from D3cold to D0 (config space inaccessible)

Known to affect at least the following SSD models:

- ADATA XPG SX8200 Pro
- Samsung 970 EVO Plus (FW version: 2B7QCXE7)

Change-Id: I79da6b08ef1949f3bf1c6111aaa7e658bd29c0e2
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64080
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-14 23:09:32 +00:00
Bill XIE 44ef2123b0 sb/intel/ibexpeak: Perform const correctness
me_bios_path_values[] in me.c should not be mutable.

Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: I56412ff0883e1d37027b989c7ac1bd83e93661f2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65729
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-07-14 23:09:09 +00:00