Commit Graph

43383 Commits

Author SHA1 Message Date
Alex1 Kao 72cfaf05bf mb/google/dedede/var/pirika: Configure I2C times to 380-400 kHz for touchpad
Configure I2C high / low time in the device tree to ensure I2C
CLK runs accurately between 380 kHz and 400 kHz.

Audio codec:388.91 kHz
Touchpad:394.48 kHz

BUG=b:193864546
BRANCH=dedede
TEST=Build and check after tuning I2C clock is between 380 kHz and 400 kHz

Signed-off-by: Alex1 Kao <alex1_kao@pegatron.corp-partner.google.com>
Change-Id: Ia57c90ead44ceb0990878dc0566e595bae5a9099
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56383
Reviewed-by: Kirk Wang <kirk_wang@pegatron.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-29 09:10:26 +00:00
Lean Sheng Tan 2597dc10d6 mb/intel/ehlcrb: Select LPSS console by default
Select `INTEL_LPSS_UART_FOR_CONSOLE` to allow using PCH UART 2 as
coreboot console. Also, simplify `UART_FOR_CONSOLE` defaults.

Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I853777116fc541e5dc31f3ca8673f8bf66c7c9e1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56423
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-29 05:18:54 +00:00
Lean Sheng Tan 471dca7b10 soc/intel/elkhartlake: Update UART clock divider params
As EHL UART source clock is 120MHz, update the clock divider
parameters (M & N) to reflect the right value.

Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I30c21bc4d1ef901a318a12664b61be75c1acf23b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56422
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-07-29 05:18:48 +00:00
Patrick Georgi 719d85bf56 util/xcompile: Allow overriding default compiler path
When looking for C compilers, xcompile uses the "" prefix to "gcc" and
"clang" as a last-resort option. This fails in environments where such
default names are blocked to prevent "unclean" builds - such as Chrome
OS.

Allow overriding this prefix using the GENERIC_COMPILER_PREFIX variable
that is hopefully both descriptive enough to suggest what it is for and
unusual enough to not trigger by chance.

Change-Id: I16239f66730f1dbcb7482f223cea4ee5957af10c
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-07-28 23:01:12 +00:00
David Wu 340cb9ae2c mb/google/brya/var/kano: Generate SPD ID for supported parts
Add supported memory parts in mem_parts_used.txt, and generate
SPD id for these parts.

MT53E512M32D1NP-046 WT:B
MT53E1G32D2NP-046 WT:B
H54G46CYRBX267
H54G56CYRBX247
K4U6E3S4AB-MGCL
K4UBE3D4AB-MGCL

BUG=b:194766276 b:194686484 b:194765811
TEST=build

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Iba019c50224be8322865eee7baf81e3a574ff9a4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56630
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-07-28 22:54:27 +00:00
David Wu fc009cb31a util/spd_tools/lp4x: Add new memory parts and generate SPDs
This change adds the following memory parts to LP4x global list and
generates SPDs using gen_spd.go for ADL:
1. H54G46CYRBX267
2. H54G56CYRBX247
3. K4U6E3S4AB-MGCL
4. K4UBE3D4AB-MGCL

BUG=b:194686484 b:194765811
TEST=build.

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: If85088f843ab11cc531a3975b5cac3e36b573970
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-07-28 22:54:18 +00:00
Wayne3 Wang eef34ef2ee mb/google/volteer/variants/drobit: Add Charger Performance Control table TCHG for DPTF setting.
Add Charger Performance Control table TCHG for DPTF setting.

BUG=b:194256990
BRANCH=firmware-volteer-13672.B
TEST=build test firmware and verified by thermal team.

Change-Id: I9dba3f0e75d07d8ee9656bd1ee8d6de2d3b8c152
Signed-off-by: Wayne3 Wang <Wayne3_Wang@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56500
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ariel Chang <ariel_chang@pegatron.corp-partner.google.com>
Reviewed-by: Paul F Yang <paul.f.yang@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com>
2021-07-28 22:51:07 +00:00
Patrick Georgi a4422b84fd Update chromeec submodule to upstream main
Updating from commit id 1e800ac83:
2021-03-01 22:59:54 +0000 - (docs: point md files in master to main/HEAD)

to commit id 4c21b57eb:
2021-07-19 11:36:07 +0000 - (pd: Fix missing polarity_rm_dts in some conditions)

This brings in 3145 new commits.

Change-Id: Iff2e9f766e750070d71644c2f9895ad10e8b1c9a
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56431
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-28 20:53:49 +00:00
Patrick Georgi aca017a8bb Update arm-trusted-firmware submodule to upstream integration
Updating from commit id 96404aa27:
2021-05-13 18:27:27 +0200 - (Merge "build(hooks): update Commitizen to ^4.2.4" into integration)

to commit id 586aafa3a:
2021-07-19 05:36:18 +0200 - (Merge "errata: workaround for Neoverse V1 errata 1791573" into integration)

This brings in 207 new commits.

Change-Id: Iaf8af5ffaf377070ee1430ed7cfdc51001a1ba6b
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56416
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-28 20:53:44 +00:00
Malik_Hsu c5ac6d9ec5 mb/google/brya/variants/primus: Update NVMe clk
According to the schematic diagram of proto, modify the clock of nvme
from the baseboard default to src0.

BUG=b:194487277

Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com>
Change-Id: I41be517b434513bca2332ec37e54f56910302bb7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56584
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-28 17:09:55 +00:00
Karthikeyan Ramasubramanian ce227fe02d Revert "soc/intel/common/block/gpio: Add support to program VCCIO selection"
This reverts commit 4c569b52f6. This has
introduced a regression in mainboards using JSL SoC such that it
overrides the soft straps for all the GPIOs. This in turn has led to
some of the peripherals not working.

BUG=None
TEST=Build and boot to OS in Storo. Ensure that the regressed
peripherals are working back again.

Change-Id: Ibfeed1075fe28051b926ddd7ca771693dc19dae8
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56613
Reviewed-by: Evan Green <evgreen@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-28 16:13:06 +00:00
Karthikeyan Ramasubramanian 2e17d7b894 Revert "soc/intel/jasperlake: Enable support to program VCCIO selection"
This reverts commit 16f2c5082c.

Change-Id: Id0f960fdeca5895afc22809ff3f0236d6dbe82f4
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56614
Reviewed-by: Evan Green <evgreen@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-28 16:12:58 +00:00
Karthikeyan Ramasubramanian d678f65564 Revert "mb/google/dedede: Program VCCIO selection for EN_SPKR GPIO"
This reverts commit ce79ceec86. This has
introduced a regression in mainboards using JSL SoC such that it
overrides the soft straps for all the GPIOs. This in turn has led to
some of the peripherals not working.

Change-Id: Ifea5d4d0f474873f8bf4818ec1986e534f455216
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56615
Reviewed-by: Evan Green <evgreen@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-28 16:12:51 +00:00
Felix Singer b8c2fcca73 ec/roda/it8518/acpi: Remove unnecessary assignments
Simplify some operations to get rid of unnecessary assignments.

Change-Id: I02c93d42ce1de693d5d58fd9a29ccd5bff0f5978
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56609
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-07-28 13:50:59 +00:00
Felix Singer afa6c41a80 ec/roda/it8518/acpi: Use lower-case hex format
Built roda/rw11 with `BUILD_TIMELESS=1` and coreboot.rom remains the
same.

Change-Id: I9f08b048d41ab7a5d7d7dc735779ea019517491a
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56608
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-28 13:49:50 +00:00
Felix Singer ee00ad3513 ec/roda/it8518/acpi: Use mathematical operators
Use mathematical operators instead of their equivalent methods.

Change-Id: I5b1d5d9882eae5e8bcf2d97bcefaeea1a7ad8f4d
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56607
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-28 13:49:43 +00:00
Felix Singer 2b902ebf95 ec/roda/it8518/acpi: Use bit-wise and logical operators
Use bit-wise and logical operators instead of their equivalent methods.

Built roda/rw11 with `BUILD_TIMELESS=1` and coreboot.rom remains the
same.

Change-Id: I30807e14b2a9a8203a76d418f586423bcaec2a3a
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56606
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-07-28 13:49:33 +00:00
Felix Singer 7f4d53a21c ec/roda/it8518/acpi: Make use of the assignment operator
Replace `Store()` with the assignment operator.

Change-Id: I2931a3e1b9a55198ec4dacc9218b6c9028052631
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56605
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-28 13:48:41 +00:00
Felix Singer 5b53d3e233 ec/roda/it8518/acpi: Get rid of `Index()`
Use `FOOO[1337]` instead of `Index(FOOO, 1337)`.

Built roda/rw11 with `BUILD_TIMELESS=1` and coreboot.rom remains the
same.

Change-Id: I4f5d5cb8ce8c3ae37dc44ca87bd67596af9feee8
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56604
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-28 13:46:32 +00:00
Felix Singer 48d064bf9b ec/roda/it8518/acpi: Use decimal integers for accessing indexes
Change-Id: I7d4fb69a223e3b48a790e9144d2682619c18d513
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56603
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-28 13:46:22 +00:00
Felix Singer 98a413257c ec/roda/it8518/acpi: Make use of `Printf("...")`
Replace `Store("...", Debug)` with `Printf("...")`.

Built roda/rw11 with `BUILD_TIMELESS=1` and coreboot.rom remains the
same.

Change-Id: Ie1a1f7320ef2850e4f861b1426240e6940036844
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56602
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-28 13:46:12 +00:00
Nico Huber 8e0d1936a2 ec/roda/it8518/acpi: Don't hard-code GPE offset
The GPE offset of 16 is PCH specific.

Built roda/rw11 with `BUILD_TIMELESS=1` and coreboot.rom remains the
same.

Change-Id: I4ec38fc28d2436f84a090bb4ab38f20612cfd795
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56080
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-28 13:46:05 +00:00
David Wu df060bc362 mb/google/dedede/var/magolor: Add custom Wifi SAR for magister
Add wifi sar for magister.
Due to fw-config cannot distinguish between magolor and magister.
Using sku_id to decide to load magister custom wifi sar.

BUG=b:192290227
TEST=build and test on magolor/magister

Cq-Depend: chrome-internal:3986580
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I4510cc2ad42a11ec802ecd439b353f8e87d63868
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-28 11:40:50 +00:00
Simon Yang df520855ca soc/intel/jsl: Add disable_external_bypass_vr config
This dev tree config controls the Vnn/Vcc1P05 bypass mode for Jasperlake.

BUG=b:191691430
BRANCH=dedede
TEST=Build fw and confirm FSP setting are set properly by log

Signed-off-by: Simon Yang <simon1.yang@intel.com>
Change-Id: I10bc203d3fed32ab65f325978426b7d0fca6f392
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55744
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-28 11:40:45 +00:00
Jamie Chen 1ebcb2ab62 soc/intel/jasperlake: add pcie modphy settings
This patch adds device tree settings to control pcie modphy tuning
FSP UPDs. With this patch, the pcie modphy can be tuned per board.

BUG=b:192716633
BRANCH=NONE
TEST=build dedede variant coreboot with fw_debug enable and check if
     these settings have been changed successfully on fsp debug log.

Change-Id: I80a91d45f9dd8ef218846e1284fdad309313e831
Signed-off-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56336
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-28 11:40:27 +00:00
Tao Xia 0f93a7b781 mb/google/dedede/var/sasukette: Set the xHCI LFPS period sampling off time to 0ms
LTE module L850-GL may encounter U3 wakeup race condition with the host.
Setting xHCI LFPS periodic sampling off time to 0ms so that the host would not
miss the device-initiated U3 wakeup thus avoid the race condition.

BUG=b:191426542
BRANCH=dedede
TEST=flash the image to the device. Run following command to check the bits[7:4] is 0x0:
iotools mmio_read32 "XHCI MMIO BAR + 0x80A4"

Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Change-Id: I3be7adad49f87956a6764ad91fec6e76681b393f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56518
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Chiasheng Lee <chiasheng.lee@intel.com>
2021-07-28 11:40:11 +00:00
FrankChu 4db34f6823 mb/google/volteer/var/collis: Update DPTF parameters for DVT build
Update Passive Policy and TCHG parameters.

BUG=b:188936764
TEST=emerge-volteer coreboot chromeos-bootimage

Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: Id75bfa74ba353f2342c95bcf8d73cd83c957deb5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56512
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-28 11:39:55 +00:00
Arthur Heymans ac522f1cd7 src/vendorcode/eltan: Don't reference CONFIG_CBFS_SIZE
This symbol is only used in generating a default fmap.

Change-Id: I8d92eba9978cdad5795b0f5755e1d75db7b3cb2d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56592
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2021-07-28 08:19:30 +00:00
Ryan Chuang de3859d538 vc/mediatek/mt8195: Improve DRAM stability by impedance tracking
Enable the impedance tracking for channel 2 and channel 3.
The impedance tracking can compensate the settings of impedance
when the temperature changes.

Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com>
Change-Id: I047ab70bb59736a8ba8ae75ab15659900c784342
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56620
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-28 02:51:36 +00:00
Felix Held 403fa86924 include/acpi/acpi.h: add comment about raw data in generic error status
Since the specification isn't very clear on this, add a comment about
the optional raw data part of a acpi_generic_error_status block.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6df7d2f216fe0515e89d08c8ed01f06d19461429
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56611
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-27 22:45:52 +00:00
Felix Held 98fb72fa3f cpu/x86/mp_init: don't wait between INIT and SIPI for X86_AMD_INIT_SIPI
Since current AMD SoCs don't need some wait time between INIT and SIPI,
we can skip the 10ms wait there, which improves the boot time a bit.

before: CPU_CLUSTER: 0 init finished in 632 msecs
after:  CPU_CLUSTER: 0 init finished in 619 msecs

mpinit still works on Mandolin and all CPU cores show up and are usable.
This also doesn't change the binary in a timeless build for boards/SoCs
that don't select X86_AMD_INIT_SIPI which I verified for lenovo/x230.

BUG=b:193885336

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1e044776f45021742a88a5e369a74383c1baaab6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-07-27 14:00:32 +00:00
Felix Held 3136424e48 soc/amd/common/block/acpimmio: add Kconfig option for biosram accessors
The biosram accessor support in soc/amd/common/block/acpimmio/biosram.c
is only used on Stoneyridge and the old amd/southbridge code and not on
Picasso or Cezanne. It also only builds as a 32 bit binary and breaks
when trying to build as a 64 bit binary, since the size of an uintptr_t
is different on those two. There is no support for using the 32 bit
binaryPI with a 64 bit coreboot while there is code to use a 32 bit FSP
with 64 bit coreboot, so not building this for FSP-based SoC support
moves us one step closer to be able to build coreboot as 64 bit binary
for Picasso and Cezanne.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2d87ec2fa1b217eaf55d865e4390308812502e56
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-07-26 19:34:20 +00:00
Angel Pons ee3d09b48e mb/*: Specify type of `VARIANT_DIR` once
Specify the type of the `VARIANT_DIR` Kconfig symbol once instead of
doing so on each and every mainboard.

Change-Id: Iea2f992a59e41e00fec3cdc9d6a13b5f3ab0a437
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56558
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26 14:07:38 +00:00
Angel Pons 75be324524 mb/*: Specify type of `FMDFILE` once
Specify the type of the `FMDFILE` Kconfig symbol once instead of doing
so on each and every mainboard.

Change-Id: I810bd3fe8d42102586db6c2c58b7037a60189257
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56557
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26 14:06:57 +00:00
Angel Pons 8905ecbcfa mb/*: Specify type of `OVERRIDE_DEVICETREE` once
Specify the type of the `OVERRIDE_DEVICETREE` Kconfig symbol once
instead of doing so on each and every mainboard.

Change-Id: I4cbf4e318a30f0cf75aa8690e7454b9caa115c9d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56556
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26 14:06:36 +00:00
Angel Pons 924546be17 mb/*: Specify type of `DEVICETREE` once
Specify the type of the `DEVICETREE` Kconfig symbol once instead of
doing so on each and every mainboard.

Change-Id: If68f11a5ceaa67a3e8218f89e1138c247ebb9a25
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56555
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26 14:06:15 +00:00
Angel Pons 2c03ffc8df mb/*: Specify type of `MAINBOARD_PART_NUMBER` once
Specify the type of the `MAINBOARD_PART_NUMBER` Kconfig symbol once
instead of doing so on each and every mainboard.

Change-Id: I3692f9e82fe90af4d0da1d037018a20aa1b45793
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56554
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26 14:05:29 +00:00
Angel Pons 9cddae151a mb/*: Specify type of `MAINBOARD_DIR` once
Specify the type of the `MAINBOARD_DIR` Kconfig symbol once instead of
doing so on each and every mainboard.

Change-Id: If1cc538b0c4938dac193699897b690e402b3c1e8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56553
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26 14:04:45 +00:00
Angel Pons ac90f593f8 src/*: Specify type of `CBFS_SIZE` once
There's no need to specify the type of the `CBFS_SIZE` Kconfig symbol
more than once. This is done in `src/Kconfig`, along with its prompt.

Change-Id: I9e08e23e24e372e60c32ae8cd7387ddd4b618ddc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56552
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26 14:02:57 +00:00
Angel Pons ac44f87465 mb/intel/galileo: Clean up `FMDFILE` Kconfig handling
Remove redundant type, prompt and help text, and replace `depends on`
clause with conditional default to allow specifying a FMAP when vboot
is not selected.

Change-Id: I37ddab3a27e304e810ea55f13821d755bb70cb4b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56551
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26 14:02:43 +00:00
Angel Pons 5b44e7dce3 mb/facebook/monolith: Don't override `CBFS_SIZE` prompt
Change-Id: I6fac40918f1ca3227ff68e79fcae039a26356d0d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56550
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26 14:01:56 +00:00
Felix Singer 4c426262d7 mb/google/brya: Deduplicate chipset lockdown config
Due to an issue in sconfig, move `chipset_lockdown` out of
`common_soc_config` and configure it separately in the baseboard's
devicetree since it might get overwritten if a variant configures
`common_soc_config`.

Also, deduplicate the configuration of `chipset_lockdown`.

Change-Id: Id969346df06aa82ab2ad2b1aa4884a9bcd876d75
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56408
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26 12:22:47 +00:00
Felix Singer 32ca3ac9ab mb/intel/coffeelake_rvp: Use CHIPSET_LOCKDOWN_COREBOOT
Currently, internal flashing is not possible due to FSP lockdown. Thus
let coreboot do chipset lockdown on all variants.

Change-Id: Ib25a0543bfee0889dce071f3b01725daabd0a0eb
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56407
Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26 12:21:26 +00:00
Jakub Czapiga ca3aa52cf8 tests: Add lib/libgcc-test test case
Add tests for src/lib/libgcc.c __clzsi2() implementation. Unlike GCC
implementation, coreboot one can handle zero input.

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I3f46071d0921e8c5edc5df3c296d11c77de01c88
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56257
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-07-26 07:32:43 +00:00
Raul E Rangel ca0606e04f arch/x86,lib/thread: Enable thread support in romstage
This change does the following:
* Pushes the cpu_info struct into the top of the stack (just like
  c_start.S). This is required so the cpu_info function works correctly.

* Adds the thread.c to the romstage build.

I only enabled this for romstage since I haven't done any tests in other
stages, but in theory it should work for other stages.

BUG=b:179699789
TEST=Boot guybrush with threads enabled in romstage

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I8e32e1c54dea0d0c85dd6d6753147099aa54b9b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-07-26 07:30:48 +00:00
Raul E Rangel e279d90d4d arch/x86,cpu/x86/mp_init: Switch cpu_info index type to size_t
The alignment for `struct cpu_info` is wrong on x86_64. c_start.S uses
the `push` instruction when setting up the cpu_info struct. This
instruction will push 8 bytes but `unsigned int` is 4 bytes. By making
it a `size_t` we get the correct size for both x86_32 and x86_64.

BUG=b:179699789
TEST=Boot guybrush to the OS

Suggested-by: Julius Werner <jwerner@chromium.org>
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I8ef311aaa8333ccf8a5b3f1f0e852bb26777671c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56573
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-07-26 07:30:36 +00:00
Raul E Rangel 474781b270 arch/{arm,ppc64,riscv}: Remove cpu_info
The structure and function are not currently used or implemented. x86 is
the only arch that currently implements it. It is currently used for
COOP_MULTITASKING and mp_init.

Keeping around the unused definitions leads to confusion.

BUG=b:179699789
TEST=none

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I0775ef03168f7f9c41b1b05cb8f12724d0458ba5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56572
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-07-26 07:29:16 +00:00
Raul E Rangel a2d83c68a3 lib/thread,lib/hardwaremain: Lazy initialize threads
By lazy initializing the threads, if a stage doesn't use them, they will
be garbage collected.

BUG=b:179699789
TEST=Boot guybrush to the OS and verify threads worked

Suggested-by: Julius Werner <jwerner@chromium.org>
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I7208ffb5dcda63d916bc6cfdea28d92a62435da6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56532
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26 07:28:33 +00:00
Raul E Rangel 7db7ee984c lib/thread,arch/x86: Move thread stacks into C bss
There is no reason this needs to be done in asm. It also allows
different stages to use threads. If threads are no used in a specific
stage, the compiler will garbage collect the space.

BUG=b:179699789
TEST=Boot guybrush to the OS

Suggested-by: Julius Werner <jwerner@chromium.org>
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ib5a84a62fdc75db8ef0358ae16ff69c20cbafd5f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56531
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26 07:28:08 +00:00
Aseda Aboagye b9d94ecd78 vboot/secdata_tpm: Add WRITE_STCLEAR attr to RW ARB spaces
It can be nice to update the TPM firmware without having to clear the
TPM owner.  However, in order to do so would require platformHierarchy
to be enabled which would leave the kernel antirollback space a bit
vulnerable.  To protect the kernel antirollback space from being written
to by the OS, we can use the WriteLock command.  In order to do so we
need to add the WRITE_STCLEAR TPM attribute.

This commit adds the WRITE_STCLEAR TPM attribute to the rw antirollback
spaces.  This includes the kernel antirollback space along with the MRC
space.  When an STCLEAR attribute is set, this indicates that the TPM
object will need to be reloaded after any TPM Startup (CLEAR).

BUG=b:186029006
BRANCH=None
TEST=Build and flash a chromebook with no kernel antirollback space set
up, boot to Chrome OS, run `tpm_manager_client get_space_info
--index=0x1007` and verify that the WRITE_STCLEAR attribute is present.
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Change-Id: I3181b4c18acd908e924ad858b677e891312423fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56358
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26 07:27:48 +00:00