Commit Graph

29363 Commits

Author SHA1 Message Date
Taniya Das 846f8c0ced coreboot: Add i2c clock API for qcs405
Add support of i2c clock enable, disable
and configure API.

Change-Id: Ia0b42357ac09bf0ab60aad18c44e5ef27fe9dac3
Signed-off-by: Shefali Jain <shefjain@codeaurora.org>
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32545
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-05 20:16:13 +00:00
Hannah Williams 1aac543a7a southbridge/intel/fsp_rangeley: Fix wrong parameters passed to outw
outw takes (value, addr) not (addr, value)

Change-Id: I6c00413ce9b9b6a3d5691d71ade2b12b08538622
Signed-off-by: Hannah Williams <hannah.williams@dell.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32842
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-06-05 16:45:35 +00:00
Frans Hendriks 1583fcd13f MAINTAINERS: Add maintainer to Facebook FBG1701
Add maintainers to the new mainboard port.

Change-Id: I620ea424cc26fa0218a74052863ea30700789e1b
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33224
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-06-05 13:04:10 +00:00
Frans Hendriks 43b6e2ed71 mainboard/facebook/fbg1701: Do initial mainboard commit
Initial support for Facebook FBG-1701 system.
coreboot implementation based on Intel Strago mainboard.

Configure 'Onboard memory manufacturer' which must match HW.

BUG=N/A
TEST=booting SeaBIOS and Linux 4.15+ kernel on Facebook FBG-1701

Change-Id: I28ac78a630ee705b1e546031f024bfe7f952ab39
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-06-05 13:03:43 +00:00
Frans Hendriks d622507450 lib/Makefile.inc: Add hexdump.c to postcar stage
hexdump() is not available in postcar stage.
Add hexdump() functionality to postcar stage.

BUG=NA
TEST=Booting Embedded Linux on Facebook FBG-1701

Change-Id: Ibdce911065c01b0a1aa81dc248557257d0e420b0
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2019-06-05 13:02:57 +00:00
John Zhao d3a73280cc src/drivers/intel: Avoid NULL pointer dereference
Coverity detects pointer fih as FORWARD_NULL. Add sanity check
for fih to prevent NULL pointer dereference.

BUG=CID 1401717
TEST=Built and boot up to kernel.

Change-Id: Ia6853e5302c87d9ffe52b942f067be56f6e77406
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
2019-06-05 13:02:32 +00:00
Elyes HAOUAS c53665ce55 nb/intel/x4x: Remove variable set but not used
Change-Id: I142ae6f7806b3f57b98a158e8f26592aed8fa452
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32939
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-05 11:44:13 +00:00
John Zhao 2ba303e49d src/arch/x86: Prevent attack on null pointer dereference
Clang Static Analyzer version 8.0.0 detects null pointer argument
in call to memory copy function. Add sanity check for pointer header
to prevent null pointer dereference.

TEST=Built and boot up to kernel.

Change-Id: I7027b7cae3009a5481048bfa0536a6cbd9bef683
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33051
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-06-05 11:43:39 +00:00
Arthur Heymans 742df5ad34 sb/intel/i82801gx: Include chip.h directly
Change-Id: I3d743e90444292be687999ab4f50aa89d514fbad
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33171
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-05 11:39:14 +00:00
Arthur Heymans fbf380abac mb/*/devicetree.cb: Remove unavailable PCIe ports
Some variants only support 4 PCIe ports so there is no need to have
those unavailable ports in the devicetree.

Change-Id: I154cae358fb7f862fc0c8eaa620474b37b5e6484
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30821
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-05 11:38:38 +00:00
Roy Mingi Park 06cfb21e24 mb/google/sarien: Fix SSD's power off sequence before going to S5
BUG=b:133389422
TEST=check SSD's power off sequence to meet PCIE requirement.
     SSD's reset should be cleared before clearing SSD's power EN Pin.

Change-Id: Ia106b805deafb8a442b56bcce91b51135cb32988
Signed-off-by: Roy Mingi Park <roy.mingi.park@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33182
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-04 16:49:46 +00:00
Prudhvi Yarlagadda 13539d2f9d qcs405: Add SPI driver support
Add SPI driver support in coreboot.

Change-Id: I813ba0b5cc8344c463c3e41ff6db80bc0d8ebd96
Signed-off-by: Prudhvi Yarlagadda <pyarlaga@codeaurora.org>
Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32058
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-04 14:16:45 +00:00
Prudhvi Yarlagadda 37e957f334 qcs405: Add UART support
Add support for UART driver in coreboot.

TEST=build & run

Change-Id: Id9626c68eadead8b8ec5ffbc08cab7b0ec36478f
Signed-off-by: Prudhvi Yarlagadda<pyarlaga@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29964
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-04 14:15:26 +00:00
Prudhvi Yarlagadda 1b05479a7f libpayload: Add UART for qcs405
TEST=build

Change-Id: I43164cf9eacc844af1d048f7b6ebbda96fc9d202
Signed-off-by: Prudhvi Yarlagadda <pyarlaga@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29957
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-06-04 14:14:58 +00:00
Nico Huber 12f0e42cb4 kconfig: Drop IS_ENABLED() macro
We keep its definition in libpayload, though, to maintain compatibility
with existing payload code. For now.

Change-Id: I8fc0d0136ba2316ef393c5c17f2b3ac3a9c6328d
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32230
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-06-04 13:33:40 +00:00
Elyes HAOUAS 2dbc095677 nb/intel/x4x/rcven.c: Remove variable set but not used
Change-Id: I13d6593e283f0a9e6603e19ccfda116f3b145e52
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32948
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-04 13:18:14 +00:00
Nico Huber ec017590e5 util/lint: Make usage of IS_ENABLED() an error
As long as we keep the IS_ENABLED() definition in libpayload for
compatibility, we should check that IS_ENABLED() usage doesn't
sneak back in.

Also remove all other IS_ENABLED() checks.

Change-Id: Id30ffa0089cec6c24fc3dbbb10a1be35f63b3d89
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32229
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-06-04 13:16:16 +00:00
Evgeny Zinoviev 086149eb32 mb/apple/macbookair4_2: Fix DRAM_RESET_GATE_GPIO
It's GPIO28 according to schematics.

Change-Id: I55be1ed178c818a17766e22cb2fd010412b8fe02
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33149
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-06-04 12:59:50 +00:00
Felix Singer ad5467d202 drivers/fsp20: Fix spelling in help text
Change-Id: Iab8d20a385bde31b29fa7766a87753fcc2d759b8
Signed-off-by: Felix Singer <felix.singer@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-06-04 12:05:35 +00:00
Arthur Heymans 59b6542bbc soc/intel/braswell: Use common cpu/intel/car code
The code in cpu/intel/car/romstage.c Does most of the things like
setting up timestamps, stack guards, entering postcar.

A functional difference is that the FSP header is searched for twice
instead of passed from the CAR entry to the C code. When using
C_ENVIRONMENT_BOOTBLOCK this needs to be done anyway (or a special
linker symbol kept across multiple stages is needed, which is likely
not worth the speedup).

Change-Id: I0f03e5a808f00157fdd807b104417a54e4bde7b2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32963
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-06-04 11:25:32 +00:00
Julius Werner 0e9116f0a1 device_tree: Make FDT property data non-const
FDT property data should not be const -- sometimes we need to update it,
for example when fixing up phandles in an overlay. On the other hand
it's occasionally desirable to put a string constant in there without
having to strdup() it all the time... let's just live with the tiny
implicit assumption that the data we'd want to modify (phandle
references, mostly) will never be added from string constants, and put a
cast in dt_add_string_prop().

Change-Id: Ifac103fcff0520cc427ab9a2aa141c65e12507ac
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32868
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-04 11:24:46 +00:00
Julius Werner 0d74653bd4 device_tree: Match debug output format to dtc -O dts output
This patch updates the device tree dumping functions (not compiled by
default but available for debugging) to output properties and nodes in a
format similar to .dts files that is very close to what dtc outputs when
you decompile a .dtb with it. This makes it easier to match device tree
dumps from coreboot with device tree dumps generated by other device
tree tooling.

This patch was adapted from depthcharge's http://crosreview.com/1536386

Change-Id: Ib40e50d906aff05473a70c4fc9b124d63232558c
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32867
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-04 11:24:34 +00:00
Julius Werner 6d5695fac5 device_tree: Add support for aliases
This patch adds support to lookup nodes via the "/aliases" mechanism in
device trees. This may be required for overlay support (don't quite
remember tbh) and is also just a generally useful feature. It was
adapted from depthcharge's http://crosreview.com/1249703 and
http://crosreview.com/1542702.

Change-Id: I1289ab2f02c4877a2d0111040384827e2b48a34a
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32866
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-04 11:24:01 +00:00
Julius Werner fbec63d15f device_tree: Have absolute paths start with '/'
Currently DT paths are *not* expected to start with '/'. This is not
what the spec says (see Devicetree Specification v0.2, 2.2.3 Path Names)
and also not what is done by Linux.

Change dt_find_node_by_path() to expect paths to start with '/' and add
a leading '/' to all DT path strings. Besides the compatibility with the
spec this change is also needed to support aliases in the future.

This patch was adapted from depthcharge's http://crosreview.com/1252770

Change-Id: Ibdf59ccbb4ead38c6193b630642fd1f1e847dd89
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32865
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-04 11:23:48 +00:00
Julius Werner f36d53c653 device_tree: Drop sub-node path lookup from dt_find_node_by_path()
Besides looking up a node with an absolute path dt_find_node_by_path()
currently also supports finding a sub-node of a non-root node. All
callers of the function pass the root node though, so it seems there
is no real need for this functionality. Also it is planned to support
DT path names with aliases, which would become messy in combination with
the lookup from a sub-node.

Change the interface of dt_find_node_by_path() to receive the DT tree
object instead of a parent node and adapt all callers accordingly.

This patch was adapted from depthcharge's http://crosreview.com/1252769

Change-Id: Iff56be4da2461ae73a7301dcaa315758d2a8c999
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32864
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-04 11:23:12 +00:00
Julius Werner 6702b68a79 device_tree: Add phandle caching and lookups
This patch caches phandles when unflattening the device tree, so we
don't have to look up the phandle property again every time we're trying
to find the phandle of a node. This is especially important when
supporting phandle lookups, which are also added. In addition we keep
track of the highest phandle in the whole tree, which will be important
for applying overlays later.

With this, dt_get_phandle(node) becomes obsolete because the phandle is
already available as a member variable in the node.

This patch was adapted from depthcharge's http://crosreview.com/1536385

Change-Id: I9cbd67d1d13e57c25d068b3db18bb75c709d7ebe
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32863
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-04 11:22:57 +00:00
Julius Werner 73eaec8168 device_tree: Add version checks
This patch adds a few more sanity checks to the FDT header parsing to
make sure that our code can support the version that is passed in.

This patch was adapted from depthcharge's http://crosreview.com/1536384

Change-Id: I06c112f540213c8db7c2455c2e8a4e8e4f337b78
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32862
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-04 11:22:47 +00:00
Julius Werner 9636a106d4 device_tree: Switch allocations to xzalloc()
The FIT code is already using xzalloc() everywhere, and that's the only
real consumer of device tree code right now. Chances are if you're
trying to unflatten an FDT and it doesn't fit into the heap you're
pretty much screwed anyway, so all the OOM handling feels a bit
unnecessary (and some functions will just silently fail because they
don't have a return value, which is bad). Let's just switch this all to
die on failed allocations.

Change-Id: I738f24d550a776653b2becd3d4f7d4d2cb3cc048
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32861
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-04 11:22:25 +00:00
Furquan Shaikh fca7c4d614 mb/google/hatch: Enable LTR for PCIe ports
Enable LTR for NVMe and WiFi PCIe ports so that they can use ASPM L1.2

BUG=b:134195632
TEST=Verified L1 substate with lspci on hatch:
Before: L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2- ASPM_L1.1+
After: L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+

Change-Id: I7fce60897b78dde12747ac7fb857c988d16118ab
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33161
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-04 11:20:42 +00:00
Furquan Shaikh a99ed13e33 libpayload/i8042/keyboard: Fix return value check for keyboard_cmd
CB:32951 ("libpayload: Reset PS/2 keyboard") added a call to reset
keyboard and check the return value of keyboard_cmd() to compare
against I8042_KBCMD_ACK. However, keyboard_cmd() already checks for
ACK and returns 1 or 0 based on whether ACK is received.

This change fixes the check introduced by CB:32951 to compare against
0 just like the other checks for keyboard_cmd(). Additionally, it adds
error messages for all failed commands in keyboard_init() to make the
prints consistent in case of failure.

BUG=b:134366527
TEST=Verified that logs do not contain "ERROR: Keyboard reset failed"
anymore.

Change-Id: Idcadaae12e0a44e404a1d98c6deb633d97058203
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-06-04 11:20:05 +00:00
Frans Hendriks 3cae9afbf9 vendorcode/eltan: Add vendor code for measured and verified boot
This patch contains the general files for the vendorcode/eltan that has
been uploaded recently:
- Add eltan directory to vendorcode.
- Add documentation about the support in the vendorcode directories.
- Add the Makefile.inc and Kconfig for the vendorcode/eltan and
  vendorcode/eltan/security.

BUG=N/A
TEST=Created verified binary and verify logging on Portwell PQ-M107

Change-Id: Ic1d5a21d40b6a31886777e8e9fe7b28c860f1a80
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30218
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-06-04 10:41:53 +00:00
Furquan Shaikh b2709ae0ae soc/intel/cannonlake: Do not read SPD again if index hasn't changed
With the recent refactoring of memory configuration in
CB:32513 ("soc/intel/cannonlake: Support different SPD read type for
each slot"), meminit_cbfs_spd_index ends up reading SPD from CBFS for
each slot. However, for mainboards that use the same SPD index for
each slot this is unneccessary. This change adds a check to see if
spd_data_ptr is not NULL and current spd index is the same as the last
call to decide if SPD read from CBFS should be skipped.

TEST=Verified that SPD gets read only once on hatch.

Change-Id: I91963b55cea534c92207b2cd9f0caa96df8f222b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33137
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Philip Chen <philipchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-04 02:40:08 +00:00
Subrata Banik ef1ab4d6d4 arch/riscv/Kconfig: Make correct default value for CONFIG_ARCH_RISCV_M
Change-Id: Ib9329904060cab48d527de1b1ccdab5b6fe71b99
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33144
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-04 01:54:15 +00:00
Arthur Heymans 8a2056cac4 mainboard/intel/saddlebrook: Remove unused functions
Setting up the SIO serial console is done in the bootblock.

Change-Id: Ideaf8f3dc0ee067e96d3fb5046071551c6d45329
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32985
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-03 21:21:31 +00:00
John Zhao 317cbd6f02 src/soc/intel: Avoid NULL pointer dereference
Coverity detects pointer mem_info as NULL_RETURNS. Add sanity check
for mem_info to prevent NULL pointer dereference.

BUG=CID 1401394
TEST=Built and boot up to kernel.

Change-Id: I9d78ab38b8b2dd3734e0143acfd88d9093f16ce6
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33152
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-03 18:24:06 +00:00
Nico Huber 9995418166 soc/intel: Replace UART_BASE() and friends with a Kconfig
Re-add the Kconfig CONSOLE_UART_BASE_ADDRESS. It was lost by accident
on APL at least. It is used outside of soc/intel/ scope, e.g. to con-
figure SeaBIOS.

As we only ever configure a single UART for the coreboot console, we
don't need different addresses for each possible UART. Which saves
us a lot of code.

Change-Id: I28e1d98aa37a6acb57b98b8882fc4fa131d5d309
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-06-03 15:23:49 +00:00
Arthur Heymans 10ed374d7d sb/intel/i82801ix: Select SOUTHBRIDGE_INTEL_COMMON_SPI
This allows to use the CONFIG_CONSOLE_SPI_FLASH.

Change-Id: I563c69ce6337d46380f889f42633e858ac207916
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33064
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-06-03 15:02:32 +00:00
Christian Walter 4b55935173 src/soc/intel/common/block/sgx: Add missing new lines
Added missing new lines to Debug Output.

Change-Id: I30f208a60661451bc0794c705113e8d19a68b0eb
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33035
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-03 13:35:39 +00:00
Marshall Dawson 920bab553e soc/amd/stoneyridge: Fix alignment in iomap.h
Change-Id: I79e8bc425d5db45abaeb655f86773f3bb1b2f8c4
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32933
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-06-03 13:35:30 +00:00
Elyes HAOUAS c6d503fb81 sb//nvidia/mcp55/mcp55.c: Remove variable set but not used
Change-Id: I40cae58a7a7c9c3c20367541853001510a59e42b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33061
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-03 13:34:02 +00:00
Elyes HAOUAS 6b7171b32c nb/amd/pi/00630F01/northbridge.c: Remove variable set but not used
Change-Id: Id5e762880ddfcb65872a50e8ffe10d86b3719b5d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33012
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-06-03 13:32:50 +00:00
Elyes HAOUAS 95794693cb sb/nvidia/ck804: Remove variable set but not used
Change-Id: Ia8586e229e04fa11696a846653a3a54909ca7c1a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33007
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-06-03 13:32:31 +00:00
Elyes HAOUAS 99f1d50335 cpu/amd/family_10h-family_15h: Remove variable set but not used
Change-Id: Ifc63ec5b588f8edcec5eda343ec9694332845045
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33006
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-03 13:32:19 +00:00
Elyes HAOUAS 4be1f8a2f6 sb/nvidia/mcp55: Remove variable set but not used
Change-Id: Ic8f6c264aedbdab0eacb6a99a32cc90336e08d84
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33011
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-03 13:30:12 +00:00
Elyes HAOUAS 156936b771 nb/amd/amdmct/mct_ddr3/mct_d.c: Remove variable set but not used
Change-Id: Icd9c0541d9006f4ebddcefff9d2355056af0c5c4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32972
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-03 13:29:59 +00:00
Elyes HAOUAS 1a7623bc1a drivers/aspeed/ast2050: Remove variable set but not used
Change-Id: Iedda92edf8c4eb7be037dcc0faa6fe8aa0c0754c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-06-03 13:29:26 +00:00
Elyes HAOUAS 19cb6c9980 sb/intel/fsp_rangeley: Remove variable set but not used
Change-Id: Ia2bc9bb0f0ece5ae3a57662b54f3e7e78ce00b19
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32942
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-06-03 13:29:08 +00:00
Elyes HAOUAS 9c8895fd88 nb/intel/sandybridge: Remove variable set but not used
Change-Id: I75f5d821e018932d3f10d84b7ebed362777fb17d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32938
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-03 13:28:34 +00:00
Elyes HAOUAS fa1f7216ce nb/intel/sandybridge: Remove variable set but not used
Change-Id: Iaac05f73d2ba892d3ec7ee2ac0c16a98f2fce5bc
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32926
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-03 13:28:03 +00:00
Nico Huber 10ed868d19 soc/intel/{skl,cnl,icl}: Drop soc_uart_set_legacy_mode()
This is never called: The only calling path is guarded by both
!DRIVERS_UART_8250MEM_32 and INTEL_LPSS_UART_FOR_CONSOLE but the
latter selects the former.

If somebody figures out how this is supposed to be used, we can
easily revive the implementation.

Change-Id: I96e304bdee4eadb52725027d0d662ef75f3d4307
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33093
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-03 13:26:00 +00:00