Change-Id: I2e4f1d1551141c6225e762631e52d71357112425
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This change updates the release notes for coreboot-4.14 to add
deprecation notice for SAR support in VPD for Chrome OS platforms.
BUG=b:173465272
Change-Id: If6d511a22a3a2a31671dac91e57e801134d4ecf8
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51486
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The X11SSH-LN4F and X11SSH-F are very similiar. They both use the same
PCB and use the same Supermicro BIOS ID. The X11SSH-LN4F has 4 NICs in
difference to the X11SSH-F which only has 2 NICs. The two additional
NICs aren't populated on the X11SSH-F. Enable the PCIe root ports
connected to the two additional Intel NICs.
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Change-Id: Id4e66be47ceef75905ba760b8d5a14284e130f63
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
The current values are actually for 32MiB and result in a brick if used
with a 16MiB chip because of the invalid bios region.
Change-Id: I08337394ce0d6e31e5c03cda2bfb3b9f0282f2c3
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51322
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Configuring touch controllers to use edge-triggered interrupts is not
recommended as it is very easy to lose an edge when kernel drivers
disable the interrupt for one reason or another, and recovering from
this condition requires workarounds in the kernel.
Unfortunately the example setting up a touchpad used edge-triggered
interrupts, and this set up has been propagating through the boards.
Let's switch the example to use level interrupts instead.
Change-Id: I4dc8b91ed070ce117553b00a087ad709aeaf16af
Signed-off-by: Dmitry Torokhov <dtor@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
`bincfg` is not creating anything new, it just converts
from text to binary.
Change-Id: I14e67ee8bc449d171a951f6edeaa9f9d0c04dbe1
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51319
Reviewed-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It’s good practice to put the unit into the name.
Change-Id: I1493f61d4e495c22f09abf1829bb2eab9b1fd2b6
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50517
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
There has been some repeated discussion about how header includes should
be formatted, specifically on the topic of chain-including. The coding
style currently doesn't say anything about the topic but clearly people
have some basic assumptions. This patch tries to codify some common
ground rules that are supposed to reflect the existing practice.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ibbcde306a814f52b3a41b58c7a33bdd99b0187e0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This is the new output of the util_readme.sh script.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ia46924474f75692192ef4b52aab714f5071f9534
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48966
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tested with TianoCore payload (UefiPayloadPkg).
Working:
- PS/2 keyboard, touchpad
- Both DIMM slots
- Both NVMe ports
- SATA port
- All USB ports
- Webcam
- Ethernet
- Integrated graphics
- Internal microphone
- S3 suspend/resume
- Flashing with flashrom
- Booting to Ubuntu Linux and Windows
Not working:
- Discrete/Hybrid graphics
- Internal speakers
These two require new drivers to work correctly, which will be added and
enabled later.
Change-Id: Iae6e530dcd52df3642cdfe74b65bfff5aa0dd402
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47892
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Put this in a new directory called 'infrastructure' and make a link
and an index.md file for the directory.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I54a0204e7525a25f2fd717a73007b304aac67396
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43984
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Unlike Ivy Bridge series, there isn't a method to flash coreboot
internally when running vendor firmware (yet). Until someone finds a way
to bypass flash protections, the first flash has to be done externally.
Change-Id: Idaff264f2b7277516d69d1323f1a0c885b28c3db
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49848
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Drop LPC pad configuration code since all boards now do pad
configuration on their own. The comment about LPC_CLKRUNB when using
eSPI is moved to `Documentation/getting_started/gpio.md`.
Change-Id: I710d6aee8c3b2c8282cd321cd0688b9b26abea07
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49410
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The bugs happen on real hardware or in qemu with KVM enabled.
The very same code runs on some real devices and it runs in qemu
with KVM disabled.
The bugs are so strange that no root cause could be found yet.
Change-Id: I01050f2e38f92c6b96e3258a5b619aa9ee685acc
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44733
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Do not mislead newcomers into thinking the GM45 series laptops are hard
to flash. Describe the simple coreboot flashing procedure first, then
explain how to remove the ME firmware and use a custom flash layout.
Also, reword a sentence on the simple flashing procedure for clarity.
Change-Id: Ie83ec3d20f00e9d9c869e483e24d601506857f07
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48604
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Swift Geek (Sebastian Grzywna) <swiftgeek@gmail.com>
Reviewed-by: Evgeny Zinoviev <me@ch1p.io>
This change adds details memory mapped window handling in cbfstool
required for x86 platforms. It also captures the details about the
newly added support for multiple decode windows.
BUG=b:171534504
Change-Id: Icf970f951e56d717e6a4f8845fc73f10d5a21dd0
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
DeltaLake Open System Firmware stack (FSP/coreboot/Linuxboot) has
reached EVT exit parity. Update the documentation accordingly.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I7cce855d207a53b1d3cd497b74cdc0b00027a3ce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48252
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
- Drop issue about non-working TianoCore with Aspeed NGI. see CB:35726
- Add missing reference to X11SSH-F
- Drop TODO reference; there are no TODOs left
Change-Id: I5becfa9ea01a0d9d651c6b51b30ebfcedb6412a5
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48101
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Drop the TODO comment, since there is no TODO left. Also drop the now
obsolete TODO section from the board documentation.
Change-Id: I4192aaedc1429c8ff1bd7c52baa4741e1df0d0c5
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48126
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
- Drop vanished issue on PCIe warning
- Drop TODO section, since the TODOs are done
- Document the jumper J6, that was not documented by the vendor. Its
function has been determined by dissecting a dead board.
- The flash is not socketed anymore. Drop that note and compress the
whole paragraph. Also add a note about flashing via the BMC web
interface.
Change-Id: I2b5a08a6b6d80717621d6a30f31829fe4b84891a
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Start a new section *Notes* for these kind of information.
Change-Id: I86be22cebb96e6f07676a9bc52794a4c12dad3e4
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47762
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use angle brackets so that they appear as links, and update a link to a
Gerrit change to use the current format.
Change-Id: I41f82986429dcfd1cbc5b5c088a0c47bd24a57c4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47812
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds support for the Kontron mAL10 COMe module with the
Apollo Lake SoC together with Kontron T10-TNI carrierboard.
Working:
- UART console and I2C on Kontron kempld;
- USB2/3
- Ethernet controller
- eMMC
- SATA
- PCIe ports
- IGD/DP
- SMBus
- HWM
Not tested:
- IGD/LVDS
- SDIO
TODO:
- HDA (codec IDT 92HD73C1X5, currently disabled)
Tested payloads:
- SeaBIOS
- Tianocore, UEFIPayload - without video, EFI-shell in console only
Tested on COMe module with Intel Atom x5-E3940 processor (4 Core,
1.6/1.8GHz, 9.5W TDP). Xubuntu 18.04.2 was used as a bootable OS
(5.0.0-32-generic linux kernel)
Change-Id: Ib8432e10396f77eb05a71af1ccaaa4437a2e43ea
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39133
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Fill in some blanks for 4.13, mark it done, add template for 4.14.
Also update the list of vboot supported boards.
Change-Id: Ie593efe515136a3b06620db6f0dbe3da00df7e9b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47801
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This change adds details about the new resource allocator v4 in
coreboot to the release notes for 4.13.
Change-Id: I7071bdf0faffda61fc5941886c963181939c07e3
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
While some of these have little impact, they are worth mentioning here.
Change-Id: Idbf629ae77b8918ff1d93edb7b6c4669bbbe17df
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47444
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Work on this mainboard was abandoned and never finished. It's not really
usable in its current state, so let's get rid of it.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I4cd2e2cd0ee69d9846472653a942fa074e2b924d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The code is based on autoport, with necessary modifications.
This laptop uses SMSC MEC1322 embedded controller, but the EC
interface is the same as the EliteBook laptops of previous generations
that use KBC1126 EC. So it still uses ec/hp/kbc1126, but does not need
EC firmware inserted into CBFS. We also need to leave the end of the
OEM flash content untouched, so the default ROM size is set to 12MiB
instead of 16MiB, and we need to modify the IFD when flashing.
Thanks to persmule for providing the laptop and pointing out how to
program the system flash chip of it.
Change-Id: I2328c43cbb1f488aa1d0ddd9116814d971e5d8ae
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45578
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Patrick Georgi