Camera LED will blink several times as sensor is being probed during kernel boot.
Configure _DSC to ACPI_DEVICE_SLEEP_D3_COLD so that driver skips
initial probe during kernel boot and prevent privacy LED blink.
BUG=b:274634319
TEST=Build and boot on Craask. Verify & observe Camera LED blinking behavior.
Change-Id: I78ed5efe1e2c071d817c1e0455271886e89e63c7
Signed-off-by: Jimmy Su <jimmy.su@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74728
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The support for a spd.bin from CBFS was removed for all mc_ehl boards in
commit 833bb448c5 (mb/siemens/mc_ehl: Remove spd.bin from CBFS).
There is still a remaining comment in romstage_fsp_params.c referring to
the removed capability. This fix removes the spd.bin related part of the
comment to stay consistent with the code.
Change-Id: I669ee1c33d1d1c47764640982f71129195e63f14
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74801
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
With the profile ATLAS_PROF_REALTIME_PERFORMANCE it is desired to not
have the option to be able to enter sleep. The reason is that Microsoft
Windows goes to sleep after 30min of inactivity by default.
TEST: See that Microsoft Windows 11 has no 'Sleep' option in the start
menu.
Change-Id: I424db7e712a705c628aa3a10a486d3313404987a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74421
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
This allows mainboards to override available sleep states at runtime.
This is done by adding a IntObj in SSDT that DSDT consumes to override
the available _Sx states.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ic21830c1ef9c183b1e3005cc1f8b7daf7e9ea998
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74762
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
FSP is fractionally faster at configuring ASPM (1,118,688 vs 1,122,205)
but coreboot's configuration results in lower power consumption of
approximately 0.5W when idling - the reason why is unknown.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ib15eaede956f0aa55118d093fdff0fd9487df250
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74520
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
FADT duty_width/duty_offset fields, together with P_CNT (previously
P_BLK) IO address are provided with _PTC entry.
FADT p_lvl2/3_lat fields had values that disabled C2/C3 state
transitions so _CST entries are not required.
Change-Id: I629cd0793f6a64e955e197400efaa7d9d898e775
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74440
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Add functionality to ensure that the FPMCU is power cycled long enough
on boot to ensure proper reset.
This solution relies solely on coreboot to sequence the power and reset
signals appropriately (150ms on boot).
-Confirmed power is off for 150ms on boot.
-Confirmed RCC_CSR of FPMCU indicates power cycle occurred.
-Confirmed reset is de-asserted approx 3ms after power application
(target >2.5ms)
BUG=b:245954151
TEST=Confirmed FPMCU is still functional on Nami and timings are
as expected.
Change-Id: I0a23bda96bc2ea90be81a2310605f75c55c0a839
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73212
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Add functionality that allows a variant SKU to have a specific set of
GPIO configs in romstage (modeled after the existing one in
ramstage)
BUG=b:245954151
TEST=builds
Change-Id: I593a23951306908fadc00e6bc8d9d310f09c5e4b
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
I forgot to remove these in commit 0fe36db154eb ("ACPI: Make FADT
entries for SMI architectural").
Change-Id: Ib1bc1dad6053ddb0454d4510917fd2bcf0901f35
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74811
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
For AMD, replace name RTC_ALT_CENTURY with RTC_CLK_ALTCENTURY
that points to same offset. Since the century field inside
RTC falls within the NVRAM space, and could interfere with
OPTION_TABLE, it is now guarded with config USE_PC_CMOS_ALTCENTURY.
There were no reference for the use of offset 0x48 for century.
Change-Id: I965a83dc8daaa02ad0935bdde5ca50110adb014a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74601
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
On boards with RECOVERY_MRC_CACHE FMAP section, populate type 0x63 BIOS
directory entry in RO with that section. If the RECOVERY_MRC_CACHE
section is not present, then fall back to RW_MRC_CACHE.
BUG=b:270569389
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Ic5ac87685eaa5fec717e3efa4df7af511b4ce8aa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73257
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
This ports back commit d75ee46d3c ("soc/amd/picasso/acpi: Change PCI0
BAR window") to Stoneyridge so that the correct end of the non-fixed
MMIO region gets reported in PCI0's _CRS method.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I19153947cbb1b1b684291765eb1902caac65b9ec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74809
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
This ports commit 8c28e51a16 ("soc/amd/picasso: fix host bridge bus
numbers") back to Stoneyridge so that the correct number of PCI buses
gets reported from PCI0's _CRS method. The MCFG ACPI table already had
the correct last bus number.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I40121ab0e0438281192b6a0bec8dbecdc1749379
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
The number of NID entries was too high for the Realtek
and Intel sound cards, preventing the verb table from
loading. Now the values are correct; it loads as intended.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I79825313a4801c120a0a2a321cbabab7c728aa71
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74241
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Change the fallback value of the `fn_ctrl_swap` option to 0, which
is disabled.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I9fcbb497f14ed0c97ff05c6c01a3929522786781
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74744
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
The EC will constantly update the battery variables approximately
every 60 seconds; they should be used unmodified, rather than
trying to change them.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I3cff0ac6a322018cbca33b5f90dd62b3475da25c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Commit 5103b87a4d ("mb/starlabs/starbook/adl: Add an option to
enable Hot Plug") introduced an option to enable Hot Plug for the
SSD. The port was set to 4 (RP5) which is the wireless card. Change
this to 8 (RP9) which is the SSD.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I884f4997d73e31bd422477952466f168afad66a1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74738
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
The MAX_PSP_ENTRIES constant reserves space for the psp directory table
entries. This table is aligned to 4K and the next binary is also aligned
to 4K. The number of psp directory entries on Birman exceeds the
previous limit, so increase it to the maximum that will fit in a 4K
block.
TEST=timeless builds for Birman unchanged
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I297edc9cccffde0ad1ce7461b375542f9f2f7c23
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73653
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bao Zheng <fishbaozi@gmail.com>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Some of the chip.h files in the tree are missing the include guards.
This patch adds them in order to avoid potential redefinions of symbols
contained in these headers, when they are included multiple times in
static.c generated by sconfig.
Change-Id: I550a514e72a8dd4db602e7ceffccd81aa36446e3
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
VGA defined the extended ASCII set based on CP437, but the function
vga_write_text() accepts a signed char array.
This will cause unnecessary confusion that if we want to print u with
umlaut (code=129 in CP437), we need to explicitly cast it to -127 in
signed char.
Since we still want to leverage the built-in string utilities
which only accepts const char*, we still need to cast it to signed char
while processing, and cast it back to unsigned once we write into the
frame buffer.
BRANCH=brya
BUG=b:264666392
TEST=emerge-brya coreboot chromeos-bootimage
Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org>
Change-Id: If555bbc05f40ce3f02339c0468afff6dda8b7ded
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Because SPL fuse needs to be set before the FW lock. So enable
Markarth project to send the fuse SPL (security patch level)
command to the PSP.
BUG=b:279499511
BRANCH=none
TEST=FW_NAME="Markarth" emerge-skyrim coreboot chromeos-bootimage
Then get "PSP: SPL Fusing Update Requested." in the firmware log.
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I8fbbd89d11b1bdb2c95c761955c10bedb366fd70
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74753
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
walkcbfs_asm is a simple CBFS implementation in assembly to find a file
on a system with memory-mapped SPI flash. It seems to be mostly unused
nowadays and is only still called for early microcode loading on some
old systems (e.g. FSP 1.1 and older).
Using this implementation with CONFIG_CBFS_VERIFICATION is unsafe
because it does not verify the hashes the way the normal CBFS code does.
Therefore, to avoid potential security vulnerabilities from creeping in,
this patch makes sure the code cannot be compiled in when
CBFS_VERIFICATION is active. That means it won't be supported on the old
boards using this for microcode loading.
Ideally CONFIG_CBFS_VERIFICATION should have a `depends on` to make this
dependency more obvious in menuconfig, but the configs actually using
this code are not easy to untangle (e.g. CONFIG_MICROCODE_UPDATE_PRE_RAM
is just set everywhere by default although only very few boards are
really using it, and a lot of different old Intel CPU models are linking
in src/cpu/intel/car/non-evict/cache_as_ram.S without being united under
a single Kconfig so that's not easy to change). To keep things simple,
this patch will just prevent the code from being built and result in a
linker error if a bad combination of Kconfigs is used together. Later
patches can clean up the Kconfigs to better wrap that dependency if the
affected boards are still of enough interest to be worth that effort.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I614a1b05881aa7c1539a7f7f296855ff708db56c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74243
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
According to SPI programming guide, a region limit of 0 as well as
region base of 7FFFh indicates an unused/reserved region.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I790d7f5631ecef3043b2c17c41430dc4fd854f72
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74735
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This patch adds new USB_DB FW_CONFIG to enable support for USB4 ANX7452
Rev 2.
BUG=b:279647370
TEST=Able to build and boot google/rex with Proto 2 SKU
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I878b591e5919d05d3c5fc2eefdeb492e95d4f7b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74775
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Set edp_panel_t9_ms to 8ms which means it will delay 8ms
between backlight off and vary backlight off.
BUG=b:271704149
BRANCH=Skyrim
TEST=Build; Verify the UPD was passed to system integrated table;
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I952d05b18e29cf30256f43562a5052007c5c6268
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74790
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add UPD parameter for eDP power sequence adjustment.
The edp_panel_t9_ms parameter is set for bloff to varybloff.
BUG=b:271704149
BRANCH=Skyrim
TEST=Build; Verify the UPD was pass to system integrated table.
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: Id651c9cc4d6f4e27f6c78ca10ca12936d66ef43b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74789
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add UPD edp_panel_t9_ms for eDP panel sequence adjustment.
BUG=b:271704149
BRANCH=Skyrim
Test=Build/Boot to ChromeOS
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: Idc1a212e9c203584a6497fd6cbd3f995eeb030f2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74788
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Rename the UPD pwr_on_vary_bl_to_blon to edp_panel_t8_ms to
match the eDP sequence timing in milliseconds.
BUG=b:271704149
BRANCH=Skyrim
Test=Build/Boot to ChromeOS
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: Iecdfe47cd9142d8a1ddeee0ec988d37b2a11028e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74787
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Instead of having multiple instances of the same magic numbers in the
code, introduce and use the PCI_IO_CONFIG_INDEX and PCI_IO_CONFIG_DATA
definitions.
TEST=Timeless build for Mandolin results in identical image.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If6f6f058180cf36cae7921ce3c7aaf1a0c75c7b9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
which is based on Intel Sapphire Rapids Scalable Processor chipset
which was product launched on Jan. 10 2023.
The site-local/* files are Intel binaries that are not published yet
but coreboot build validation system would skip these binaries when
they are in "site-local" directory.
Please make sure you have the correct Intel binaries for your AC CRB
and place them to the right location accordingly.
CONFIG_PAYLOAD_FILE="site-local/archercity/linuxboot_bzImage" is
LinuxBoot payload, there are several ways to build it, one way is to
build it from the x86_64 qemu example from osf-builder:
git clone https://github.com/linuxboot/osf-builder
cd examples/qemu; make kernel
commit ae90fc0bb (soc/intel/xeon_sp/spr: Default to X2APIC support)
would enable DEFAULT_X2APIC_RUNTIME, your LinuxBoot kernel needs to
enable X2APIC support, otherwise need to set CONFIG_XAPIC_ONLY=y in
your defconfig.
Change-Id: I15aefc3edb2d22fc00d854850e948fe2048a992e
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71969
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com>
Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
TEST=fsp_print_guid() output doesn't get cobbled with other serial
output and now separated by a newline character.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I8d47dbc5d493f86f14a1bbcf9cb5c16c0e12b841
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74781
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
The MIPI panels will be used on the detachable variant starmie, and
there will be different MIPI panels used on starmie. In order to make
the different panels functional on unprovisioned devices, it needs
to pass the SKU ID and panel ID to the payload to load the matched
device tree for kernel. From the schematic, the starmie variant
will read the LCM ID from ADC channel 5.
BRANCH=corsola
BUG=b:275470328
TEST=boot starmie and see FW screen display
Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com>
Change-Id: I6339dc3c177fb8982f77fb3bd32dc00da735fce4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74135
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com>
It is unused. The use of field irq is problematic as it should
appear relative to IOAPIC GSI bases in the devicetree.
Change-Id: I460fd5fde3a7fba5518ccfc153a266d097a95a39
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74357
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The signals for the NV33 regulator were swapped (enable and power
good). Switch these back to the way they should be:
GPIO_NV33_PWR_EN GPP_E1
GPIO_NV33_PG GPP_E2
BUG=b:269371363
TEST=builds
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Change-Id: Ic2a53103e1feadd7ecebd4bed02dcc34410b8e3b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74693
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Match-any-character operators (eg. ".*") shall not match newline
characters for BANNER_REGEX, since given regular expression
matches newline explicitly.
Add REG_NEWLINE flag to `regcomp` call.
BUG=b:278718871
TEST=Boot firmware on skyrim, reboot.
Run `cbmem -2`.
`cbmem -2` returns second-to-last boot log.
Change-Id: I9e924349ead0fa7eea8b9ad5161138a4c4946ade
Signed-off-by: Konrad Adamczyk <konrada@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74742
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Because WD SSD drive isn't holding the clock low for some reason.
So we change to read eMMC clkreq signal instead.
BRANCH=none
BUG=b:274377518
TEST=emerge-skyrim coreboot chromeos-bootimage and verify ok.
Change-Id: I1329386631dc54209db54ac146e4aafe95b6a3ac
Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74599
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
This patch implements helper function get_cse_ver_from_cbfs() to
retrieve the CSE Lite version from CBFE RW's metadata and calls
the helper function from cse_check_update_status()
TEST=Verified CSE Lite version in coreboot boot log
Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com>
Change-Id: Ie1bf186adfc3f87826a7ce9b0167a6bbe6767299
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74755
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Himanshu Sahdev <himanshu.sahdev@intel.com>
By default, coreboot includes support for all the different types of SPI
ROMs. Excluding the unused ROM types shrinks ramstage by almost 4k.
BUG=b:267735039
TEST=Build & Boot ROM
BRANCH=Skyrim
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: If6e402269d1f2cac8256d478eb36743441497bdf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72769
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Commit c7b8809f155a ("soc/amd/common/block/gfx: Use TPM-stored hash
for vbios cache validation") replaced checking the vbios signature
(first two bytes) with checking against a TPM-stored hash, but there
exists an edge case where the empty cache can be hashed and therefore
never updated with the correct vbios data. To mitigate this, re-add
the signature check to ensure that an empty cache will never be hashed
to TPM.
BUG=b:255812886
BRANCH=skyrim
TEST=build/boot skyrim w/selective GOP enabled, flash full firmware
image, ensure GOP driver is run until cache updated with valid data
and hashed to TPM.
Change-Id: Id06a8cfaa44d346fb2eece53dcf74ee46f4a5352
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74525
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
In order to make supported sleep states a runtime configuration option
use a variable. A follow-up patch will implement updating this variable
based on an SSDT generated IntObj.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I6910c2c75e668e6f75a6f431813edeb59d52dd93
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74761
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Since skylake Intel hardware does not support this sleep state. Trying
to enter S1 by having the OS enter sleep results in a system hang on at
least Alder lake (prodrive/atlas).
CONFIG_SOC_INTEL_COMMON_BLOCK_PMC is a good proxy whether devices
support 'skylake style' PMC PCI device for ACPI registers.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ic9e19410696240755e8714db53a0525284f3a2da
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74760
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Remove rtd3 for emmc device on taeko
BUG=b:271003060
TEST= emerge-brya coreboot, flash to DUT and can boot to OS
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: I21191c9762a00ba137892e680d533f7dc3b53e86
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Jimmy Su