Commit Graph

10867 Commits

Author SHA1 Message Date
Kyösti Mälkki 232ae17718 AGESA fam12: Fix entry to cimx/sb700
Move SB700 calls to match comments and changes already made for
family14 et al.

Change-Id: I20a84e487ba346f63dd4454447077e0d2fd12c89
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6222
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-14 19:48:29 +02:00
Kyösti Mälkki 7b23ae0e89 AGESA: Trace execution with AGESAWRAPPER()
Implement logging just once to have uniform output.

Change-Id: I8db694a3bf6b1af459bdf98f7acb99edf4dd07f7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6180
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-14 19:48:00 +02:00
Edward O'Callaghan 06ff7268f6 AGESA: Fix error status code return type to enum from UINT32
AGESA correctly uses the enum AGESA_STATUS type whereas boards use a
mess of UINT32 typecasts.

Also no need to shout VOID. We are not that careful on changing
all cases of VOID->void or whitespace issues as these files will
get merged with follow-ups.

Change-Id: I16ccfcc73cda6b917c7ff5fd42ee2cd04e7dc0dd
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6182
Tested-by: build bot (Jenkins)
2014-07-14 19:47:25 +02:00
Kyösti Mälkki 9f0a2be165 AMD SPI: Optimise for longer writes
Leave it to the implementation of flash->write() to split the writes
to match SPI controller and SPI flash part restrictions. This allows
for some optimisation for auto-address-increment (AAI) commands.

Kconfig AMD_SB_SPI_TX_LEN can be kept as local.

Change-Id: I4a8bc55ab7eb0eeda8f25003a8f5ff2a643ab7a7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6164
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-14 19:43:03 +02:00
Kyösti Mälkki 1110495de9 SPI: Split writes using spi_crop_chunk()
SPI controllers in Intel and AMD bridges have a slightly different
restriction on how long transactions they can handle.

Change-Id: I3d149d4b7e7e9633482a153d5e380a86c553d871
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6163
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-14 19:42:49 +02:00
Kyösti Mälkki 77d1280d0c SPI flash: Fix alignment checks in Page Program commands
There are two separate restrictions to take into account:

  Page Program command must not cross address boundaries defined by the
  flash part's page size.

  Total number of bytes for any command sent to flash part is restricted
  by the SPI controller capabilities.

Consider

  CONTROLLER_PAGE_LIMIT=64, page_size=256, offset=62, len=4.
  This write would be split at offset 64 for no reason.

Consider

  CONTROLLER_PAGE_LIMIT=40, page_size=256, offset=254, len=4.
  This write would not be split at page boundary as required.

We do not really hit the second case. Nevertheless, CONTROLLER_PAGE_LIMIT
is a misnomer for the maximum payload length supported by the SPI controller
and is removed in a followup.

Change-Id: I727f2e7de86a91b6a509460ff1f374acd006a0bc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6162
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-14 19:42:27 +02:00
Luigi Semenzato 562db3bb3f libpayload: find source of input characters
This change makes it possible for vboot to avoid an
exploit that could cause involuntary switch to dev mode.
It gives depthcharge/vboot some information on the
type of input device that generated a key.

BUG=chrome-os-partner:21729
TEST=manually tested for panther
BRANCH=none
CQ-DEPEND=CL:182420,CL:182241,CL:182946

Change-Id: I87bdac34bfc50f3adb0b35a2c57a8f95f4fbc35b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/182357
Reviewed-by: Luigi Semenzato <semenzato@chromium.org>
Tested-by: Luigi Semenzato <semenzato@chromium.org>
Commit-Queue: Luigi Semenzato <semenzato@chromium.org>
Reviewed-on: http://review.coreboot.org/6003
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-12 20:19:14 +02:00
Matt DeVillier f4d1f3a4d9 google/panther: adjust critical temp
Set critical temp to match newer devices

Change-Id: I11f32297a9b8c9a3554821b5d1cd723d8d9e2b69
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: http://review.coreboot.org/6023
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-12 20:17:48 +02:00
Stefan Reinauer 4923c399f3 google/panther: Force enable ASPM on PCIe Root Port 4
BUG=chrome-os-partner:21535
BUG=chrome-os-partner:25990
BRANCH=panther
TEST=manual: Boot on Panther and look in /sys/firmware/log for
the string "PCIe Root Port 4 ASPM is enabled"

Change-Id: I294571c113a8909adb2e97afca92aef9a1af917c
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/187153
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: Stefan Reinauer <reinauer@chromium.org>
Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: http://review.coreboot.org/6007
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-12 20:17:03 +02:00
Stefan Reinauer c63ad997a5 google/panther: acpi: Fix unstable fan behavior on boot + resume
FLVL is used to keep track of which thermal zones are active, but it is
not initialized upon boot / resume. An initial value of zero corresponds
to all zones being active, which causes the fan to spin at max speed
until the OS changes zones. Fix this annoyance by initializing FLVL to
the lowest temperature zone.

Also, fix a related bug where FLVL may jump to an undesired value. For
example, if FLVL=3 (zones 3 + 4 active), and zone 0 is set to off (it's
already off!), FLVL would previously become 1 (zones 1 + 2 + 3 + 4
active!). Fix this by not taking zone ON / OFF actions if our zone is
already ON / OFF.

BUG=chrome-os-partner:25766, chrome-os-partner:24775
TEST=Suspend / resume on Panther 20 times, verify that thermal zone after
resume matches expectation based upon temperature. Also, stress system
and verify thermal zones become active according to temperature
increase.

Change-Id: Ic60686aa5a67bf40c17497832b086ba09d56111a
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/186455
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org>
Tested-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/186669
Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
Tested-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: http://review.coreboot.org/6006
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-12 20:17:01 +02:00
Stefan Reinauer 123fa68987 google/panther: Fix RW ramstage index
Without this patch coreboot will always use the read-only version
of ramstage, even if there is a read-write version available.

BRANCH=panther
BUG=chrome-os-partner:25870
TEST=Install different RO and RW version, check in cbmem log that
     coreboot's romstage and ramstage have different timestamps
     in their banners.

Change-Id: I723a3d4479d59534660728d891a9f40a077b4ef0
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/186664
Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
Tested-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/6005
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-12 20:17:00 +02:00
Mohammed Habibulla 3d24edab2c google/panther: Add new thermal values
Based on latest thermal report

BUG=chrome-os-partner:24532
TEST=boot tested on panther
BRANCH=panther

Change-Id: I4b8639f926fc3cf57eb5329818b9b912bfbe222d
Signed-off-by: Mohammed Habibulla <moch@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/186113
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: http://review.coreboot.org/6004
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-12 20:16:59 +02:00
Stefan Reinauer 9b43edf36c google/panther: Avoid shutdown when thermal sensor is unavailable
When the thermal sensor on Panther is unavailable (early on resume)
it will return 0x80 which causes our AML thermal code to overflow,
which causes the system to shut down. Instead, return a reasonable
value in those cases so that the system will continue running until
the sensor gets back on its feet.

BUG=chrome-os-partner:24918
BRANCH=panther
TEST=suspend_resume_test survived more than 100 iterations on Panther

Change-Id: Ib2d714c39d353ce2415361bc6590784a3f6837d2
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/182369
Tested-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: http://review.coreboot.org/6002
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-12 20:16:58 +02:00
Stefan Reinauer a0819eb38d google/panther: Re-read temperature if current reading would cause power-off
Sometimes the SuperIO seems to provide wrong readings, especially early
on after a resume from suspend. This will cause the system to power off.
If that happens, wait for 1s and read again, to make sure the high
temperature value was not just a flaky read.

BUG=chrome-os-partner:24918
BRANCH=panther
TEST=Boot tested on Panther.

Change-Id: Ib3768528d90e34448e96ad587b2503d8d8b1a775
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/182188
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: Stefan Reinauer <reinauer@chromium.org>
Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: http://review.coreboot.org/6001
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-12 20:16:56 +02:00
Stefan Reinauer 06946cabd9 google/panther: Disconnect speaker and mic in verb table
There is no speaker and no builtin microphone in this system,
hence disable them in the verb table.

BRANCH=panther
BUG=chrome-os-partner:24230
TEST=Boot Panther, see Microphone and Speaker disappear
     in Audio Settings

Change-Id: I32bacec38ba3ba0c2359a8fc94e12af64f576012
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/182006
Reviewed-by: Dylan Reid <dgreid@chromium.org>
Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
Tested-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: http://review.coreboot.org/6000
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-12 20:16:55 +02:00
Stefan Reinauer a0eeba47a1 google/panther: Disable DEVSLP for SATA
Some SSD modules don't support DEVSLP correctly due to their
firmware. Since the power savings are minimal, don't use
DEVSLP to prevent potential problems. Some of the symptoms
are that sometimes this causes USB devices to not work properly.

BUG=chrome-os-partner:23186,
BRANCH=panther
TEST=Boot tested on Panther

Change-Id: Iba3f721c73e0e760b6a9861ca23480ddb923df40
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/181957
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/5999
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-12 20:16:54 +02:00
Stefan Reinauer 1abeef6005 google/panther: Add ACPI code to support wake-on-lan
There needs to be an ACPI linkage to provide the power resource
needed to wake this device so the kernel will enable the SCI
before going to suspend.

A link is added for both NIC and WLAN, but it is only tested
on the NIC.

This is a forward port from Duncan's beltino patch.

BUG=chrome-os-partner:24657
BRANCH=panther
TEST=build and boot on panther, suspend and wake with etherwake

Change-Id: I2804d2e904e26d6e34f5a177f0dabc1aaa3f0288
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/181752
Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
Tested-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: http://review.coreboot.org/5998
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-12 20:16:53 +02:00
Stefan Reinauer 84570d6c5b google/panther: Update Fan Policy
Update fan policy according to Panther thermal report.

CPU Temp. Readings | PWM
-------------------+------
 40C               |  42%
 50C               |  42%
 83C               |  80%
 90C               |  90%
 96C               | 100%

BUG=chrome-os-partner:24532
BRANCH=panther
TEST=boot tested on Panther

Change-Id: I60f04d8b038c561b87dad505bbf058100119cc23
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/181666
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
Tested-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: http://review.coreboot.org/5997
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-12 20:16:52 +02:00
Stefan Reinauer a3f061bf22 google/panther: Disable power-failure gating for the PSON# signal
When the system loses AC power, the system will power back on
automatically as soon as the AC power is reapplied.

BUG=chrome-os-partner:24066
BRANCH=firmware-panther-4920.24.B
TEST=boot tested on panther

Change-Id: I37ddc5a162afcce01c2df5f509bfd7f2d0c15ba1
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179537
Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
Tested-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/5996
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-12 20:16:51 +02:00
Mohammed Habibulla e9b6155e46 google/panther: Configure USB_ILIM_SEL to low
(panther port of Ib980100c648ae7472eac6f97e47f8ef3cbe72c7e)

BUG=none
BRANCH=none
TEST=boot tested on Panther

Change-Id: Iedcc107a43be170762d42d515c7e2a16ec395452
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/177474
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Commit-Queue: Mohammed Habibulla <moch@google.com>
Tested-by: Mohammed Habibulla <moch@google.com>
Reviewed-on: http://review.coreboot.org/5995
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-12 20:16:49 +02:00
Mohammed Habibulla d2259dd3a1 google/panther: Set default interrupt value for Environmental Controller
This writes the default value to the register, but it gets rid of
the error that disturbs some of our tests:

ERROR: PNP: 002e.4 70 irq size: 0x0000000001 not assigned
(panther port of Ieab1c776b553c996a7d06e4059110943aaf41338)

BRANCH=none
BUG=chrome-os-partner:23945
TEST=boot test on Panther

Change-Id: Id45c3bdc0d2feaf6f75d984c41d1f6ffef592d4d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/177468
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Commit-Queue: Mohammed Habibulla <moch@google.com>
Tested-by: Mohammed Habibulla <moch@google.com>
Reviewed-on: http://review.coreboot.org/5994
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-12 20:16:49 +02:00
Mohammed Habibulla 74a4175912 google/panther: Make sure the S5 power status is on track
(panther port of I933c475f693b0271f86b5166eb2c9b3873f1c2c6)

BUG=none
BRANCH=none
TEST=boot test on panther

Change-Id: I5958a8d701901706eaa38df4323120c8352fea5c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/176563
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Commit-Queue: Mohammed Habibulla <moch@chromium.org>
Tested-by: Mohammed Habibulla <moch@chromium.org>
Reviewed-on: http://review.coreboot.org/5993
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-12 20:16:47 +02:00
Mohammed Habibulla fcb5270d54 google/panther: Disable LPSS I2C controllers
There is nothing attached to these devices so we can disable
them as well as the function 0 DMA controller.

Also remove the EC SMI/SCI mappings since there is no EC.
(panther port of Iedfe711058676f7ee118b0b66ab0f8a1e792ea87)

BUG=chrome-os-partner:23563
TEST=none
BRANCH=panther

Change-Id: Ie66f9b66744db98f8638495c05f3a075b6fa6db9
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/174944
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Commit-Queue: Mohammed Habibulla <moch@chromium.org>
Tested-by: Mohammed Habibulla <moch@chromium.org>
Reviewed-on: http://review.coreboot.org/5992
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-12 20:16:46 +02:00
Mohammed Habibulla f0790e4e51 google/panther: Fix thermal zone to use SIO PWM/TACH port 2
Fan is attached to port 2 instead of 3.
(panther port of I9878063a24b0b908c74522580f776a4ce7d03d75)

BUG=chrome-os-partner:23563
TEST=none
BRANCH=panther

Change-Id: I028e0e5a748fa0a20d34e27e870e14ed8c75e4d1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/174984
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Commit-Queue: Mohammed Habibulla <moch@chromium.org>
Tested-by: Mohammed Habibulla <moch@chromium.org>
Reviewed-on: http://review.coreboot.org/5991
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-12 20:16:45 +02:00
Matt DeVillier 0fccebb5d9 google/panther: Use ISO C99 syntax for designated initializers
In C99 we defined a syntax for this. GCC’s old syntax is deprecated.

Modelled after commit 8089f178 (mainboard/lenovo/x230 Fix usage of GNU field
designator extension) [1].

[1] http://review.coreboot.org/5392

Change-Id: I51c72252800be64b9420d845e330fc0481c66470
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: http://review.coreboot.org/6024
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-12 20:16:43 +02:00
Mohammed Habibulla 05497d037e mainboard: Add new board Google Panther
(Panther clone of Ia41af8425ab6c24746253abd025acd3365dd5a18 by reinauer)

BUG=chrome-os-partner:23563
TEST=emerge-panther chromeos-coreboot-panther

[pg: Drop configs/, which is chromeos stuff, adapted
     libpayload's config.panther to work with upstream]

[pm: Add HAVE_IFD_BIN and HAVE_ME_BIN Kconfig options]
[pm: rebase to master branch of coreboot upstream]
[md: don't use FMAP to get MAC address if CONFIG_CHROMEOS not set]

Change-Id: I50fd5c02da154e424dfefbe2020f4ce7ef9a4f8f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/174555
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Mohammed Habibulla <moch@chromium.org>
Tested-by: Mohammed Habibulla <moch@chromium.org>
Reviewed-on: http://review.coreboot.org/5990
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-12 20:16:42 +02:00
Rudolf Marek d13059a5a2 asus/f2a85-m: Switch off automatic fan control for fan2
The fan2 (chasis fan) was set to automatic mode, but the
registers for smart guardian have still default value which
will stop it. Run it in manual mode for now.

Change-Id: Ic2c2414ac88abba77a9e7a129788f9777e7e5ad5
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/6217
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-11 19:04:41 +02:00
Stefan Reinauer 6dbbe2ee96 intel/lynxpoint: Allow to always route USB3 ports to XHCI
This will make USB keyboards connected to USB3 ports work
in libpayload on Beltino.

BUG=chrome-os-partner:23396
BRANCH=none
TEST=Use USB keyboard on Beltino in dev mode screen

Change-Id: I70b03d733bd9e4c8be5673b48bd2196effa8a5e7
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/173640
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
Tested-by: Stefan Reinauer <reinauer@chromium.org>
[pm: rebase to master branch of coreboot upstream]
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/6018
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-11 18:08:04 +02:00
Duncan Laurie 32d2e2b360 intel/lynxpoint: Work around XHCI resume issues
When USB3 devices are attached while in suspend, or two USB3 devices
that are both plugged in are switched to the other port while in
suspend the kernel does not seem to notice this -- despite the cold
attach status bit.  This results in the devices showing up in the USB
list at the old enumerated device numbers and higher layers continuing
to think they are present but not reseponding.

With the kernel workaround to deal with devices that are logically
disconnected it is possible for firmware to send a warm port reset to
devices that are in this state and then the kernel will see them disappear
and handle it properly.

This same issue exists in the EFI firmware on the Whitetip Mountain 2
reference board so it is not specifically a coreboot bug.  If this
behavior is fixed in the kernel then this workaround could be removed
since it is in RW firmware.

BUG=chrome-os-partner:22818
BRANCH=falco,peppy,wolf,leon
TEST=manual:

1) attach two USB3 devices
2) suspend system
3) switch the ports that the USB3 devices are attatched to
4) resume system
5) confirm that the devices are re-enumerated and come up properly

Original-Change-Id: Ifba3ffc94a06dc0b2436d7d7d464d824657362af
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/170335
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 203d200268f4af6445224962190cbc66ad2a83e4)

Change-Id: I54fd2847ee25a60f25c2cefebdc1a3c18455464a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/170579
[pm: rebase to master branch of coreboot upstream]
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/6017
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-11 18:08:03 +02:00
Duncan Laurie 16a0f5c4e3 intel/lynxpoint: xhci: Revert suspend/resume changes
I have been attempting to work around USB3 issues that appear in the
kernel with hacks in the firmware, but this is resulting in more
headaches in the kernel.

Instead remove all the work that was being done at resume time and undo
the change that was issuing a warm reset to all ports at suspend time.

The bad device behavior will be dealt with at the kernel level to
handle devices that get stuck in polling state after enable/disable
sequence.

BUG=chrome-os-partner:22754
BRANCH=falco,peppy,wolf,leon
TEST=manual:

suspend/resume with several misbehaving devices:
Kingston USB3 Media Reader
Transcend USB3 Media Reader
Various ADATA USB3 drives
Various Kingston USB3 sticks

Original-Change-Id: I0894454af42d2ced456fe0da921d74c9e74902d0
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/170107
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit c2abb4d0dad6ed00e1e230d604c4c0a76eb4eef7)

Change-Id: Ib215d9c230f90a1c9f34bf29254bb9feec28c67e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/170578
[pm: rebase to master branch of coreboot upstream]
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/6016
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-11 18:08:02 +02:00
Patrick Georgi 7fc2da9107 kontron/ktqm77: Clean up int15 handler
Worked out the purpose of more int15 calls and let them return
appropriate values. Also remove handlers for copy-pasted calls never
observed on this board.

Change-Id: I3d8c4ec5542bd19baca1dca83badc9b568779e1b
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/6249
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-11 09:23:57 +02:00
Nico Huber 40f9ce93fa kontron/ktqm77: Improve W83627DHG's GPIO config
Fix some outputs of the super i/o that should be GPIOs and make
variables out of magic values that configure LVDS.

Change-Id: Ib9eef065980cefff0046485549a68cf8f070d5b9
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/6248
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-11 09:23:56 +02:00
Nico Huber 2b2f849b53 YABEL: Initialize global `biosmem` pointer for VBE
The global pointer `biosmem` defined in vbe.c was never set. Thus, VBE
calls didn't work within YABEL.

Change-Id: I63c1c77755f9c442cfec227a495332595ce2b70c
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/6250
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-11 09:23:18 +02:00
Edward O'Callaghan f6e1cbec2a southbridge/amd/rsXY0/cmn.c: Trivial - Style fixes
Remove some ASCII art past 80 columns.

Change-Id: I00ad79f2e1ddd78935efcfab19d9e166f0349ae3
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6155
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-11 08:39:39 +02:00
Edward O'Callaghan 7116ac8037 src: Make use of 'CEIL_DIV(a, b)' macro across tree
The objective here is to tighten coreboot up a bit by not repeating
common helpers. This makes the code base more consistent and
unified/tight.

Change-Id: Ia163eae68b4a84a00ed118125e70308fab1cea0c
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6215
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-07-11 08:39:07 +02:00
Rudolf Marek c805e62f9d vendorcode/amd/agesa/f15tn: Fix erratum #712
Implement the fix for the erratum #712. - Processor May Hang During Graphics Memory Controller
Sequencing

The processor may hang during a graphics memory controller (GMC) sleep state transitioning. The failure may
be processor specific and may be sensitive to temperature.

Potential Effect on System:
System hang.

Suggested Workaround:
BIOS should set D18F2x408_dct[1:0] bit 31 = 1b.

See Publication # 48931 Revision: 3.08

Change-Id: I4346fd4ef3cf554ffdaaad5ab6fc84e73532e885
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/6216
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <gaumless@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-11 05:50:23 +02:00
Patrick Georgi 533c119f5b build system: avoid more race conditions
In an abuild run, cbfstool is built in a shared directory
using "make tools". Unfortunately the build system doesn't
actually use that binary directly but creates a per-board
copy (for convenience purposes when editing the image later)
and uses that.

With this change the build system uses the original file but
still creates the copy for the user, avoiding the race while
ensuring convenience.

Change-Id: I38c603a7eca5ef859875ad3031bf7a850189645f
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/6242
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-07-10 20:56:35 +02:00
Nico Huber 5b9e6f175f libpayload: Drop obsolete setting of reg_base in [oex]hci
Setting of `controller->reg_base` is of no use here, as it is never read
(in another function) later. Looks like this pattern originated from uhci.c
where it makes sense.

By removing the indirection through `reg_base` we also fix a possible
truncation to u32.

Change-Id: I5c99c5bf1f5b1d6c04bd84d87fd3e275fd7d0411
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/6251
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-10 20:55:42 +02:00
Nico Huber f4316f8c10 libpayload: Catch null-pointer dereference in xHCI
Fix a possible null-pointer dereference (hopefully) before anyone runs
into this. Also don't switch ports to xHCI if initialization failed.

Change-Id: I5dbaeb435a98ead0b50d27fde13c9f1433ea3e81
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/6245
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-07-10 20:55:41 +02:00
Nico Huber 8b8e96370d libpayload: xHCI: Always initialize controller->pcidev
As the controller structure is never fully cleared, this one wasn't
initialized for non-pci controllers (but checked for non-null later).

Change-Id: I852671c5f55650bdb6cd97f4ec74b1f95ee894c7
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/6246
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-07-10 20:55:41 +02:00
Nico Huber 6e23066d7a libpayload: Use unsigned long for BARs in *hci_init()
Using void* for physical addresses leads to much casting and confuses
developers when to convert from physical to virtual addresses or
the other way around. When using plain integers for physical addresses
and pointers for virtual addresses things become much cleaner and we
won't ever end up dereferencing a physical address.

Change-Id: I24cd53b81c7863b6d14f0cbb4ce8937728b37c1c
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/6244
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-10 20:55:41 +02:00
Nico Huber 322794243a libpayload: Keep physical addresses in console drivers
Like done in FILO, libpayload's console drivers might be initialized
before a relocation. So keep physical pointers in there which won't
break on relocation.

Change-Id: I52e5d9d26801a53fd6a5f3c7ee03f61d6941d736
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/6247
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-07-10 20:55:41 +02:00
Nico Huber 6a058904d9 libpayload: Remove redundant phys_to_virt() from xHCI driver
Remove a redundant phys_to_virt() that sneaked in the initialization of
PCI xHCI controllers. The use of casts from void* to u32 (and vice versa)
prompts for things going wrong here. That will be addressed in a later
commit.

Change-Id: Ibc71ed6ee7016529c0e3a51559aaec07aaaba315
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/6243
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-07-10 20:55:36 +02:00
Edward O'Callaghan fd570665ce include/stdlib.h: Extend common macro collection
Add the following useful macros:

 * Absolute Value Macro
 * Taking ceiling of (a / b)
 * Check if value x is a power of 2 or not

Change-Id: I4e9a326aea3cdd963f13548d1fb63331a57d84b1
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6198
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-10 20:50:16 +02:00
Kyösti Mälkki 4793328fbd AGESA Hudson: Fix build without HAVE_ACPI_RESUME
If one commented out HAVE_ACPI_RESUME in Kconfig file for a board
using agesa/hudson the build failed.

Change-Id: Ifbad8f6e23ce4b5431e596bf67e6ab108fedb4ce
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6253
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Tested-by: build bot (Jenkins)
2014-07-10 20:11:19 +02:00
Dave Frodin 7e5494c549 northbridge/amd: Fix the family15tn option rom mapping
Family15tn video bioses internal have a PCI ID of 1002/9901.
The vendor/device mapping in the family15tn/northbridge.c
file needs to map to 1002/9901 and not to 1002/9900.
This was tested on the amd/parmer mainboard.

Change-Id: I0153e9b522e847099c6054d91bf73b50966ed838
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/6252
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-10 19:29:38 +02:00
Matt DeVillier b2a14fb4f1 intel/haswell: add vmx support w/Kconfig option
patch based on VMX support in intel/fsp_model_206ax and intel/model_6fx
tested/verified working on google/panther

Change-Id: I61232fdc2a29c53aa3bea5ea78b2fdc41fd7396a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: http://review.coreboot.org/6223
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-10 16:46:41 +02:00
Edward O'Callaghan e963b388ba vendorcode/amd/agesa/f14: Trivial - drop whitespaces in .h
Change-Id: Ic63c456e775ad0863ea773abd957d9399e8e2a13
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6191
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-07-10 10:41:09 +02:00
Edward O'Callaghan 1542a6fb8c vendorcode/amd/agesa/f14: Trivial - drop trailing whitespaces
Change-Id: I716253fe8532a4215e5770cd901ee3b3c4963d3d
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6187
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-07-10 10:40:59 +02:00
Edward O'Callaghan 648c9548ba vendorcode/amd/agesa/f12: Trivial - drop whitespaces in .h
Change-Id: Iace2ccfe95bd7f7e5dabbbc69ee4249d80d1cb84
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6190
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-07-10 10:40:52 +02:00