Commit Graph

10867 Commits

Author SHA1 Message Date
Edward O'Callaghan f1323167a9 vendorcode/amd/agesa/f12: Trivial - drop trailing whitespaces
Change-Id: Ieca3358a2a459016b7a38dce7f717100b55baba5
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6186
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-07-10 10:40:42 +02:00
Edward O'Callaghan 692f522962 vendorcode/amd/agesa/f10: Trivial - drop whitespaces in .h
Change-Id: Ie8d74970ef8969cf65b40970cb234399c3db8e56
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6189
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-07-10 10:40:31 +02:00
Edward O'Callaghan 8a6f21602e vendorcode/amd/agesa/f10: Trivial - drop trailing whitespaces
Change-Id: I8f4b2b555d71dd30f134e41ce998c946c4ac0280
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6185
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-07-10 10:40:21 +02:00
Edward O'Callaghan b9a67008b9 vendorcode/amd/cimx: Trivial - drop trailing whitespaces in .h
Change-Id: I3af50553191d7df9255be222eaf941b4232955d9
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6188
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-07-10 10:40:13 +02:00
Edward O'Callaghan ef5981b4aa vendorcode/amd/cimx: Trivial - drop trailing whitespaces in .c
Change-Id: I485f79ece481210f31b0b6d3c62d7269131e29ab
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6184
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-07-10 10:40:06 +02:00
Edward O'Callaghan e1163c1782 mainboard: Trivial - drop trailing blank lines at EOF in .h
Change-Id: I4a4ee99468e5f1dae8412ae565a34290493db726
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6201
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
2014-07-08 13:55:02 +02:00
Edward O'Callaghan 7974471e37 mainboard: Trivial - drop trailing blank lines at EOF
Change-Id: I05d6d22664155ac8478e665733f816776e277c22
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6200
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-07-08 13:54:47 +02:00
Edward O'Callaghan 1f19d34941 vendorcode/google: Trivial - drop trailing blank lines at EOF
Change-Id: Ib8d26d62566e42a78abc282dc9e351774b8e2faf
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6212
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-07-08 13:54:01 +02:00
Edward O'Callaghan 16a8206d52 vendorcode/intel: Trivial - drop trailing blank lines at EOF
Change-Id: Iea9e95981e5e87f2890841e7a0cf45ba93ce84eb
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6211
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-07-08 13:53:50 +02:00
Edward O'Callaghan 234781e074 northbridge: Trivial - drop trailing blank lines at EOF
Change-Id: I9515778e97cc5ae0e366b888da90a651ae5994fe
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6210
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-07-08 13:53:35 +02:00
Edward O'Callaghan 264d265d9c southbridge: Trivial - drop trailing blank lines at EOF
Change-Id: I5484ebb665453777cc3b2561be6e50c787f1a257
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6209
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-07-08 13:53:21 +02:00
Edward O'Callaghan 730e3b02fb soc: Trivial - drop trailing blank lines at EOF
Change-Id: I1829c77f41cc809b590d00ef5522f368bd5fd814
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6208
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-07-08 13:52:54 +02:00
Edward O'Callaghan f7c55148c0 cpu: Trivial - drop trailing blank lines at EOF
Change-Id: I9004f34ba0c13b4489b26ac8c1476d00a6c6d01d
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6207
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-07-08 13:52:43 +02:00
Edward O'Callaghan 7e8d48372b arch: Trivial - drop trailing blank lines at EOF
Change-Id: I472f3b70226ea5236ba6fc231f0f257f0f0eed9d
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6206
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-07-08 13:52:34 +02:00
Edward O'Callaghan 6beb1fe325 lib: Trivial - drop trailing blank lines at EOF
Change-Id: I69a4a2ffb41eeae04529e527d68edc652f3638a5
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6205
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-07-08 13:52:15 +02:00
Edward O'Callaghan 64ea6dbe2e device: Trivial - drop trailing blank lines at EOF
Change-Id: I50a5177a8bad5dada862f30c5c9421f08b0e1686
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6204
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-07-08 13:52:03 +02:00
Edward O'Callaghan 1bd01663f5 drivers: Trivial - drop trailing blank lines at EOF
Change-Id: Ie80c87c614a536cc6b0bdbf196c280b64547d3b7
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6203
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-07-08 13:51:47 +02:00
Edward O'Callaghan f35353af55 superio: Trivial - drop trailing blank lines at EOF
Change-Id: I8633d331d095fe9506a8f01969060ba9889c8eac
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6202
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-07-08 13:39:24 +02:00
Patrick Georgi c2bc6fdc5b build system: prevent race on more tool binaries
ifdfake is the newest tool addition that leads to build time
races on highly parallel builds.

Change-Id: I86289e50079da851dcc8e1c05c2536d5c03de87c
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/6197
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-08 08:41:03 +02:00
Edward O'Callaghan 96c801bfe9 mainboard/hp/dl145_g3/get_bus_conf.c: Use ARRAY_SIZE macro
Change-Id: Ie3287cba45bd6f4f8823ce03cd9983707c9ad0de
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6194
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
2014-07-08 07:55:47 +02:00
Edward O'Callaghan 4b7910635d mainboard: Make use of ARRAY_SIZE macro in hda_verb.h
We have the macro, let us be sure to make use of it.

Change-Id: I8dc5ca580c7485e3cce7ebc29189a452de52b1b1
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6193
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-08 07:55:29 +02:00
Patrick Georgi 577573fd5e YABEL: Drop IO stubs that are (by own admission) never used
Change-Id: I90a120e64a5062493f64e3e8b48a75dae9342ec4
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/6178
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-05 21:16:13 +02:00
Paul Menzel 501093d4fe Intel Lynx Point boards: Kconfig: Add `HAVE_ME_BIN`
Change-Id: Ib7d2a5c14675427fe9556a6b81ed5397f17937d8
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/6049
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-05 16:53:19 +02:00
Paul Menzel cc53d51225 Intel Lynx Point boards: Kconfig: Add `HAVE_IFD_BIN`
Change-Id: I0ea09d75cb05687407fb152642578e19824d1c4c
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/6048
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-05 16:53:17 +02:00
Kyösti Mälkki 32d2298828 amd/dinar: Fix agesawrapper header
Change-Id: I246cfb38aa47e67d62bcfcc37539e9593b8026ce
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6179
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-07-05 12:39:31 +02:00
Kyösti Mälkki 36abdc4017 gizmosphere/gizmo: Move support of SPD data in CBFS
This code is not specific to any board or AGESA family.

Change-Id: I26c32fbe8e45018e239762b072dfe3da05271697
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5690
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-07-05 11:41:52 +02:00
Gabe Black 93d9f92cfb spi: Change spi_xfer to work in units of bytes instead of bits.
Whenever spi_xfer is called and whenver it's implemented, the natural unit for
the amount of data being transfered is bytes. The API expected things to be
expressed in bits, however, which led to a lot of multiplying and dividing by
eight, and checkes to make sure things were multiples of eight. All of that
can now be removed.

BUG=None
TEST=Built and booted on link, falco, peach_pit and nyan and looked for SPI
errors in the firmware log. Built for rambi.
BRANCH=None

Change-Id: I02365bdb6960a35def7be7a0cd1aa0a2cc09392f
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/192049
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
[km: cherry-pick from chromium]
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6175
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-05 11:36:20 +02:00
Gabe Black 1e187356e8 spi: Remove unused parameters from spi_flash_probe and setup_spi_slave.
The spi_flash_probe and and spi_setup_slave functions each took a max_hz
parameter and a spi_mode parameter which were never used.

BUG=None
TEST=Built for link, falco, rambi, nyan.
BRANCH=None

Change-Id: I3a2e0a9ab530bcc0f722f81f00e8c7bd1f6d2a22
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/192046
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
[km: cherry-pick from chromium]
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6174
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-05 11:36:11 +02:00
Kyösti Mälkki ab60510818 spi flash: Organise options list
Change-Id: I21e4e2384d9b8bbd34f652e99af11dee993fb41c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6173
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-05 11:35:53 +02:00
Kyösti Mälkki c06af9eb8b Drop redundant select CACHE_AS_RAM
The few remaining boards without CAR override this with
select ROMCC.

Change-Id: Ifd5223e67f6a2dadb47846bdaab40b1be763cf69
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6172
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-05 11:33:23 +02:00
Paul Menzel 8aeab56b10 lenovo/x60/i915.c: Use define for `BSM`
Although it builds without any further changes, including the header

	src/northbridge/intel/i945/i945.h

where `BSM` is defined, would be useful. Unfortunately that conflicts
with the already included header `southbridge/intel/bd82x6x/pch.h`,
so it is left as is.

Change-Id: I7c0a795338c34038169e082446907987364a0e88
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/5932
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-07-05 10:39:22 +02:00
Duncan Laurie 9238c11be4 intel/lynxpoint: Build intermediate step to add Lynx Point ME image
This is needed to successfully build fox_wtm2 from external repo.

BUG=chrome-os-partner:18638
BRANCH=none
TEST=manual: successfully compile coreboot for fox_wtm2 and
create an image with chromeos-bootimage/cros_bundle_firmware

Change-Id: Iaa4e9983faa1d86c2b29d8fd4f577be035497e38
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/48676
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4132
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-05 10:36:48 +02:00
Duncan Laurie 88c873a07e intel/lynxpoint: xhci: Port reset changes on suspend/resume
Some USB3 devices are not showing up after suspend/resume cycles.
In particular if a device uses a lower power state like U2 it may
take longer to come up and the firmware needs to wait after sending
a warm port reset.

In addition skipping port reset to connected ports in the way into
suspend was causing problems so instead send all ports a reset
before suspend.

BUG=chrome-os-partner:22402
BRANCH=falco,peppy,leon,wolf
TEST=manual:

Suspend/resume with ADATA HE720 HDD (and other devices) both
connected at suspend and connecting while in suspend and ensure
that the devices always show up in the kernel.

Change-Id: Ib7b15dc65792742b4ceb7dcfc4b2c83192eafcc2
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/169548
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/6015
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-05 10:12:07 +02:00
Stefan Reinauer 779e178353 intel/lynxpoint: Export pch_enable_lpc() for Super I/O systems
In order to enable a Super I/O in non Chrome EC systems we
need to make pch_enable_lpc() available to the mainboard
romstage.c

BUG=none
BRANCH=none
TEST=boot ChromeOS on Beltino

Change-Id: I34e7d23012e1852c69e82ba7cdc81a05751846de
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/172180
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: http://review.coreboot.org/6019
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-05 10:12:05 +02:00
Dave Frodin c50c0ab456 drivers/spi: Reduce the per loop delay of spi_flash_cmd_poll_bit()
At the end of some SPI operations the SPI device needs to be polled
to determine if it is done with the operation. For SPI data writes
the predicted time of that operation could be less than 10us.
The current per loop delay of 500us is adding too much delay.
This change replaces the delay(x) in the do-while loop with a
timer so that the actual timeout value won't be lengthened by the
delay of reading the SPI device.

Change-Id: Ia8b00879135f926c402bbd9d08953c77a2dcc84e
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/5973
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-07-05 00:38:46 +02:00
Edward O'Callaghan ba92428514 intel: Make monotonic timer a first class citizen
The monotonic time now needs to be a first class citizen in Coreboot as
it is a hard dependency of the drivers/spi flash command polling
function.

Change-Id: I4e43d2680bf84bc525138f71c2b813b0f6be5265
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6135
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-07-05 00:38:06 +02:00
Vladimir Berezniker bda9a82114 Documentation: Use correct file name for the build guide in the Makefile
Change-Id: I19c456e8bcd2de19c5f9d963ea17dad84d300ab8
Signed-off-by: Vladimir Berezniker <vmpn@vmpn.net>
Reviewed-on: http://review.coreboot.org/6170
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <gaumless@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-04 19:03:10 +02:00
Marc Jones e05cba2c72 intel/lynxpoint: Add SATA DEVSLP disable option
Add the chip option to disable SATA DEVSLP. This disables
the SDS bit in the SATA CAP2 register.

BUG=chrome-os-partner:23186
BRANCH=leon
TEST=Manual: System runs without SATA failure for more than 10 hours

Original-Change-Id: I8baa40935421769aeee341a78441fb19ecaa3206
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: https://chromium-review.googlesource.com/174648
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
(cherry picked from commit 49d25812b04a983d687a53a39530559ba99fd9b4)

Change-Id: Iac0b32f80958f5ffb571733484dc931bee216f55
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: https://chromium-review.googlesource.com/176352
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/6013
Tested-by: build bot (Jenkins)
2014-07-04 17:50:24 +02:00
Duncan Laurie 5a45b04ac0 intel/lynxpoint: Add CONFIG_LOCK_MANAGEMENT_ENGINE entry to Kconfig
This was missing from lynxpoint.

BUG=chrome-os-partner:21796
BRANCH=falco,peppy
TEST=emerge-falco chromeos-coreboot-falco

Change-Id: Id1b261a5310ce1482f11c8c032c13f49046742fc
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/66669
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/6012
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-04 17:50:22 +02:00
Duncan Laurie 78145a56b4 intel/lynxpoint: Use separate SMI callback for USB XHCI routing
This will allow the legacy mode boot path to leave USB
ports routed to EHCI so they can be used by SeaBIOS.

BUG=chrome-os-partner:22085
BRANCH=falco,peppy
TEST=manual: Build and boot from USB and SeaBIOS on falco

Change-Id: I46870eccd1b846dc8a7f8d7948969c8e623e18cd
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/66547
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/6011
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-04 17:50:20 +02:00
Stefan Reinauer 7034b9ef77 intel/haswell: Allow overriding PRE_GRAPHICS_DELAY in config
Without a prompt the config option will always stay 0
due to the way Kconfig works.

BUG=chrome-os-partner:25387
BRANCH=panther
TEST=Boot into dev mode with Mohammed's TV screen, see
     the dev mode screen appear.

Change-Id: Ib7d9ec82b4a4a29daddc29aa7702fc420279017d
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/185970
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
Tested-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: http://review.coreboot.org/6010
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-04 17:50:15 +02:00
Stefan Reinauer f1aabecaac intel/haswell: Allow pre-graphics delay
Some slow monitors/TVs can't wake up quickly enough for coreboot,
so when the VBIOS is run it won't detect them. Hence, add an option
to wait for a while before running the VBIOS.

BUG=none
BRANCH=panther
TEST=Boot to dev mode on one of the systems that exposed the problem
     and see it go away.

Change-Id: Ib9524f1c7ee08bedf96a6468da8b4ccf712fe0e2
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/183545
Reviewed-by: Mohammed Habibulla <moch@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/6009
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-04 17:50:13 +02:00
Paul Menzel 0089c2418b intel/lynxpoint: Make inclusion of Intel ME optional
Current build configuration always wants to include an Intel Management Engine
(ME) firmware (`me.bin`) on Intel Lynx Point systems.  However, we can have a
working coreboot without it, as long as the factory delivered ME firmware is
kept untouched in the flash ROM. So let the user decide if a ME firmware will
be included in the build by introducing the Kconfig option `HAVE_ME_BIN`.

The same was done in commit 99fd30e4 (sandybridge: Make inclusion of me.bin
optional) [1] for Intel Sandy Bridge (BD82x6x).

[1] http://review.coreboot.org/3522

Change-Id: I7c6048fd0f56288769ad90acbfb67b908ac8d824
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/6047
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-04 17:48:41 +02:00
Paul Menzel 5218e61651 intel/lynxpoint: Allow building without IFD (descripter.bin)
On newer Intel systems, like Intel Lynx Point, the flash ROM is shared
between the host processor (BIOS), its Management Engine (ME) and an
integrated Ethernet controller (GbE). The layout of the flash ROM (and
other information) is kept in the so called Intel Firmware Descriptor
(IFD).  If we only want to build coreboot to update the BIOS section,
all we need is the flash layout.

So add the option to specify the flash layout in the mainboard’s
Kconfig, and thus, to build without the real IFD. However, with such a
build, one has to make sure that the IFD section on the flash ROM will
not be written over (nor any other section that has not been included
by coreboot). A patch to write selected sections of a flash ROM with
IFD has been sent to the flashrom mailing list [2].

The same was done in commit a15cd66b [1] (sandybridge: Make build
possible without descriptor.bin) for Intel Sandy Bridge (BD82x6x).

[1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html
    [PATCH] Add option to read ROM layout from IFD
[2] http://review.coreboot.org/3524

Change-Id: I26a604446cdf37a6bbcee2b14a107b7ccf417d5c
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/6046
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-04 17:48:40 +02:00
Kyösti Mälkki 6a089e3b18 AGESA boards: Use acpi_is_wakeup_s3()
Change-Id: Ib76ec433710b3a7c26360329a9403585d6f4fe4c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6143
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-03 09:50:41 +02:00
Kyösti Mälkki db8693bde7 ACPI: Recover type of wakeup in acpi_is_wakeup()
Update acpi_slp_type early in ramstage.

Change-Id: I30ec2680d28b880171217e896f48606f8691b099
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6142
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-03 09:49:26 +02:00
Kyösti Mälkki ef40ca57eb AGESA: Call get_bus_conf() just once
Instead of calling get_bus_conf() three times from write_tables()
and executing it once, just make one call before entering write_tables().

Change-Id: I818e37128cb0fb5eaded3c1e00b6b146c1267647
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6133
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-03 09:48:57 +02:00
Kyösti Mälkki 005028e0a9 AGESA: Add agesawrapper_post_device()
NOTE: The procedure is moved across a collected timestamp
TS_WRITE_TABLES, so the delay of SPI erase/write will be accounted
for in an earlier entry in cbmem -t output.

Change-Id: I0f082e7af1769c8d7d03cdd51fdb5dacbf3402b4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6132
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-03 09:47:48 +02:00
Kyösti Mälkki e1b468e1a7 AGESA boards: Use acpi_s3_resume_allowed()
This adds use of BROKEN_CAR_MIGRATE to include CBMEM symbols for the
build of romstage also for boards without HAVE_ACPI_RESUME.
These symbols got exposed as the use of preprocessor directives was
reduced.

We expect the linker to do a fair job and optimize away function
bodies that are on unreachable execution paths.

Change-Id: Ibf5181d3eecb87ce647abe0be01072594b05aa5f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6067
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-03 09:46:50 +02:00
Kyösti Mälkki adf3d6ff52 AGESA: Clean separation of SPI flash
To be precise, wakeup from S3 does not involve SPI writing, while
preparing for it on cold power-ons currently does.

For S3DataTypeMtrr storage is changed such that the first 4 bytes
is the length of data stored like with the other two S3DataType.

Change-Id: Id920650474530d4191075da4ef70daa66c904c5b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6085
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2014-07-03 09:46:15 +02:00