Commit Graph

35911 Commits

Author SHA1 Message Date
Furquan Shaikh a469736cca mb/google/zork: Enable ACP_PME_EN and ACP_I2S_WAKE_EN
This change enables ACP_PME_EN and ACP_I2S_WAKE_EN for dalboz and trembyle
boards using devicetree settings.

BUG=b:161328042,b:146317284

Change-Id: Ie367a9ba878a1892177df874bbcb8005efeb0880
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43496
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-17 05:03:00 +00:00
Akshu Agrawal 42d4a57b77 soc/amd/picasso: Configure ACP_PME_EN and ACP_I2S_WAKE_EN
This change adds support for configuring ACP_PME_EN and ACP_I2S_WAKE_EN
using the mainboard setting for `acp_pme_enable` and `acp_i2s_wake_enable`
in the devicetree. This is required to get I2S_Wake event on headset jack
plug/unplug when using CODEC_GPI pad.

BUG=b:146317284,b:161328042

Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
Change-Id: I522d7497940f499fbc3181d866f2b44e979bba7a
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/1969104
Reviewed-by: Raul E Rangel <rrangel@chromium.org>
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43495
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-17 05:02:50 +00:00
Felix Held 34aab089e3 soc/amd/picasso: remove unused fadt_pm_profile devicetree setting
commit 56da63c3dc removed overriding that
field in the FADT.

Change-Id: I0c8ff9ab125129dc856949c47a3a0c14e4109c73
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43417
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-16 23:58:30 +00:00
Felix Held 12732536df mb/amd/mandolin: add SATA DXIO descriptor for Dali SKUs
Dali supports two SATA ports, but no PCIe alternate function on those
pins.

Change-Id: I27a13100e80565eb1dade2d703ba3d1f8b5f630f
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43493
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-16 23:39:06 +00:00
Felix Held 4794264ff1 mb/amd/mandolin: fix DXIO lane numbers
The DXIO descriptors use the logical and not the physical lane numbers,
which are different.

Change-Id: I7a90056d782d8d32fe34a0f5bdb61c3b61df1af8
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43492
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-16 23:38:44 +00:00
Martin Roth b39e10dbaa soc/amd/common: Don't get eSPI address from PCI if not on x86
Exclude lpc_get_spibase() on the PSP.  This also simplifies the
espi_get_bar() function.

BUG=b:159811539
TEST=Build & boot trembyle; Verify address in PSP & x86

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I5927dd40610860b54bb35a7e5b03ddb731597745
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43468
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-16 22:20:53 +00:00
Martin Roth 37d1206c6e soc/amd/picasso: Get rid of VERSTAGE_SIZE
Currently, the code and data in psp_verstage is ~59K.  Adding the code
to save vbnv to the SPI rom increases that to 66K.

Getting rid of VERSTAGE_SIZE allows verstage to grow as it needs to.

BUG=b:161366241
TEST=Build & Boot Morphius with VBOOT_VBNV_CMOS_BACKUP_TO_FLASH enabled

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Ic6853b70073f9e781fc10402a2a47c9c8e0d49d3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43486
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-16 22:20:27 +00:00
Martin Roth 6812626382 soc/amd/stoneyridge: Remove unused SPI #defines
These #defines are not used, and conflict with #defines in
amdblocks/spi.h

BUG=None
TEST=Build stoney platforms

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I29b77a6b21a4deda6f28f5b057988cf3921540e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43485
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-07-16 17:38:57 +00:00
Raul E Rangel 79ab7d7780 soc/amd/picasso/acpi,mb/{zork,mandolin}: Stop clearing PciExpWakeStatus
The kernel already clears this: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/master:src/third_party/kernel/v5.4/drivers/acpi/acpica/hwregs.c;l=390
No reason to have the firmware do it as well.

BUG=b:153001807, b:154756391
TEST=Build Trembyle, boot, suspend, and resume and didn't see any ACPI
errors.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ia5c79fb95dc885eaef8abc4257b6ba18c1ef1b66
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43428
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-16 17:20:04 +00:00
Raul E Rangel d458358379 soc/amd/picasso,mb/{zork,mandolin}: Remove invalid UPWS variable
PMx0EE is not defined in the Picasso PPR.

BUG=b:153001807, b:154756391
TEST=None

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I98caf0cd2d0bdcf19de2b945dcf74f5cf7354769
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-16 17:11:29 +00:00
Raul E Rangel b20a16ef4e mb/amd/mandolin/.../sleep.asl: Remove unnecessary variable
There is no reason to create a named variable. We can just return the
package.

BUG=b:153001807, b:154756391
TEST=None

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ic0ca2e6d4fb833c68d29e9948a670ace7c89b6a5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43464
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-16 17:10:34 +00:00
Ronald G Minnich a92a07d9c0 libpayload: allow nonblocking delay and more than one delay
Extend the local APIC timer delay so that it can be started,
and waited for, independently.

Add an EOI so that more than one APIC timer interrupt is possible.
Previous to this, because there was no EOI, the first timer
interrupt the CPU took was also the last it would take --
apic_delay would only work one time.

Change-Id: Ib11aeee5b7da81287166ac68fc327e7ae62d1b84
Signed-off-by: Ronald G Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43323
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-07-16 16:48:42 +00:00
Furquan Shaikh bf6541d876 soc/amd/picasso: Drop mainboard_romstage_entry_s3
mainboard_romstage_entry_s3() was dropped from zork (CB:43476). This
function call in picasso does not do anything and hence is being dropped.

BUG=b:154351731

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I10e15422d7eef5af9c19737c32e433718b6479d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43477
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-16 16:45:57 +00:00
Furquan Shaikh bf9eb00c11 mb/google/zork: Move variant_pcie_gpio_configure() to bootblock
On zork, bootblock is part of RW firmware in non-recovery mode, so PCIe
GPIOs can be configured early on in bootblock rather than waiting until
romstage. This change moves the call to variant_pcie_gpio_configure() to
happen in bootblock and drops romstage.c file.

BUG=b:154351731

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ic515304f35fe5623d58d6000efcb11fb9039e137
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43476
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-16 16:45:48 +00:00
Furquan Shaikh 56f949cd0c mb/google/zork: Drop variant_romstage_gpio_table()
gpio_set_stage_rom table is now configuring only PCIe related GPIOs in
romstage. This change moves the configuration of PCIe related GPIOs to
variant_pcie_gpio_configure() to keep all the configuration for WiFi and
non-WiFi PCIe pads in one place. It also drops the function
variant_romstage_gpio_table() as it is unused.

BUG=b:154351731

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ib1c41ba141dce6b52b6e0a250a3aa07c296068aa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43475
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-16 16:45:27 +00:00
Furquan Shaikh 6a5c77cc84 mb/google/zork: Drop redundant romstage GPIO table
Now that the power and reset GPIO configuration for non-PCIe devices is
dropped from romstage GPIO table, the tables for pre-v3 and v3 version of
schematics are exactly same. So, this change drops the duplicate table and
also removes the check for v3 schematics when configuring the pads in
romstage.

BUG=b:154351731

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I67ca9f587c3f47912393ebaf38badcc9d76cc393
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43474
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-16 16:39:25 +00:00
Furquan Shaikh ddfec569d1 mb/google/zork: Drop power and reset control in romstage for dalboz
This change drops power and reset control for non PCIe devices in
romstage for dalboz reference as this is not required.

 +---------------------------------------------------------------------------------------+
 | GPIO|    Net name   | External| Internal| Domain| State at reset | State on S3 resume |
 |  #  |               | Pull    | Pull    |       |                |                    |
 +---------------------------------------------------------------------------------------+
 |  5  | PEN_POWER_EN  | 100K PD |   PD    | S5    | Powered off    | Powered on         |
 |     |               |         |         |       | (because of    | (since power is not|
 |     |               |         |         |       |  internal PD)  |  disabled when     |
 |     |               |         |         |       |                |  entering S3)      |
 +---------------------------------------------------------------------------------------+
 |  6  |EN_PWR_TOUCHPAD| 499K PD |   PU    | S5    | Powered on     | Powered on         |
 |     |               |         |         |       | (because of    | (since trackpad    |
 |     |               |         |         |       |  internal PU)  |  is wake source)   |
 +---------------------------------------------------------------------------------------+
 | 68  | EMMC_RESET_L  | 100K PU |   PD    | S0    |  Asserted      | Asserted           |
 |     |               |         |         |       |  (because of   | (because of        |
 |     |               |         |         |       |   internal PD) |  internal PD)      |
 +---------------------------------------------------------------------------------------+
 | 76  | EN_PWR_CAMERA | 499K PD |   PD    | S0    | Powered off    | Powered off        |
 |     |               |         |         |       | (because of    | (because of        |
 |     |               |         |         |       |  internal PD)  |  internal PD)      |
 +---------------------------------------------------------------------------------------+
 | 140 | USI_RESET     | 10K PD  |   PD    | S0    | Deasserted     | Deasserted         |
 |     |               |         |         |       | (because of    | (because of        |
 |     |               |         |         |       |  internal PD)  |  internal PD)      |
 +---------------------------------------------------------------------------------------+
 | 141 | USB_HUB_RST_L | 10K PU  |   PD    | S0    | Asserted       | Asserted           |
 |     |               |         |         |       | (because of    | (because of        |
 |     |               |         |         |       | internal PD)   |  internal PD)      |
 +---------------------------------------------------------------------------------------+
 +---------------------------------------------------------------------------------------+
 | 67  |EN_PWR_TOUCHPAD| 10K PU  |   PD    | S0    | Powered off    | Powered off        |
 |     |_PS2 (pre-V3)  |         |         |       | (because of    | (because of        |
 |     |               |         |         |       |  internal PD)  |  internal PD)      |
 +---------------------------------------------------------------------------------------+

GPIO_140 starts deasserted out of reset and S3 resume, but gets
asserted in ramstage since it is eventually deasserted by OS using
ACPI methods.

BUG=b:154351731

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ie792a5a9d6420763ff10d1e475c094b6ee514888
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43463
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-16 16:39:16 +00:00
Furquan Shaikh 9961343e67 mb/google/zork: Drop power and reset control in romstage for trembyle
This change drops power and reset control for non PCIe devices in
romstage as this is not required.

+---------------------+--------------------------------------------+--------------------+
| GPIO|    Net name   | External| Internal| Domain| State at reset | State on S3 resume |
|  #  |               | Pull    | Pull    |       |                |                    |
+---------------------------------------------------------------------------------------+
|  5  | PEN_POWER_EN  | 100K PD |   PD    | S5    | Powered off    | Powered on         |
|     |               |         |         |       | (because of    | (since power is not|
|     |               |         |         |       |  internal PD)  |  disabled when     |
|     |               |         |         |       |                |  entering S3)      |
+---------------------------------------------------------------------------------------+
| 13  |EN_PWR_TOUCHPAD| 499K PD |   PU    | S5    | Powered on     | Powered on         |
|     |_PS2           |         |         |       | (because of    | (since trackpad    |
|     |               |         |         |       |  internal PU)  |  is wake source)   |
+---------------------------------------------------------------------------------------+
| 68  | EMMC_RESET_L  | 100K PU |   PD    | S0    |  Asserted      | Asserted           |
|     |               |         |         |       |  (because of   | (because of        |
|     |               |         |         |       |   internal PD) |  internal PD)      |
+---------------------------------------------------------------------------------------+
| 76  | EN_PWR_CAMERA | 499K PD |   PD    | S0    | Powered off    | Powered off        |
|     |               |         |         |       | (because of    | (because of        |
|     |               |         |         |       |  internal PD)  |  internal PD)      |
+---------------------------------------------------------------------------------------+
| 140 | USI_RESET     | 10K PD  |   PD    | S0    | Deasserted     | Deasserted         |
|     |               |         |         |       | (because of    | (because of        |
|     |               |         |         |       |  internal PD)  |  internal PD)      |
+---------------------------------------------------------------------------------------+
+---------------------------------------------------------------------------------------+
| 67  |EN_PWR_TOUCHPAD| 10K PU  |   PD    | S0    | Powered off    | Powered off        |
|     |_PS2 (pre-V3)  |         |         |       | (because of    | (because of        |
|     |               |         |         |       |  internal PD)  |  internal PD)      |
|     |               |         |         |       |                |                    |
+-----+---------------+---------+---------+-------+----------------+--------------------+

GPIO_140 starts deasserted out of reset and S3 resume, but gets
asserted in ramstage since it is eventually deasserted by OS using
ACPI methods.

BUG=b:154351731

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ieadc62f1a13857209cf0a62f204efb9278e0e97d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43462
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-16 16:39:09 +00:00
Furquan Shaikh eb912ed9ad mb/google/zork: Keep USI_RST asserted in ramstage
This change keeps USI_RST(GPIO_140) asserted in ramstage since it gets
deasserted by OS using ACPI methods.

BUG=b:160854397

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I8feced788e471a0efb2358d42b2146df04fb7a0c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43461
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-16 16:38:55 +00:00
Furquan Shaikh 19a2a2db7e mb/google/zork: Keep pen power enabled in sleep state
This change keeps pen power enabled in sleep state to allow it to
charge in S3.

BUG=b:155422911

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I6190496653878327f34a01f6a743db474d32e929
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43452
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-16 16:37:06 +00:00
Philipp Deppenwiese 96dc015519 Revert "mb/ocp/deltalake: Select IPMI OCP to send POST start/end command"
This reverts commit a5ca4a0c75.

Reason for revert: Breaks coreboot tree because of non existent kconfig symbol

Change-Id: Ib8f55dc2f6444690945bc2dc64baad5d0c39cdf4
Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-16 16:32:46 +00:00
Tim Chu adb6922a6d soc/intel/common/block/pmc: Select PMC on mainboard basis
Currently the common soc code automatically selects
POWER_STATE_DEFAULT_ON_AFTER_FAILURE which making other mainboard
options unselectable.

However, there're some cases that power state should change to different
states after reapplying power.

Make POWER_STATE_DEFAULT_ON_AFTER_FAILURE default y but do not select it
in soc code so that we can disable it and select other options in the
mainboard code.

Tested on OCP Delta Lake.

Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: Ifa853d81ee9477d2440ceaa67b2bd6b863ee52c2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43338
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-16 13:08:06 +00:00
TimChu a5ca4a0c75 mb/ocp/deltalake: Select IPMI OCP to send POST start/end command
Implement sending POST start/end command to BMC.

TEST=Read POST command log in OpenBMC,
if command received successfully, message may show as below,

root@bmc-oob:~# cat /var/log/messages |grep -i "POST"
 2020 May 28 13:21:22 bmc-oob. user.info fby3-v2020.20.2:
ipmid: POST Start Event for Payload#1
 2020 May 28 13:21:25 bmc-oob. user.info fby3-v2020.20.2:
ipmid: POST End Event for Payload#1
root@bmc-oob:~#

Signed-off-by: TimChu <Tim.Chu@quantatw.com>
Change-Id: I38b512ee97c0eda6ba54482a448ef9ffc27b4ddb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41993
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-16 13:07:58 +00:00
Morgan Jang b29d16fc8a mb/ocp/deltalake: Config PCH PCIe ports in devicetree
Tested on OCP Delta Lake with lspci checking if PCIe speed is changed
are expected.

Change-Id: I189027c403814d68db2b7c5f41fc254a293fe3a1
Signed-off-by: Morgan Jang <Morgan_Jang@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41690
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
2020-07-16 13:07:31 +00:00
Patrick Georgi b8d0d089b3 Documentation: Remove mention of manual checkpatch.pl invocation
We typically call checkpatch.pl through make lint which properly adds
the option to tell checkpatch that our lines may be 96 columns long.

However there's one mention of calling checkpatch directly and that
confuses people with complaints about overly long lines that exceed
80 columns.

The lint test that runs checkpatch (and with the right options)
can also be used on a per-directory basis, so offer that instead.

Change-Id: If21e925d2d2394c876724a44b0e23c9b2744c56b
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43450
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-07-16 10:48:18 +00:00
Sheng-Liang Pan 14eca573d1 mb/google/kukui: Add new config 'willow'
New board introduced to Kukui family.

BUG=b:159194582
TEST=None
BRANCH=kukui

Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: Icc6bcbd006008a05303693e481a54636f0645887
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43318
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-16 05:47:59 +00:00
Julius Werner aa4c1d2b5b google/trogdor: Remove GPIO_AP_SUSPEND_L
This pin has been removed from recent revisions (or at least moved to a
pin that's not controlled like a normal GPIO). It has also never been
used on older ones (I think?). The same GPIO is now used as a SKU ID
pin, so make sure we're not incorrectly configuring it as an output
(although sku_id() overrides that later anyway, but it's still
incorrect).

BUG=b:160754995

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I6e0d56e230d0bef172d7b78cc48263e9b6f059de
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43471
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Philip Chen <philipchen@google.com>
Reviewed-by: Bob Moragues <moragues@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-16 00:58:24 +00:00
Rob Barnes 9754f38e82 mb/google/zork: Remove redundant PCI info from overridetrees
This information is redundant since it's already specified in
baseboard/devicetree_trembyle.cb or baseboard/devicetree_dalboz.cb

domain 0 is still required because sconfig uses it as an identity anchor
to match devicetree and overridetree.

BUG=b:157580724
TEST=Boot zork, usb functional

Change-Id: I3c3c1c2410166b99599d7343fae3ee756f4da321
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43437
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-16 00:16:40 +00:00
Paul Fagerburg 31b7d95350 util/mb/google: add template files for dalboz and trembyle
Now that Zork is using upstream coreboot, we need the template files
in the main branch.

BUG=b:157570490
TEST=n/a

Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Change-Id: I6cab4ab0b414473e0a759dce81df9872a40d3f26
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43419
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-15 20:45:03 +00:00
Shelley Chen 31a3788739 cbgfx: Add blend functions to calculate transparency
Up until now we have no way of adding transparency into our firmware
screens.  Add set_blend() and clear_blend() functions to store alpha
value and rgb values to calculate alpha blending in
calculate_colors().

BUG=b:144969091,b:160839199
BRANCH=puff
TEST=dut-control power_state:rec
     press ctrl-d
     Ensure background is dimmed when dialog pops up

Change-Id: I95468f27836d34ab80392727d726a69c09dc168e
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43358
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-07-15 20:23:07 +00:00
Paul Menzel df5571dc9d util/board-status: Reject logs with unknown timestamps
Check the output of `cbmem -t` for unknown timestamps. If present, ask
the user to rebuild `cbmem`.

Change-Id: Ief7aa1a698f10d9721964ad1bee057fcd9f4aa40
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41857
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-07-15 12:31:46 +00:00
Michael Niewöhner 91323593f3 payloads/depthcharge: Makefile: resolve fail of concurrent build
Resolve missing dependency to fix concurrent building.

Resolves: https://ticket.coreboot.org/issues/271
Change-Id: Idbd9155e01fcc4571a61f1bba5b2b4a446036da0
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43407
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-07-15 10:33:13 +00:00
Karthikeyan Ramasubramanian e0407a8e44 mb/google/dedede: Enable SIS touchscreen for Waddledee
Add SiS9813 USI touchscreen support.

BUG=b:160129126
TEST="emerge-dedede coreboot chromeos-bootimage", build successful.

Change-Id: I42fdc5e8243d2c70c953b2f516c10f84a041c035
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43304
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-15 08:42:25 +00:00
Jett Rink 3f5de1c8f4 security/vboot: ensure that NVMEM is saved on every kernel space write
If the AP actually needs to write to the TPM, then it is important and
the TPM should commit those changes to NVMEM immediately in case there
is an unexpected power loss (e.g. from a USB-C port partner reset upon
cold reboot request).

BRANCH=none
BUG=b:160913048
TEST=Verify that puff will no longer reboot loop when coreboot writes a
new Hmir (Hash mirror) in the TPM

Change-Id: I9597a55891d11bdf040d70f38b4c5a59c7888b8a
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43414
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-15 08:42:11 +00:00
Shaunak Saha 60e6f6e1e5 mb/google/volteer: Enable SATA Port Dito Config
Enable SataPortsEnableDitoConfig for port 1.

BUG=b:151163106
BRANCH=None
TEST=Build and boot volteer.

Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Change-Id: I552faaa0e7172e77208025cf4251bb848cc90709
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42415
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-15 08:40:37 +00:00
Shaunak Saha 1a8949c0c4 soc/intel/tigerlake: Hook up SATA Port Enable DITO UPDs
SataPortsEnableDitoConfig Enable DEVSLP Idle Timeout settings DmVal and
DitoVal. SataPortsDmVal and SataPortsDitoVal helps to determine when to
enter Device Sleep. Device Sleep enables the host bus adapter (HBA) to
assert the DEVSLP signal as soon as there are no commands outstanding
to the device and the port specific Device Sleep idle timer has expired.
Device Sleep Idle Timeout values (PxDEVSLP.DITO and PxDEVSLP.DM) are
port specific timeout values used by the HBA for determining when to
assert the DEVSLP signal. They provides a mechanism for the HBA to apply
a programmable amount of hysteresis so as to prevent the HBA from
asserting the DEVSLP signal too quickly which may result in undesirable
latencies. This patch is created based on Intel Tiger Lake Processor
PCH Datasheet with Document number:575857 and Chapter number:12.

* PxDEVSLP.DM ->     SataPortsDmVal: Enable SATA Port DmVal DITO multiplier.
 Default is 15.
* PxDEVSLP.DITO -> SataPortsDitoVal: Enable SATA Port DmVal DEVSLP Idle Timeout
 (DITO), Default is 625ms.

BUG=b:151163106
BRANCH=None
TEST=Build and boot volteer and TGL RVP.

Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Change-Id: I6a824524738a9e0609f54bea9d892b4a42a1d3db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42214
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-15 08:40:25 +00:00
Raul E Rangel 742abd3daf soc/amd/picasso/acpi: Delete unused and invalid OperationRegions
0xc50, 0xc52, 0xc6f don't exist on Picasso. The PCI config space
registers define SATA and OHCI which are at the wrong bus locations.
I just remove the whole section since it's not used. We never access the
PCIe Error region, or the PM2 region either.

BUG=b:153001807, b:154756391
TEST=Build Trembyle

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I98aee09770f1df9f553c94580c1ee00c06a9cec1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-15 08:38:43 +00:00
Raul E Rangel 1aa5cff709 soc/amd/picasso/acpi: Remove old AOAC register definitions
We no longer need this code. It's been added differently in CB:42473.

BUG=b:153001807, b:154756391
TEST=Build Trembyle

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I6fe1e465f137ba6afbf9f0dbce501b5fc845e210
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43426
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-15 08:38:34 +00:00
Raul E Rangel e62a17b118 soc/amd/picasso/acpi: Remove invalid and unnecessary devices
These devices are not referenced by anything else.

BUG=b:153001807, b:154756391
TEST=None

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I6ea3c326247dce095b5ac1706dbc37f8b215a21e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43425
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-15 08:38:19 +00:00
Raul E Rangel b3d7ced512 mb/google/zork/.../sleep.asl: Remove unnecessary variable
There is no reason to create a named variable. We can just return the
package.

BUG=b:153001807, b:154756391
TEST=None

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I4f8f0362adf5ea5f026d0ba5ac6ac917fa160142
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43423
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-15 08:37:42 +00:00
Tim Wawrzynczak 0c0bcd4072 PCI IDs: Add PCI ID for JSL DPTF/DTT PCI device
This PCI ID is required in order for JSL devices to perform SSDT
generation for DPTF.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I42209d15bc4f1654814465ce1412576f7349dddc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43421
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-15 08:34:29 +00:00
Evgeny Zinoviev 7c1fe4bd12 util/intelmetool: Fix error message
Add a missing space to the message.

Change-Id: I7d4042ebb587af8558294fb4961100b43910fd4a
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43357
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
2020-07-15 08:33:55 +00:00
Angel Pons 380789a6ee mainboard: Drop optional and empty ACPI \_BFS methods
The ACPI specification, version 2.0 says:

    _BFS is an optional control method.

So, remove them. They have been copy-pasted around quite a bit, and do
not do anything useful. Plus, it's deprecated in later ACPI versions.

Change-Id: I9ef21f231dd6051d410ac3a0fe554908409c2fa7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43443
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-15 08:33:43 +00:00
Felix Held f06d7d7003 amd/picasso: rework DXIO and DDI UPD handling
Turning the DXIO and DDI descriptor fields in the FSP_S_CONFIG struct
into arrays allows to properly iterate over the fields.

BUG=b:158695393
TEST=Mandolin still boots.

Change-Id: I85debe4d52399e933768b89b665ff10c9f7779f8
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43434
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-15 08:32:47 +00:00
Felix Held 692dde599f vc/amd/fsp/picasso: replace #pragma pack(1) with __packed attribute
Forgetting to add the #pragma pack() at the end of the header file can
lead to hard to debug breakage, so get rid of the #pragma pack usage and
add a __packed to the structs that need to be packed which has less
possibly unwanted side effects.

Since commit d44221f9c8 coreboot always
includes commonlib/compiler.h which provides __packed.

TEST=Timeless build results in identical binary.

Change-Id: Icc53168f4fbc3a63a859f686b18e7023d225f8d2
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-15 08:32:18 +00:00
Angel Pons de3fe84ca9 mb/lippert/frontrunner-af: Drop commented-out Kconfig symbol
Drop it before it grows moss.

Change-Id: I0b4f5487cca3c864ba531cc6c78a20c2682fc43d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43287
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-15 08:31:21 +00:00
Rob Barnes 13ec6a03ab mb/google/zork: Change SPI fast speed to 66mhz
Morphius cannot support 100Mhz fast SPI causing it to not boot.
Downgrade all zork boards to fast=66mhz and normal=33mhz to be safe.

BUG=b:161233767
TEST=Boot morphius

Change-Id: I7744dd0cb8dede985fbdc28a64385e0bc4048402
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43459
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Eric Peers <epeers@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-15 03:41:18 +00:00
wuxy 288646744f mb/google/oak: Add new DRAM modules for oak
Add DRAM support for oak:
Samsung  K4E6E304ED-4GB        # 1001
Nanya    NT6CL512T32AM-H0-4GB  # 1010

BUG=b:157702981
BRANCH=oak
TEST=emerge-hana chromeos-ec coreboot chromeos-bootimage depthcharge,
update FW to DUTs,these DUTs can pass 'memtester' test over 48 hours.

Signed-off-by: Xingyu Wu <wuxy@bitland.corp-partner.google.com>
Change-Id: I95eb51debac905145f16b83c9b74a2bd31dbef45
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-07-15 01:55:03 +00:00
Edward O'Callaghan 0f72ddfd20 mb/hatch: Fix Puff baseboard missing mainboard symbols
Fix a missing CONFIG_ prefix in Makefile.

BUG=b:161154280
BRANCH=puff
TEST=builds

Change-Id: I177fcd830a8a03a8db1910bfbfd784a60dc08e11
Spotted-by: Ryan Lin.
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43438
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-14 22:45:36 +00:00
Angel Pons c3c7ef3ec2 soc/intel/skylake: Move `acpi_fill_fadt` to fadt.c
Intel southbridges do this.

Change-Id: I8ecf3c0b0c822185ca66bae1bd65b0cf24512a49
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43378
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
2020-07-14 22:34:03 +00:00