Commit Graph

12512 Commits

Author SHA1 Message Date
Nicolas Reinecke 0908839323 cpu/amd/model_10xxx: add Propus (00100F52h BL-C2) equivalent id
Change-Id: I32eccfb4eae176e0155c53efaf463258653eefc2
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-on: http://review.coreboot.org/8355
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2015-02-11 23:10:44 +01:00
Timothy Pearson 6fdb4d5d3c amd/amdfam10: Fix incorrect core count identification
The core count identification code in the PowerNow! _PSS
ACPI object generation code was incorrectly copied from the
model_fxx code.  This code has been rewritten to properly
return the number of cores installed in the system.

Change-Id: I19567486f2de9dc2c43970addf4d91fa3d233a99
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8421
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2015-02-11 23:10:10 +01:00
Nicolas Reinecke 2f5bb6548d asus/m4a785/Kconfig: Add vgabios PCI id
The PCI id defaults to 1106,3230 -> via chrome 9 ...
Tested on the board.

Change-Id: I5ad91faec9c97f34c8ca48eee9198237e9ea8336
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-on: http://review.coreboot.org/8177
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-11 22:43:21 +01:00
Nicolas Reinecke fa0b3c8cdd cpu/amd/model_10xxx: update microcode
microcode updates are extracted from: www.amd64.org/microcode.html
Mircocode versions of 1020h and 1022h are more recent in coreboot
than inside the AMD archive.

Change-Id: I9f52accc1ebc7057890a769a059048e9982109d2
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-on: http://review.coreboot.org/8354
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-11 22:41:33 +01:00
Stefan Reinauer 44d0fd9841 Add Linux kernel's checkpatch.pl script
Carefully staging to enable checkpatch for coreboot contributions.

The biggest offender of the rules enforced by checkpatch I have found so
far is ... Oh, you guessed it? It's checkpatch itself.

Change-Id: Iaacbcd52c3bc22b083a24127a3ea17a7cc706245
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/8417
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-11 19:53:53 +01:00
Timothy Pearson f73179d4be mainboards/asus/kfsn4-dre: Run BSP FIDVID before AP FIDVID
This resolves an issue on Shanghai dual CPU configurations where
the APs on node 0 would not start.  Single CPU configurations are
unaffected by this issue.

TEST: Booted KFSN4-DRE with dual Opteron 8389 CPUs and verified
proper BSP/AP start and microcode patch levels.

Change-Id: I0f5d4e0e356c6bd64e324b4399ef43b400ecab0c
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8397
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-11 07:16:47 +01:00
Alexander Couzens f251a6d7d4 cpu/intel: >= nehalem: add comments to msr finalize's
Improve documentation of lock down MSRs in finalize().
Most of these aren't documented in public MSRs.

Change-Id: I4fc47bb9b71bdd7907aae65fc18b419a17ae8547
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: http://review.coreboot.org/8294
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Peter Stuge <peter@stuge.se>
2015-02-11 02:58:06 +01:00
Alexander Couzens c768f9231b utils/msrtool: add westmere cpuids to nehalem
Westmere's are nehalem's in 32nm

Change-Id: I529194d50dbe3f585faee14961542433ea96ab75
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: http://review.coreboot.org/8293
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Peter Stuge <peter@stuge.se>
2015-02-11 02:51:16 +01:00
Alexander Couzens ba0e895659 ectool: remove extra printf("Not dumping EC IDX RAM.")
It doesn't provide any useful information.

Change-Id: I13e68d443bbcadea45b8fbcc262ceb9deb3e2e61
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: http://review.coreboot.org/8380
Tested-by: build bot (Jenkins)
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Peter Stuge <peter@stuge.se>
2015-02-11 02:36:40 +01:00
Alexander Couzens a5410dc450 ectool: add write support
Use `ectool -w <addr> -z <data>` to write into ec ram

Change-Id: Id4aca045f6b7c2343be96ea474ee74033897b8b7
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: http://review.coreboot.org/8323
Tested-by: build bot (Jenkins)
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-by: Peter Stuge <peter@stuge.se>
2015-02-11 02:35:32 +01:00
Kyösti Mälkki 754fac4346 PCI subsystem: Remove AGP bridge type
There is no auto-detection for AGP type and we have no hardware that
selects this. Furthermore, we treat AGP bridges just like PCI bridges,
there is no optimisation for higher bandwidth.

Change-Id: I4fe87c83411643cb9b8d3216f2af07bf098174d3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8367
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-10 09:38:32 +01:00
Werner Zeh b474abee84 Baytrail_fsp: Make ME path configurable in menuconfig
By adding a description to ME_PATH it becomes visible
and editable in menuconfig.

Change-Id: I8c2f6a30c10f16b19f3667263db02c93688c9f8f
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: http://review.coreboot.org/8398
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-10 09:26:52 +01:00
Michał Masłowski 208a53527a lenovo/x200: Increase default CBFS_SIZE to 2 MiB
The original firmware has a 2 MiB BIOS region in both 4 MiB and 8 MiB
flash variants.  Let's allow using the whole region instead of the
gm45 default of 1 MiB.

Change-Id: I2d8a04bcb992bf2e8e15890a5c6719810b1cf405
Signed-off-by: Michał Masłowski <mtjm@mtjm.eu>
Reviewed-on: http://review.coreboot.org/8392
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-10 07:27:06 +01:00
Timothy Pearson c1f47c1460 amd/amdfam10: Fix invalid transition latency in PowerNow! _PSS objects
Fix a mistake that led to an invalid 0ms latency in the automatically
generated PowerNow! ACPI _PSS objects.

TEST: Booted FreeBSD and Linux and verified correct latency values.

Found-by: Coverity Scan
Change-Id: I03cecab694708136dc555ca2af7ee9a0bf9be5af
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8376
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-02-10 07:26:32 +01:00
Martin Roth 2213843ae8 fsp_baytrail: Get FSP reserved memory from the FSP HOB list
Because the pointer to the FSP HOB list is now being saved, we can
use that to find the top of usable memory.  This eliminates the need
to hardcode the size of the FSP reserved memory area.

Tested on minnowboard max for baytrail.

The HOB structure used does not seem to be present for the rangeley
or ivybridge/pantherpoint FSPs.  At the very least, the GUID is not
documented in the integration guides.

Change-Id: I643e57655f55bfada60075b55aad2ce010ec4f67
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/8308
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-02-09 17:44:31 +01:00
Martin Roth ad4fa21705 Get rid of .car.global_data warnings for GCC build
The "used" attribute was added in commit 27cf2472 which caused these
warnings to start appearing when using the standard coreboot GCC
toolchain:

{standard input}: Assembler messages:
{standard input}:96: Warning: ignoring changed section type for .car.global_data
{standard input}:96: Warning: ignoring changed section attributes for
.car.global_data

The # at the end of the section name causes the assembler to
ignore everything following the name. I verified that the resulting
binaries are the same with and without the #.		

Change-Id: Iaac8042533842ed887f33895f083b613a18f496a
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/8301
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-02-09 17:44:02 +01:00
Kyösti Mälkki cd02ef19e5 Intel FSP platforms: Fix timestamps
Now that BROKEN_CAR_MIGRATE is fixed we can stash these in CAR.

Change-Id: I49c31b91f34d415778797d08a347a51dbef797e3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8024
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <gaumless@gmail.com>
2015-02-09 11:41:34 +01:00
Nicolas Reinecke 29d358e6a1 lenovo/t430s: Add new port.
The port is based on the x230 / t530.
Tested - is in active use.

Change-Id: Ic5ccfe70343e8aef3465690edce9cdebf153a44d
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-on: http://review.coreboot.org/8359
Tested-by: build bot (Jenkins)
Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-08 09:26:46 +01:00
Alexandru Gagniuc b5669ba579 drivers/pc80/mc146818rtc: Reduce superfluous preprocessor use
cmos_init() had layers of preprocessor directives, which resulted in
a complete mess. Refactor it to make use of the IS_ENABLED() macro.
This improves readability significantly.

One of the changes is to remove in inline stub declaration of
(get|set)_option. Although that provided the ability for the compiler
to optimize out code when USE_OPTION_TABLE is not selected, there is
no evidence that such savings are measureable.

Change-Id: I07f00084d809adbb55031b2079f71136ade3028e
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8306
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-02-06 23:56:04 +01:00
Alexandru Gagniuc a4d784eeab include/types.h: Provide BIT() macro
This macro is controversial for arches where the bits are numbered
MSb first, though we don't support such an arch. We've seen this macro
creep into our tree in different places, so provide it in one place.

Change-Id: I86cd8a16420f34ef31b615aec4e0f7bd3191ca35
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8280
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2015-02-06 19:25:57 +01:00
Timothy Pearson da8fcf0afe mainboards/asus/kfsn4-dre: Indicate native text mode init support
Change-Id: Ib00ecdcad17fa5c0300d22378837e36d0918f9db
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8369
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-06 19:22:56 +01:00
Timothy Pearson 08c15ed266 drivers/xgi: Fix legacy VGA text mode initialization
TEST: Booted KFSN4-DRE with on-board XGI Volari Z9s
Initial text from coreboot appeared, and the Linux
console was displayed immediately at the start of
kernel initialization.  After boot was complete
the text mode console continued to behave normally.

SeaBIOS does not currently make use of the legacy
VGA text-mode display.

Change-Id: I2177a1d00e6f07db661dd99fe0184e2c228404d1
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8360
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-06 19:22:36 +01:00
York Yang 114baa0a0a intel/fsp_rangeley: Indent '#define' consistently
The indentations of #define are not consistent in chip.h. Update to make 
all #define indentations being aligned and put them after the variable 
declaration.

Change-Id: I37550acac18bac3efddb580ef6b956be0e2b357a
Signed-off-by: York Yang <york.yang@intel.com>
Reviewed-on: http://review.coreboot.org/8333
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Tested-by: build bot (Jenkins)
2015-02-06 00:58:50 +01:00
Martin Roth 582b2aee0f FSP & CBMEM: Fix broken cbmem CAR transition.
1) Save the pointer to the FSP HOB list to low memory at address 0x614.

This is the same location as CBMEM_RESUME_BACKUP - the two aren't used
in the same platform, so overlapping should be OK.  I didn't see any
documentation that actually said that this location was free to use, and
didn't need to be restored after use in S3 resume, but it looks like
the DOS boot vector gets loaded juat above this location, so it SHOULD
be ok.  The alternative is to copy the memory out and store it in cbmem
until we're ready to restore it.

2) When a request for the pointer to a CAR variable comes in, pass back
the location inside the FSP hob structure.

3) Skip the memcopy of the CAR Data.   The CAR variables do not
get transitioned back into cbmem, but used out of the HOB structure.

4) Remove the BROKEN_CAR_MIGRATE Kconfig option from the FSP platform.

Change-Id: Iaf566dce1b41a3bcb17e4134877f68262b5e113f
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/8196
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-02-06 00:53:13 +01:00
Kyösti Mälkki 0490f74d78 TPM: Fix whitespace
Change-Id: I2d00a2964b16436356c5e02764897e37ef610efc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8343
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-06 00:25:59 +01:00
Timothy Pearson 67085e0c09 mainboards/asus/kfsn4-dre: Enable native VGA initialization
Change-Id: I953ced7d34af9ec0923fa6df93b9ad4270196c77
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8332
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-05 17:37:17 +01:00
Timothy Pearson c522fc8f38 drivers/xgi/z9s: Port Linux framebuffer initialization to coreboot
Add native XGI Z9s framebuffer support to coreboot
XGI initialization code largely taken from Linux 3.18.5

TEST: Booted KFSN4-DRE with XGI Volari Z9s into SeaBIOS
with SeaVGABIOS enabled.  Text appeared correctly on screen
and interaction with graphical comboot menu was successful.
However, Linux cleared the framebuffer on boot, rendering the
screen useless until Linux loaded its native xgifb driver.

Change-Id: I606a3892849fc578b0c4d74536aec0a0adef3be3
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8331
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-02-05 17:37:05 +01:00
Dave Frodin 5c015f045d southbridge/amd/pi: write_hpet requires additional config option
This copies what was done in southbridge/amd/agesa in:
commit 56f46d8 agesa/family15tn: Switch to per-device ACPI

TEST: amd/lamar.

Change-Id: Id8890ccd4a1ea783ad4740333ae6b061b6bbd7fc
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8288
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-05 17:34:05 +01:00
Dave Frodin ef9a4e6aec southbridge/amd/pi: Update Kconfig and makefiles for bolton
Change-Id: I208c931bdaee572c9df11b35c1e6e9f27609ea6c
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8287
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-02-05 17:33:42 +01:00
Dave Frodin 9cfa742a26 southbridge/amd/pi: Add the bolton definitions
This adds the PCI and interrupt related definitions
for the bolton specific features.

Change-Id: Ia6530c57ec5a4a5c4525bfbae0eb5db04c0bef9e
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8286
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-02-05 17:33:00 +01:00
Kyösti Mälkki c3f6bb086b AMD HyperTransport: Drop unused link optimisation
Change-Id: Ia4398f6eb013c69838487bdd02d094f97d7224b6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8342
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-05 16:11:43 +01:00
Kyösti Mälkki 08e39c572f AMD K8: Remove some excessive preprocessor use
Tests on CPUID are valid regardless of revision.

Change-Id: I5a3a01baca2c0ecfb018ca7965994ba74889a2e2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8337
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-05 02:20:42 +01:00
Kyösti Mälkki 9bc83888ad newisys/khepri broadcom/blast: Drop duplicate entry in Kconfig
Keep the value that is listed first, it also the one with a more
recent change.

Change-Id: I0336c962544d75f94512563c08f280aa43c7a175
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8336
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-05 02:18:06 +01:00
Kyösti Mälkki 09b5e4d005 AMD8131: Remove obsolete directory
Change-Id: I875384e55a4a71d1a5c962d128d13356f3befa56
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8335
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-05 02:17:42 +01:00
Dave Frodin 17ace82552 superio/fintek: Add required changes so F81216H can be used
The amd/lamar mainboard is the first mainboard to use the f81216h.
These changes are needed to fix up commit 27a63d77 so the
Super I/O builds and functions correctly.
  - Wrong #include name
  - Removed global variable in romstage
  - Missing "case" in switch()

Change-Id: I1b2058a915b776664fba14e4341e8a410b50330f
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8255
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-04 15:45:39 +01:00
Kyösti Mälkki 1608f3651f cpu/amd (non-AGESA): Remove terminator from microcode blob
Change-Id: I6370e971922dee5e8d476a883c5f0f32fbbc8911
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4534
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-02-03 04:52:12 +01:00
Kyösti Mälkki d15cb519ad amd/model_10xxx: Drop AMD_UCODE_PATCH_FILE selection
Include microcode updates in CBFS for every CPU revision the platform
can support, as changing to different CPU revision should not require
a coreboot rebuild.

This increases CBFS usage from 2 kB to 14 kB.

Change-Id: I6bf90221a688f1a54e49641ce3ba378c5bf659f9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4521
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
2015-02-03 04:52:00 +01:00
Kyösti Mälkki 5fe1fb7a5f cpu/amd (non-AGESA): Load microcode updates from CBFS
Change-Id: Ic67856414ea2fea9a9eb95d72136cb05da9483fa
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4502
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-02-03 04:51:52 +01:00
Alexandru Gagniuc 893b81f79f cpu/amd/model_10xxx: Remove UPDATE_CPU_MICROCODE option
This option is now deperecated by loading microcode updates from cbfs.
Remove this option in anticipation of implementing CBFS loading for
AMD cpus. Removing it beforehand results in less patch overhead.

Change-Id: Ibdef7843db686734e2b6b1568692720fb543b240
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8322
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-02-03 04:51:43 +01:00
Jonathan A. Kollasch 30c34c0751 nvidia/ck804: make Message Signaled Interrupts work
Use HT MSI Mapping capability register at 0xe0 in CK804 HT device to enable
HT MSI Mapping so that MSIs work.  Prior to this change PCIe devices
downstream of the CK804 with MSI enabled would fail to actually assert
their interrupt.  Tested on msi/ms7135 and winent/mb6047 running Debian
GNU/Linux 7.0 (wheezy).

Change-Id: I5e0dc8b352f3d04e3b16b899af11d2b908a82850
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/8276
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-03 00:47:26 +01:00
Alexandru Gagniuc a583924252 src/arch/*/include/stdint.h: Provide definitions for bool type
Although bool normally belongs in stdbool.h, for our use cases,
providing these definitions in stdint.h is acceptable.

Change-Id: I1d0ca1018efacc27d7a4a72aa452912e004401f9
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8279
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2015-02-02 20:29:23 +01:00
Jonathan A. Kollasch e299ae673c winent/mb6047: switch to CAR version of ck804 early_setup.c
Change-Id: I9b45b7fbd862a5600ead7ad4e623a8a87ae364aa
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/8319
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-02-01 16:48:36 +01:00
Jonathan A. Kollasch bdebb07d2f winent/mb6047: clean up includes in acpi_tables.c
Change-Id: I63bdc856fa4232cd66ff2e48e39c2cdb97bb88d3
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/8316
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-02-01 16:45:43 +01:00
Jonathan A. Kollasch 679efee2d7 winent/mb6047: use correct ACPI SCI interrupt trigger
Change-Id: I245c0afb66f3a29b5acb40e8d949d8b1aa08cd73
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/8315
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
2015-02-01 16:43:39 +01:00
Jonathan A. Kollasch fcf5988cf6 winent/mb6047: drop inaccurate comment in acpi_tables.c
Change-Id: Ib0bb8bed32b96a5f7fd48407bd111972f89e7907
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/8314
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-02-01 16:11:17 +01:00
Vladimir Serbinenko ac1b6def75 lenovo/x230: Set xhci_switchable_ports and superspeed_capable_ports.
Fixes USB3 ports degraded to USB2 speeds.

Change-Id: Ie71c9fb6e52a3e72bb1e61351ad1cc0492d93cbc
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/8313
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
2015-02-01 10:12:12 +01:00
Vladimir Serbinenko b26156ec65 bd82x6x/xhci: Set mask of ports switchable between USB2 and USB3.
Change-Id: Ica1cc90715c1810668e3f4f7282e5757a5688483
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/8312
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-02-01 08:22:40 +01:00
York Yang e1e11e63af intel/rangeley: Update UPD_DATA_REGION to support POST-GOLD 2 FSP
Rangeley POST-GOLD 2 FSP added PCIe ports de-emphasis configuration
by UPD input. Update UPD_DATA_REGION structure for matching up this
FSP change.

PcdCustomerRevision is a debugging aid that will be output to debug
message in FSP. When needed, it can be customized by BCT tool for tracking
BCT configurations.

Change-Id: I6d4138c9d8bbb9c89f24c77f976dbc760d626a9b
Signed-off-by: York Yang <york.yang@intel.com>
Reviewed-on: http://review.coreboot.org/8107
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <gaumless@gmail.com>
2015-01-31 23:09:26 +01:00
Martin Roth 9cd155334b FSP platforms: Clear area in CAR for cbmem
This patch clears the CAR area. The FSP loads the entire CAR area with a
pattern instead of clearing it.  At least the cbmem area needs to be
cleared or cbmem will not use it.

Change-Id: I829ddc26133353a784dfc01729af9b3bf427e889
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/8195
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-31 22:30:03 +01:00
Timothy Pearson 4e6f0c289b asus/kfsn4-dre: Increase maximum logical CPUs for Istanbul devices
Test:
Single Opteron 2419 with 1GB RAM in slot A1
Booted Ubuntu Linux 14.04 and verified all 6 cores were visible
Brief stress test of all 6 cores simultaneously
Verified proper ACPI power states for all 6 cores

Change-Id: I1e598e36f9eaed5ba8a18b9c62ceedee16870f15
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8311
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
2015-01-31 21:33:20 +01:00