Define the CCD (aka "Webcam") USB port in the devicetree as
it is used in multiple places. It is used in devtree to
disable it based on the CMOS setting "webcam", and in the
devicetree to configure the port tuning.
This also corrects the port that is disabled on CML, from
usb2_port[6] to usb2_port[3].
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I16e368fc7965f978f2302633122ba63038603c1e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64704
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Group the USB ports by hardware ports, rather than separate USB 2.0 and
3.0 interfaces.
This also removes usb3_port[2] as it is not connected and fixes the labelling of usb3_port[0] and usb3_port[1].
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I7923fc00c36687a7f89d863eb0ea4e01a036502d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64703
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Update the Vbt to disable the fixed mode feature, to allow for
bootloader resolutions higher than 1920x1080.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ibd9850dcaef97a58c6694ee594014e9f16ae7f96
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65337
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
There is a new ground rule, variant should honor baseboard lock gpios.
Thus, lock the gpio which is locked in baseboard.
BUG=b:216671701
TEST=check gpios are locked in pinctrl dump.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Ieed2d40b0222d8c8c193e0590131f83a5d96add9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65598
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
There is a new ground rule, variant should honor baseboard lock gpios.
Thus, lock the gpio which is locked in baseboard.
BUG=b:216671701
TEST=check gpios are locked in pinctrl dump.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I61931b0b2f1f936a672e72c98b83d66ba0059bf3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
This patch sets the Power Limits and Voltage Regulator settings for
three RaptorLake SKUs (45W, 28W and 15W) following the guidance from
document 686872 (June 7th edition).
BUG=b:237809660
TEST=Power Limit and VR serial logs review + debug instrumentation
SKUs successfully booted
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Change-Id: I7e9d4039615e6c33b869c6243efbfeb2259ac219
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65582
Reviewed-by: Zhixing Ma <zhixing.ma@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
In reality the expression should not overflow as the value
fits in 32 bits.
Change-Id: I50d83dce25a4d464e1c979502c290d8ecd733018
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
mch_id is set to zero and then unnecessarily tested.
TEST=build and boot image on ADL RVP board
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Change-Id: I4f48742b04edd50fbc0db342b563534e709d6fdd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65583
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Platform with public FSP hooked-up have an additional parameter
to control CNVi WiFi with CnviWifiCore UPD.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I19efb645fbe1530a571c92d0573c1c60ff6605a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Update 3rdparty/fsp submodule to include AlderLake FSP.
Hook up the Kconfig settings to point to Fsp.fd and headers for
ADL-S and ADL-P platforms which the FSP has been published for.
The FSP binaries are compliant with the specification revision 2.3
so update these settings accordingly.
Although FSP header is v2.3 compliant, the features set of the FSP
v2.3 is not being met.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I577931da7952b681534bb78b7b2c7683cd99febd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65519
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The patch disables PCH USB2 Phy power gating to prevent possible display
flicker issue for primus board. Please refer Intel doc#723158 for
more information.
BUG=b:237725329
TEST=Verify the build for crota board
Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: I6dde74c098ba57b7cd66ce7b9ee941b8961ad20c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65594
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Cyan Yang <cyan.yang@intel.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Modify GPIOs according to SOC_GPIO_Table_0629.xlsx.
- GPP_A21 from TCP_DP1_CTRLCLK to NC
- GPP_A22 from TCP_DP1_CTRLDATA to NC
- GPP_E20 from NC to TCP_DP1_CTRLCLK (Native Function 1)
- GPP_E21 from NC to TCP_DP1_CTRLDATA (Native Function 1)
BUG=b:237468533
TEST=emerge-brask coreboot
Change-Id: I8e7d343731efbfc04304d52a3493ab30b8a739b0
Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65552
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ricky Chang <rickytlchang@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
There is a requirement that the TPM RST signal cannot be asserted by
software. On nissa this is PLT_RST_L, so lock this pin to prevent it
being reconfigured as a GPIO.
BUG=b:216671701
TEST=Try to change GPP_B13 from the kernel:
$ echo 677 > /sys/class/gpio/export
$ echo out > /sys/class/gpio/gpio677/direction
$ echo 0 > /sys/class/gpio/gpio677/value
$ echo 1 > /sys/class/gpio/gpio677/value
GSC console doesn't show "PLT_RST_L ASSERTED" / "PLT_RST_L DEASSERTED"
Change-Id: Id5d64b4b028e4f63c4acb05cd8632d0642866688
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65591
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Set the GPIO configuration of joxer
BUG=b:237628218
TEST=USE="project_joxer emerge-nissa coreboot"
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I1f7529342fc0800878f875d3641a2f93fbe6009a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65553
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Branding changes to unify and update Chrome OS to ChromeOS (removing the
space).
This CL also includes changing Chromium OS to ChromiumOS as well.
BUG=None
TEST=N/A
Change-Id: I39af9f1069b62747dbfeebdd62d85fabfa655dcd
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65479
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
CPUID_RAPTORLAKE_P_Q0 is ES. Add it to generate is_es = 1 in ACPI
BUG=b:229134437
BRANCH=firmware-brya-14505.B
TEST=Booted to OS on adlrvp + rpl silicon
Signed-off-by: zhixingma <zhixing.ma@intel.com>
Change-Id: I67d70dc7e916a4818869aef86e7e642b66ea5dae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Create PSP NVRAM and RPMC NVRAM region with size 128K & 64K
respectively, which are supported region by the PSP.
moved CBFS up due to build error, CBFS need not to be at the end the flash for amd Zen cpu.
Change-Id: Ide778c61a755697c1bef1eaa87f2976d8ff12eb6
Signed-off-by: Ritul Guru <ritul.bits@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65341
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This change adds new Rembrandt SoC support by defining it as base SoC
of sabrina as sabrina is derived from Rembrandt SoC.
All the needed changes for Rembrandt SoC will be applied under
SOC_AMD_REMBRANDT config.
Change-Id: I1c9392918cc2c6b511d467f99aceefc725750ce6
Signed-off-by: Ritul Guru <ritul.bits@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63353
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The patch disables PCH USB2 Phy power gating to prevent possible display
flicker issue for kano board. Please refer Intel doc#723158 for
more information.
BUG=None
TEST=Verify the build for kano board
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I19430a68e1e847e71382781563200a4c88f37a59
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65107
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Add new folder and basic drivers for Mediatek SoC 'MT8188'.
Difference of modules including in this patch between MT8188 and
existing SoCs:
Timer:
Similar to MT8195 and MT8186, MT8188 uses v2 timer.
EMI/PLL/SPI:
Different from existing SoCs.
The implementation is based on these files:
MT8188G_Application Processor Technical Brief_v0.4.pdf
MT8188G_Functional Specification v0.4.pdf
MT8188 Application Processor Registers-1.pdf
MT8188 Application Processor Registers-2.pdf
TEST=saw the coreboot uart log to bootblock
BUG=b:233720142
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I3320f3d49a9b9ed781ceb812e4341e379db4ac20
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65585
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@chromium.org>
This patch assigns FSP handler event for FSP-M and FSP-S with coreboot
romstage and ramstage debug handler when FSP_USES_CB_DEBUG_EVENT_HANDLER
Kconfig is enabled.
BUG=b:237263080
TEST=Able to build and boot MTL simics. Also, verified the FSP debug
log is using coreboot debug library as below:
Before:
Register PPI Notify: DCD0BE23-9586-40F4-B643-06522CED4EDE
Install PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3
Install PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A
The 0th FV start address is 0x000F961B000, size is 0x00150000, handle
is 0xF961B000
Register PPI Notify: 49EDB1C1-BF21-4761-BB12-EB0031AABB39
Register PPI Notify: EA7CA24B-DED5-4DAD-A389-BF827E8F9B38
Install PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6
With this code change:
[SPEW ] Register PPI Notify: DCD0BE23-9586-40F4-B643-06522CED4EDE
[SPEW ] Install PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3
[SPEW ] Install PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A
[SPEW ] The 0th FV start address is 0x000F95C0000, size is 0x00160000, handle is 0xF95C0000
[SPEW ] Register PPI Notify: 49EDB1C1-BF21-4761-BB12-EB0031AABB39
[SPEW ] Register PPI Notify: EA7CA24B-DED5-4DAD-A389-BF827E8F9B38
[SPEW ] Install PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I80ba73afed642e6d21c5310e9bf734f6f7170347
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65456
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This patch ensures AP UART messages are coming over LPSS UART 0 hence,
select required kconfig and program both early and late UART
RX/TX GPIOs accroding to the rex schematics dated 06/27.
BUG=b:224325352
TEST=Able to see AP UART log over LPSS UART0.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I7daa8200d1a7cf825dfdfed538573efd57ab2d97
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65454
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the support LP5 RAM parts for rex:
DRAM Part Name ID to assign
MT62F512M32D2DR-031 WT:B 0 (0000)
BUG=b:224325352
TEST=emerge-rex coreboot
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ibcd25ae80d625b623b9a78ff2cd4447e85831cc0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65476
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add memory init with placeholder to fill in required memory
configuration parameters. DQ map and Rcomp can be auto probed by
the FSP-M hence, kept it as default.
BUG=b:224325352
TEST=util/abuild/abuild -p none -t google/rex -a -c max
Able to boot till FSP-M/MRC using MTL simics.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I5baa87411c28a20602eb5a7077f00664ccab3ade
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64850
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add SMI handler implementation to manage power cycle,
power state transition and Chrome EC events.
BUG=b:224325352
TEST=util/abuild/abuild -p none -t google/rex -a -c max
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I10aab8257fce92aaf913a53c0c9fb6c1a4f5dea6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64623
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable building for Chrome OS and add associated ACPI configuration.
BUG=b:224325352
TEST=util/abuild/abuild -p none -t google/rex -a -c max
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I75cb2d30d699166a056ed9d3c0779816b733b0d2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64621
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add stubbed out GPIO configuration and perform GPIO initialization
during bootblock, romstage and ramstage.
BUG=b:224325352
TEST=util/abuild/abuild -p none -t google/rex -a -c max
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I51426f9557dafc357fc54a971b6f76fac5323e0a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64593
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add entry point stubs of each stage for Rex. More functionalities will
be added later.
BUG=b:224325352
TEST=util/abuild/abuild -p none -t google/rex -a -c max
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I2310e58ab92bdb0ce86a9f7284cc0b3e04a2889f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64591
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is a stub for rex, which is a an Intel Meteor Lake-P
reference platform.
BUG=b:224325352
TEST=util/abuild/abuild -p none -t google/rex -a -c max
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I46bd8d47b370cacbe0a09bbeaccacf7f1d51d8b6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62969
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add definitions for the GPIO pins on Meteor Lake SoC,
as well as GPIO IRQ routing information and supporting ACPI ASL.
For now, add the following GPIO communities and GPIO groups:
Comm. 0: GPP_CPU, GPP_V, GPP_C
Comm. 1: GPP_A, GPP_E
Comm. 3: GPP_H, GPP_F, SPI0, VGPIO3
Comm. 4: GPP_S, JTAG
Comm. 5: GPP_B, GPP_D, VGPIO
BUG=b:224325352
TEST=util/abuild/abuild -p none -t google/rex -a -c max
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: I7fe9654f22b074a9af18eb7bcdc21812dee77035
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64169
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Not all of the fields of the amd_cb_config structure were properly
initialized. Rather than initialize each field individually, initialize
the entire structure to 0.
TEST: Boot chausie
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Ia343f01bce3956d66d01ce485b43963193c9df31
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
These are architectural and followup works will address
the VGA MMIO and/or ASEG better.
Change-Id: I88e1dca8058661e31ba934b9860751e13a107108
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55928
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The patch disables PCH USB2 Phy power gating to prevent possible display
flicker issue for primus board. Please refer Intel doc#723158 for
more information.
BUG=b:237421399
TEST=Verify the build for gimble board
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: Ie66c9679c985215ad7f1a5ae76560b839ea95702
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65474
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For ipq806x this fixes two resources getting declared
with same index. The latter previously overwrote former.
Change-Id: Ifee321d930d5433c824e2e977f1bb455766582f0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55914
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
In ADL-N, cse_fw_sync is done in ramstage. Compile debug_feature.c in
ramstage to fix build error.
BRANCH=firmware-brya-14505.B
Change-Id: I0118b024fce4781cf6008b1c0b416e409fc52065
Signed-off-by: Krishna P Bhat D <krishna.p.bhat.d@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63979
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In the CSE FW update flow, update is triggered when there is a mismatch
in CSE versions. CSE RW blob is directly mapped from SPI flash, hashed,
compared and then the CSE RW region is updated. However, in the case of
compressed blobs, we cannot directly map the blobs from SPI. It needs to
be decompressed before the hash is calculated and compared. Add a check
for compressed blobs and figure out whether it needs to be directly
mapped from SPI or loaded into memory allocated for file in CBMEM, with
the provided CBMEM ID.
BRANCH=firmware-brya-14505.B
Change-Id: I3bc7708c95272e98702bc25b2334e6e64a93da8a
Signed-off-by: Krishna P Bhat D <krishna.p.bhat.d@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63743
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
CSE FW sync is currently performed in romstage, when uncompressed ME_RW
blobs are used. When compressed blobs are used, this has to be done in
post-RAM stages. Add Kconfigs to describe when the CSE FW sync will be
performed, in romstage or in ramstage.
BRANCH=firmware-brya-14505.B
Change-Id: Iac37aaa5ede5e1cd2d76a58ce2db9cb5b8f42398
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65366
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Sean Rhodes