Commit Graph

44832 Commits

Author SHA1 Message Date
David Wu f0d9c1212c mb/google/brya/var/kano: Move max98373 amp ACPI info to I2C0
Move max98373 amp ACPI info to I2C0 according to kano's schematics version KANO_MLB_Proto_0811.

BUG=b:192370253
TEST=FW_NAME=kano emerge-brya coreboot chromeos-bootimage

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I8f7a7938dd407666e0104ba64b22da85216a145f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57909
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-27 13:33:42 +00:00
Eric Lai 658d7c56b8 mb/google/brya: Correct SSD power sequence
SSD sometimes can't be detected in in warm/cold boot stress.
M.2 spec describes SSD_PREST should be sequenced after power enable.

BUG=b:199822704
TEST=SSD was always discovered in warm/cold boot stress.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: If0a9e36cda4dc91bbccec02f39ccb9b658d24056
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57665
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-27 13:33:23 +00:00
Karthikeyan Ramasubramanian b3ffff87dd soc/amd/cezanne, vc/amd/fsp/*: Add support for CCP DMA SVC call
Add support to access the boot device from PSP through Crypto
Co-Processor (CCP) DMA. Implement a SVC call to use CCP DMA on SoCs
where it is supported and a stub on SoCs where it is not supported. This
provides an improved performance while accessing the boot device and
reduces the boot time by ~45 ms.

BUG=b:194990811
TEST=Build and boot to OS in guybrush. Perform cold and warm reboot
cycling for 250 iterations.

Change-Id: I02b94a842190ac4dcf45ff2d846b8665f06a9c75
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-27 13:29:37 +00:00
Kenneth Chan 4012388736 mb/google/hatch/moonbuggy: Update DPTF parameters
Update the DPTF parameters received from the thermal team.

BUG=b:188596619
TEST=emerge-ambassador coreboot

Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Change-Id: I081963b97ed2dae0f5d026f6443c954b52347a8a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57919
Reviewed-by: Joe Tessler <jrt@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-27 13:28:16 +00:00
Tim Crawford 81db2415eb mb/system76/gaze15: Disable OC support
Clevo indicated that DIMMs running at 2933 MHz are not supported on a
number of processors used for this model.

Change-Id: Iadf611a64de664c783696e51cfe858ca95903936
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57897
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
2021-09-27 13:27:51 +00:00
Tim Crawford 97bc0398c4 mb/system76/lemp10: Use PME virtual wire for SWI
Match the behavior of the other TGL-U boards.

Change-Id: Ida962255f7a2435319d739d59eb2dc58fe342ae8
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57895
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
2021-09-27 13:27:27 +00:00
Tim Crawford bd9b044a96 mb/system76: rtd3: Remove SrcClk pin on CPU RP
Setting srcclk_pin only works for PCH PCIe devices. Disable them on the
CPU RP and add a TODO.

Change-Id: I32db116feb33a8448eb8586fe9e882b8879489d4
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57882
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
2021-09-27 13:27:00 +00:00
Felix Singer 9c120ef1d0 mb/intel/kblrvp: Clean up dsdt.asl
Move includes using library paths to the top and remove unnecessary
comments. Also, get rid of that unnecessary _SB scope. Use an absolute
path for the PCI0 device instead.

Change-Id: Ibb63f3ecd9cfbb6f564e0a9968c2776c25d84f79
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57856
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-27 13:25:50 +00:00
Felix Singer ce9d41fe2d mb/51nb/x210: Clean up dsdt.asl
Move includes using library paths to the top and remove unnecessary
comments. Also, get rid of that unnecessary _SB scope. Use an absolute
path for the PCI0 device instead.

Change-Id: I7255ac1ec6c43dd4b21325ae60e117458bea956d
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-27 13:25:32 +00:00
Felix Singer e87b2a2d3d mb/razor/blade_stealth_kbl: Clean up dsdt.asl
Move includes using library paths to the top and remove unnecessary
comments. Also, get rid of that unnecessary _SB scope. Use an absolute
path for the PCI0 device instead.

Change-Id: I375ab879dd95d6a7a20644dc36312a1e62f58226
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57854
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-27 13:25:04 +00:00
Felix Singer 75ff7859cb mb/facebook/monolith: Clean up dsdt.asl
Move includes using library paths to the top and remove unnecessary
comments.

Change-Id: I4e5be60d2784d003a388c52254514d0ab4d002b0
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57853
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2021-09-27 13:24:31 +00:00
Felix Singer a29e75482c mb/google/glados: Clean up dsdt.asl
Move includes using library paths to the top and remove unnecessary
comments.

Change-Id: Id26d9dfc3822b9120360fc2cb2ced8d67345a659
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-27 13:24:13 +00:00
Felix Singer 80f3cbe787 mb/intel/kunimitsu: Clean up dsdt.asl
Move includes using library paths to the top and remove unnecessary
comments.

Change-Id: I42458f16a323d3e37d0ee1bd8335e1f8d0e1fadc
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57851
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-27 13:23:52 +00:00
Felix Singer 35d94009fb mb/intel/saddlebrook: Clean up dsdt.asl
Move includes using library paths to the top and remove unnecessary
comments. Also, get rid of that unnecessary _SB scope. Use an absolute
path for the PCI0 device instead.

Change-Id: I730cd3eeffff60b3b569bfb748febbdc8ca85990
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57850
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-27 13:23:20 +00:00
Zhi Li 0c9bc82d48 mb/google/dedede/var/blipper: Generate SPD ID for supported parts
Add the relevant memory configuration of beetley to the blipper coreboot code
The memory parts being added are:
1. Micron MT53E512M32D1NP-046 WT:B
2. Samsung K4U6E3S4AB-MGCL
3. Hynix H54G46CYRBX267

BUG=b:200000608
TEST=emerge-dedede coreboot

Signed-off-by: Zhi Li <lizhi7@huaqin.corp-partner.google.com>
Change-Id: I0b04f64cb007a58ae98f5ed187feb4859a43b1b6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57670
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-27 13:21:50 +00:00
Felix Held 07958d3e86 soc/amd/common/block/include/acpimmio_map: add AOAC acronym in comment
The Always On Always Connected block is referenced as AOAC in the code,
so add that acronym in the comment and change the "Connect" to
"Connected".

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6a23e0ccff62c6ceddae70e1bef5c5abf872c495
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57926
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-27 13:20:33 +00:00
Felix Held fafeb190ae cpu/x86/mp_init: add expansion for SIPI acronym
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic182d7c551932ab6917a81568490ed18acdcd597
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57927
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-27 13:20:16 +00:00
Reka Norman 91feb06ece Revert "Revert "util/abuild: Regenerate xcompile on every abuild run""
This reverts commit d94f8bbe9d.

This is a reland of https://review.coreboot.org/57651. The original
change broke parallel abuild runs since the xcompile file was deleted by
every recursive call to abuild. This issue was fixed by rebasing on top
of a change which only regenerates the xcompile on non-recursive calls.

BUG=None
TEST=Parallel abuild run succeeds.

Change-Id: I086ba7b2ae1b8b14459838bd18ce962a84aa306d
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57913
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-09-26 16:08:05 +00:00
Subrata Banik 7b523a4be9 soc/intel/alderlake: Use intel_microcode_find() to locate ucode.bin
`intel_microcode_find()` function uses cached ucode data hence it would
avoid locating ucode.bin from CBFS while passing ucode.bin pointer to
FSP.

Change-Id: I8f92c9f20dfb055c19c6996e601c8c24767aecb7
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57831
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-25 18:39:06 +00:00
Gwendal Grignou cdad2ce2b0 mb/google/guybrush: Remove ALS presentation
guybrush does not have a light sensor, do not include ACPI0008
ACPI device (Light sensor that will be managed by acpi-als IIO
kernel driver).

BUG=b:200823325
TEST=Check on Guybrush360 the sensor is not presented.

Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Change-Id: Id1dcb3a01ee43f780e4b118d88a0351e4c543f5a
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57847
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-09-24 22:49:48 +00:00
Casper Chang 12315b52c4 mb/google/brya/variants/primus: config dram speed to 3733
This change config the DRAM speed to 3733 for primus.

BUG=b:200752480
BRANCH=none
TEST=Verified that `dmidecode -t17` shows the correct
     configured memory speed

Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: I2f3a9489dddcf102b0ffc71eb9cdab6ad38d1391
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57867
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-24 21:37:47 +00:00
Furquan Shaikh 4f5e8e030c mb/intel/adlrvp: Switch to using device pointers
This change replaces the device tree walks with device pointers by
using alias for dptf_policy device.

Change-Id: I02ca63ac2cc1b8ed2f5a381b3824c9beff7f33ec
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57870
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-24 21:20:14 +00:00
Furquan Shaikh eafca1f13a soc/intel/alderlake: Switch to using device pointers
This change replaces the device tree walks with device pointers by
using alias for tcss_usb3_port* devices.

Change-Id: I65d9c83a9d0aab5a42f5a7cc6df98a154e79d16a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57848
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-24 21:20:10 +00:00
Furquan Shaikh 20c709daad device: Drop unused function `dev_find_matching_device_on_bus`
With use of device pointers, `dev_find_matching_device_on_bus()` is
now unused and hence this change drops the function.

Change-Id: I30fcb2d9932d770ca614cceffb15646ce8256465
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57846
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-24 21:20:07 +00:00
Furquan Shaikh 0f73791606 mb/google/zork: Switch to using device pointers
This change replaces the device tree walks with device pointers by
using alias for following devices:
1. audio_rt5682
2. xhci0_bt
3. xhci1_bt
4. acp_machine
5. i2c2

Change-Id: I56921ab54716e4d771d9de1a479f191ca5657eba
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-24 21:20:03 +00:00
Karthikeyan Ramasubramanian 6fa72c7f4c mb/google/guybrush: Configure the level for AMD Firmware binaries
AMD Firmware tool allows configuring the directory table level in which
the binaries have to be added. This helps to achieve space and boot time
savings.

BUG=b:195329409
TEST=Build and boot to OS in Guybrush. Achieve a boot time savings of
~75 ms and space savings of ~600 KB per RW section.

Change-Id: Idc212b8c4f8aacfb0132983a8055f1e97af42983
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bao Zheng <fishbaozi@gmail.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-24 21:14:50 +00:00
Joey Peng 79449732c5 mb/google/brya/var/taeko: Enable SaGv support
Enable SaGv support for taeko

BUG=b:198548214
TEST=FW_NAME=taeko emerge-brya coreboot
     Flash fw into DUT and can boot successfully

Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: I580a12ca511d8cde6fee1079e39e6976202da4d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57549
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-24 19:32:36 +00:00
David Wu 4ceac3085a mb/google/brya/var/kano: Set vGPIO configuration
Due to the vGPIO is not set correctly, without setting those pins for PEG60,
CPU cannot communicate with PCH about the clkreq state.

BUG=b:200886824
TEST=FW_NAME=kano emerge-brya coreboot chromeos-bootimage

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I6adf73103ecb02c67d9a199e13d2ead9b8b2276f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57875
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-24 19:32:23 +00:00
David Wu c00be31183 mb/google/brya/var/kano: Enable EC keyboard backlight
Enable EC keyboard backlight for kano.

BUG=b:192370253
TEST=FW_NAME=kano emerge-brya coreboot chromeos-bootimage

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I7f56b92b60cadf72eb02fd8bcb87baf36acc16e5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57877
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-24 19:31:55 +00:00
David Wu 7f7424c498 mb/google/brya/var/kano: Enable SaGv support
Enable SaGv support for kano

BUG=None
TEST=FW_NAME=kano emerge-brya coreboot

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ifc537a5137f5e6eb10cd4c160923ea4da1f6b0d0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57876
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-24 19:31:36 +00:00
Ricardo Quesada 1427f12adf elogtool: Fix off-by-one error in month in timestamp
elogtool was setting the timestamp with the wrong value in the month.
This CL fixes that by incrementing the month by one. This is needed
since gmtime() returns the month value starting at 0.

TEST=pytest elogtool_test.py (see next CL in relation chain)

Change-Id: I00f89ed99b049caafba2e47feae3c068245f9021
Signed-off-by: Ricardo Quesada <ricardoq@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-09-24 18:08:43 +00:00
Ben Chuang 325f431a91 drivers/genesyslogic/gl9755: Disable ASPM L0s support
When the entry delay of L0s is less than the entry delay of L1, GL9755
will enter L0s state first. When it exits from L0s state, the time of L1
entry will be reset. Therefore, the conditions for entering L1 state
cannot be met. In order to enter L1 state, L0s needs to be disabled.

BUG=b:195611000
TEST=Verify GL9755 enters L1 by observing CLKREQ# de-asserts.

Signed-off-by: Ben Chuang <benchuanggli@gmail.com>
Change-Id: If121b5cb534eb32bac8992683c3f0eee8946acec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-24 17:56:09 +00:00
Raul E Rangel 333652c5b2 cpu/x86/mp_init: Add comment to smm_do_relocation
It took me a while to understand the SMM set up flow. This adds a
clarifying comment.

BUG=b:194391185, b:179699789
TEST=None

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I9c73e416b8c583cf870e7a29b0bd7dcc99c2f5f4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57858
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-09-24 17:11:54 +00:00
Felix Held 5ef5873576 soc/amd/common: factor out FSP-related parts of common Kconfig
TEST=Timeless build for Mandolin results in identical image.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib2fb6c29b9f42c00f252994ae2a40b7ff668105a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57885
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-24 15:48:24 +00:00
Felix Held c9737c5ce9 soc/amd/common: move block/pi out of the block folder
Since the binaryPI glue code is specific to a binary interface, but not
for a hardware block, move it out of the common blocks directory. This
also brings the binaryPI support in line with the FSP support which is
used on the newer generations. This also drops the
SOC_AMD_COMMON_BLOCK_PI Kconfig option and makes use of the already
existing SOC_AMD_PI Kconfig option instead.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I014e538f2772938031950475e456cc40dd05d74c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-24 15:47:59 +00:00
Felix Held c0982abf86 soc/amd/common/block: move binaryPI S3 block into PI block
The code in soc/amd/common/block/s3 is specific to the AMD binaryPI
coreboot integration, so move the code to soc/amd/common/block/pi. This
drops the SOC_AMD_COMMON_BLOCK_S3 Kconfig option and integrates the
dependencies and selections into the SOC_AMD_COMMON_BLOCK_PI Kconfig
option. Since only selecting SOC_AMD_COMMON_BLOCK_PI but not
SOC_AMD_COMMON_BLOCK_S3 resulted in missing functions in the linking
process, we don't lose support for any working configuration by only
having one Kconfig option for both parts.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib2bd99a88d8b05216688bc45d9c4f23a007ce870
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57883
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-24 15:47:44 +00:00
Casper Chang 8fcefd3f6f soc/intel/alderlake: add MaxDramSpeed config
This change add MaxDramSpeed for variants usage to config dram speed.

Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: Iba0fae0ab4ff0121dc63af792458492eeb21ec2b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57866
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-24 15:27:43 +00:00
Tyler Wang 28e2945ab1 mb/google/dedede/var/magolor: Add ssfc codec DA7219 support
Add DA7219 codec support in maglet.

BUG=b:198239769, b:196193562
TEST:emerge coreboot

Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: I52d980ed611b3fbe4892cd3e65e3b35931feaba5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57696
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-24 14:32:33 +00:00
Nico Huber e28eeb713d util/abuild: Run `make .xcompile` only once
If abuild called itself recursively, the file already exists and we can
spare us one evaluation of all the makefiles per recursive abuild run.

Change-Id: Id3e2239354ec251c24c03c971987586deeb026c5
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-09-24 14:32:07 +00:00
Michael Niewöhner 90fcffb416 kconfig_lint: restrict definition of defaults for choice elements
Defining defaults for symbols used inside choices is not allowed. Add a
check for this, so we can drop the existent, overly restrictive checks
in the follow-up change.

Change-Id: I45bce2633dbd168fceb81ceae9b68621b28526e8
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57715
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-09-23 22:25:53 +00:00
Felix Held dea4e0fe68 soc/amd/common/blocks/include: rename gpio_banks.h to gpio.h
This brings the AMD SoC GPIO code in line with the Intel SoC code and
removes the not really needed suffix.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie2dbec81dfe503869beb2872b01a7475e2b88b33
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57842
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-23 18:33:00 +00:00
Felix Held 2876e4f49a soc/amd/common/blocks: rename gpio_banks folder to gpio
This brings the AMD SoC GPIO code in line with the Intel SoC code and
removes the not really needed suffix.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3dfcca2f126eb49c962b5cc32cbcf72e04f3f170
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57841
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-23 18:31:53 +00:00
zhixingma ef8654554f mb/intel/adlrvp_m: Enable HECI1 communication
The patch enables HECI1 interface to allow OS applications to communicate
with CSE.

TEST=Verify PCI device 0:16.0 exposed in the lspci output

Signed-off-by: zhixingma <zhixing.ma@intel.com>
Change-Id: Ifd338345caa183f03097f1003080992da70296ff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57813
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2021-09-23 16:40:47 +00:00
Felix Held 7011fa1135 soc/amd: rename program_gpios to gpio_configure_pads
Use the same function name as in soc/intel for this functionality. This
also brings the function name more in line with the extended version of
this function gpio_configure_pads_with_override which additionally
supports passing a GPIO override configuration.

This might cause some pain for out-of-tree boards, but at some point
this should be made more consistent, so I don't see a too strong reason
not to do this.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I88852e040f79861ce7d190bf2203f9e0ce156690
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57837
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-23 14:42:03 +00:00
Felix Held 05df6ec844 soc/amd,intel/common/include/gpio: improve documentation of overrides
Explicitly point out that gpio_configure_pads_with_override will ignore
GPIOs that are only in the override configuration, but not in the base
configuration.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1bdfcac89b81fef773938133a2699897c6ee9415
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57836
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-23 14:41:30 +00:00
Mark Hsieh a9a0b331c6 mb/google/brya/variants/gimble: Update DPTF sensors
Add two thermal sensors for fan and charger for DPTF based thermal
control.

BUG=b:199180746
TEST=USE="project_gimble emerge-brya coreboot" and verify it builds
without error.

Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I1529dd5dff3445dd499ed665386a9b06d67c7028
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57833
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-23 14:39:46 +00:00
Mark Hsieh 3673a16546 mb/google/brya/variants/gimble: Update audio setting
Add vmon-slot-no,imon-slot-no and dsm_param_file_name in overridetree.cb

BUG=b:197701952
TEST=build and check SSDT

Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: Ie646360c4ebbf25762b374c5bc3ef2017989fb2f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57832
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-23 14:38:51 +00:00
Patrick Georgi b0d87f753c util/crossgcc: Update gcc to 11.2
Various fixes to gnat and the improved nds32 backend have been merged
into gcc by now, so we don't need to carry those patches anymore.

Change-Id: Icdee2a8beedd109ee1f0eef6f32f7accbf66674b
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54050
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-09-23 08:37:39 +00:00
Reka Norman e4cf38ed36 util/spd_tools: Remove old lp4x and ddr4 versions of spd_tools
The migration to the new unified version of spd_tools is complete, so
the old lp4x and ddr4 versions can be removed.

BUG=b:191776301
TEST=None

Signed-off-by: Reka Norman <rekanorman@google.com>
Change-Id: I6b1fc297739efc8dc7d7eec64956bf3343984604
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57822
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-23 07:51:38 +00:00
Reka Norman 8f690dd762 util/spd_tools: Sort platforms_manifest entries by set number
Ensure that the order of entries in each platform manifest is consistent
every time spd_gen is run.

BUG=b:191776301
TEST=Run spd_gen for lp4x and ddr4, check that the manifests are
unchanged.

Change-Id: I7bfea65c8fc781df80a8725c0cf20c7547c857e8
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57773
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-23 07:51:22 +00:00