Commit Graph

23799 Commits

Author SHA1 Message Date
Nick Vaccaro c8f0a6c31a mainboard/google/zoombini: consolidate SPD makefiles
- consolidate commonality in meowth and zoombini's SPD makefiles into
  a common zoombini/spd/Makefile.inc
- move all SPD hex files into zoombini/spd directory
- move SPD_SOURCES definitions to variants/$(VARIANT_DIR)/Makefile.inc

BUG=b:69011806,b:71776625
BRANCH=master
TEST=Verify 'emerge-meowth coreboot' and 'emerge-zoombini coreboot'
compile and boot successfully.

Change-Id: I2291ebaf0ef5da1b22eb0e8fa7af8dbb50848c29
Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org>
Reviewed-on: https://review.coreboot.org/23874
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-28 17:38:47 +00:00
Kane Chen c3892c8fa8 skylake: Fix unwanted disablement of ACPI UPWE
In PORTSC, Port Enabled/Disabled(PED) is RW1CS.

When there is a USB device attached on system, current UPWE method
will set 1 to PED, this will cause port disabled as it's RW1CS.

This change is inspired by xhci_port_state_to_neutral in linux driver.
It will mask all RO and RWS bits and set WDE and WCE.

BUG=b:70777816
TEST=System won't be awakend from s3 automatically when usb devices
     is attached. Also system can be awakend by hotplugging usb
     devices under S3.

Change-Id: Ifd4c2d6640fea538e0ac71d7c5e73ab529e94f42
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/23848
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-28 17:37:57 +00:00
Crystal Lin e099b30964 mb/google/poppy/variants/nami: Enable elan touchscreen
BUG=b:72062694
BRANCH=master
TEST=Verify touchscreen on nami works with this change.

Change-Id: Iaec71a11121b3d2849f12d18cda0e506be2ace09
Signed-off-by: Crystal Lin <crystal_lin@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/23872
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-28 17:36:56 +00:00
Ravi Sarawadi 3c2310d2df mb/google/octopus: Add LPDDR4 memory init
Add LPDDR4 initialization support.

BUG=b:73136980
BRANCH=None
TEST=Build coreboot for Octopus board.

Change-Id: Ieffcfa2f9d075eb0be13562f1a0c7ee503b005d9
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-on: https://review.coreboot.org/23832
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-28 17:36:37 +00:00
Furquan Shaikh 51700313f5 soc/intel/skylake: Add support to print ME version
This change adds a boot state callback to print ME version after
DEV_ENABLE is complete. Information is printed only if UART_DEBUG is
enabled because talking to ME to get the firmware version adds ~1
second to boot time.

TEST=Verified on Soraka that ME version printed is correct.

Change-Id: I360d5d7420950d5aa255df08be6d7123621b87a8
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/23857
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-28 02:19:02 +00:00
Arthur Heymans d2d2aef6a3 sb/intel/{bd82x6,ibexpeak}: Move RCBA macros to a common location
Many generations of Intel hardware have identical code concerning the
RCBA.

Change-Id: I33ec6801b115c0d64de1d2a0dc5d439186f3580a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-02-27 09:46:29 +00:00
Marc Jones 5fd1d5ad12 soc/amd/stoneyridge: Refactor northbridge resource allocator
The resource allocator was overly complicated due to porting
from a multi-node resource allocator. It had some assumptions
about the UMA memory and where it would be located. The
refactored allocations account for UMA being reserved above 4GiB.

TEST=Check CBMEM table has correct RAM regions.

Change-Id: I722ded9fb877ec756c3af11fcb5fea587ac0ba8e
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/23819
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-26 18:18:21 +00:00
Marc Jones 932b5bdb6d soc/amd/common: Save the UMA settings from AGESA
Save the UMA base and size settings returned by AGESA
in amdinitpost();

Change-Id: Id96cc65582118ad41d397b1a600cab1615676a55
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/23818
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-26 18:18:07 +00:00
Nick Vaccaro ab2618d488 mainboard/google/zoombini: enable 4 cores
BUG=b:70731385
BRANCH=master
TEST='emerge-meowth coreboot chromeos-bootimage', flash
image.serial.bin to meowth board, boot into kernel, and
verify 4 cores are running.

Change-Id: Ia233e41acd19b317f82433a5d41d84ea934a66c4
Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org>
Reviewed-on: https://review.coreboot.org/23839
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-26 15:07:56 +00:00
Richard Spiegel bd65480593 src/arch/x86/smbios.c: Fix type 17 part number
Some DIMMs have invalid strings when it comes to device part number
(bytes 0x149-0x15c). From DDR4 SPD specs it should be ASCIIZ with unused
space filled with white spaces (ASCII 0x20). Byte 20 should be 0 (ASCIIZ),
all others should be ASCII.

Create a test that detects invalid strings and replace invalid
characters with *. If a replacement was made the output string then must
be <Invalid (replaced string)>.

BUG=b:73122207
TEST=Build, boot and record serial output for kahlee while injecting
different strings to dmi17->PartNumber. Use code to examine SMBIOS,
while testing different valid and invalid strings.
Remove string injection before committing.

Change-Id: Iead2a4cb14ff28d263d7214111b637e62ebd2921
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-26 15:06:58 +00:00
Richard Spiegel 99fd08d324 soc/amd/common/block/pi/amd_late_init.c: Fix part number
Kahlee DIMM have invalid string when it comes to part number
(bytes 0x149-0x15c). We currently force a NA string, but grunt has the
proper strings. Just let the string go through, and a second commit
within smbios.c will be responsible for testing the string and taking
proper action.

BUG=b:73122207
TEST=Build, boot and record serial output for kahlee while injecting
different strings to dmi17->PartNumber. Remove string injection before
committing.

Change-Id: I427262873f9ec80f459245e5f509e28a68de3074
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23825
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-26 15:06:36 +00:00
Vanessa Eusebio 3ca534f302 MAINTAINERS: Update INTEL FSP DENVERTON-NS SOC & HARCUVAR CRB Maintainers
* Add David, Jeff, and Shine
* Remove Fei

Change-Id: I2803af80ac8c2b1d04ecd125c0cb123e736cdf7e
Signed-off-by: Vanessa Eusebio <vanessa.f.eusebio@intel.com>
Reviewed-on: https://review.coreboot.org/23847
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mariusz Szafranski
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2018-02-26 15:06:10 +00:00
Furquan Shaikh 8389fe6da3 ec/google/chromeec: Remove extra newline characters from printk
This change removes extra newline characters from print statements for
wake masks.

Change-Id: I13cde76bfb0f10b1dda8117c27f2891e909f9669
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/23858
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-26 15:05:08 +00:00
Werner Zeh 5ea714acce mb/siemens/mc_bdx1: Avoid dereferencing a NULL pointer
Coverity scan has found an error where a NULL pointer is dereferenced.
The bug would happen if the devicetree does not contain a valid entry
for PCA9538. In this case the code
 * if (dev->path.i2c.device == PCA9538_SLAVE_ADR)
would dereference to a NULL pointer.

This patch fixes this issue. Thanks coverity!

Found-by: Coverity (CID 1386126: Null pointer dereferences (REVERSE_INULL))
Change-Id: I75e271d86c16fa3938420c43575ebba910f6a2fd
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/23808
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-26 05:35:58 +00:00
Zhongze Hu 12f656ced7 mb/google/fizz: Enable PCIe port 11, 12
Our CFM daughter card would like to use individual PCIe lanes for two
different devices on the card.

dlaurie@ has reconfigured PCIe port 9-12 from 1x4 to 1x2 + 2x1 on b2b
connector on fizz to meet the requirement:
https://chrome-internal-review.googlesource.com/571936
We also need to enable the ports on device tree.

BUG=b:72523836
TEST=none
BRANCH=fizz

Change-Id: Icded9850d833752680e0174b6c476e657817b319
Reviewed-on: https://chromium-review.googlesource.com/923867
Commit-Ready: Zhongze Hu <frankhu@google.com>
Tested-by: Zhongze Hu <frankhu@google.com>
Reviewed-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/924860
Commit-Queue: Shelley Chen <shchen@chromium.org>
Tested-by: Shelley Chen <shchen@chromium.org>
Signed-off-by: Zhongze Hu <frankhu@chromium.org>
Reviewed-on: https://review.coreboot.org/23845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
2018-02-23 22:04:41 +00:00
Julien Viard de Galbert 4ecd42f9b5 console: Introduce a way for mainboard to override the loglevel
This change adds a config option to allow mainboard to override
the console loglevel. When the option is set, the platform has
to define the function get_console_loglevel returning a valid
loglevel value.

This allows a mainboard to sample a GPIO to switch the loglevel
value between different environments (qualification vs production)
without re-flashing.

Change-Id: Id6cc72b8fe5c4c50a6f83ce80e6440b078eec6e2
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/23712
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-02-23 08:44:59 +00:00
Richard Spiegel 8f825e0cd0 mb/google/kahlee/mainboard.c: Fix mainboard_picr_data
While programming interrupts, a message "perhaps this device was defined
wrong?" shows up twice. This is caused because some devices have
interrupt programmed for APIC mode, but not for non-APIC mode. Fix
mainboard_picr_data table by identifying devices programmed with value
0x1F while programmed differently on mainboard_intr_data table. Do so
only for devices that are used by kahlee or interrupt required by old OS.

BUG=b:70788755
TEST=Build and run kahlee, Verify that message disappears from serial
output.

Change-Id: Ic285036290519ed3ee617dffa616bd26c61575c5
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23716
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-22 20:27:09 +00:00
Justin TerAvest f6106718a8 mb/google/kahlee: Use GPIO macros for baseboard
This commit uses newly defined macros to make it easier to read which
iomux function pads are being configured to use.

TEST=Booted grunt, confirmed display backlight came on.
BUG=b:72875858

Change-Id: I24e5091fc7ef696f8e9c932ce04664e6cc3ccb90
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-22 17:16:51 +00:00
Justin TerAvest bf0a67f3ee soc/amd/stoneyridge: Add readable macros for GPIO
This commit defines a set of macros for defining GPIO configuration that
are easier to read than the raw iomux function values used today.

TEST=None
BUG=b:72875858

Change-Id: Ie100c8494c565afa28fa44d78ff73155fc8c7ea8
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23828
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-22 16:35:10 +00:00
Justin TerAvest 36b568ce7c mb/google/kahlee: Correct bad gpio entry
There's no need to set the output enable here; this is already handled
by the native function. I'm making this correction in this change to
prevent the GPIO pin descriptions from getting confusing.

BUG=b:72875858
TEST=Booted, confirmed S5_MUX_CTRL high with and without this change.

Change-Id: I9e047be7169586c59892ef2bdab915683feeebda
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23829
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-22 16:27:36 +00:00
Lijian Zhao 2e81f394cf mainboard/google/meowth: enable PCH iSCLK
Turn on PCH iSCLK for meowth platform.

BUG=None
TEST=Boot up into OS and check register programming with iotools, the
command is iotools mmio_read32 0xfdad8000, returned value is 0x03.

Change-Id: I1e44e3748c9b37c8f60adcc47a866d445d77cfaa
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/23368
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-22 10:11:00 +00:00
Arthur Heymans fc31e44e47 device/ddr2,ddr3: Rename and move a few things
In order for ddr2.h and ddr3.h to be included in the same file it
cannot have conflicting definitions, therefore rename a few things and
move some things to a common header.

Change-Id: I6056148872076048e055f1d20a60ac31afd7cde6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23717
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2018-02-22 10:07:53 +00:00
Martin Roth 13089b008f Update chromeec submodule to upstream master
Updating from commit id 9fb10386a: 2017-06-21 04:19:06 -0700
(Poppy: Configure camera PMIC to low power mode.)

to commit id 927b64a0b: 2018-02-15 00:10:45 -0800
(meowth: zoombini: enable CONFIG_CMD_PD_CONTROL)

This brings in 1205 new commits.

Change-Id: I3f7a1ceb1ea8c70d57a8f067023358b93df2670b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/23480
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-22 10:03:22 +00:00
Martin Roth fd75e55fea mainboard/google: Disable big, pit, and ryu ec builds
The EC builds for nyan_big, peach_pit, and smaug (ryu) have been removed
from the latest EC codebase, so don't try to build them by default
anymore.

Change-Id: I53901b32753c5b9b050f517bbf3f10b9071913d4
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/23826
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-22 10:03:10 +00:00
Richard Spiegel 7b89a28149 util/amdfwtool/amdfwtool.c: Check fstat return
Funtion fstat will return -1 if there's any error, 0 if successful.
Check that fstat return is equal to 0, print error message and exit if
not 0.

This fixes CIDs 1353018 and 1353020

BUG=b:72062481
TEST=Build no errors

Change-Id: I83284d9125c75a29471f213f88b9181d5edba2e6
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23827
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-22 09:59:40 +00:00
Lijian Zhao 51605e2c9e soc/intel/cannonlake: Clear EMMC timeout register
Clear EMMC timeout register to avoid EMMC issue according to cannonlake
bios writer guide.

BUG=b.71586766
TEST=Install OS into EMMC successfully on meowth P1 platform.

Change-Id: I39e927a2c312c94561213f9f7c3319dcafa426b9
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/23831
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-02-22 09:59:03 +00:00
Lijian Zhao 9672b54087 soc/intel/cannonlake: Add emmc/sdc port id
EMMC and SD Controller port id listed here, the port id definition came
from Cannonlake BIOS Writer Guide 570374.

BUG=None
TEST=None

Change-Id: I901e90c47b08bb013fcfee5def610e320a7ac19a
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/23789
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-02-22 09:58:39 +00:00
Sathyanarayana Nujella 206821ee2f mainboard/google/zoombini: Add config for meowth audio
Add NHLT and dt support for meowth with max98373 amp.

BUG=b:71724897
TEST='emerge-meowth coreboot' compiles correctly
TEST=check SSDT and verify entries for max98373
TEST=check NHLT ACPI tables included blobs for max98373

Change-Id: Ic89bf669c7ab2ef39ce64e4da6a57a7069ee75f9
Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/23334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2018-02-22 09:57:30 +00:00
Lijian Zhao 416ded8dc1 soc/intel/cannonlake: Add more HDA Audio Link settings
Since FSP version 7.x.11.43, more HDA Audio link options are exposed,
so included that into coreboot. Users can modify that base on platform
implementations.

BUG=None
TEST=Boot up with debug build version FSP and check the debug print
result on meowth platform.

Change-Id: Ib2a75f554ddf9919a62c78a162ec1b9e602f1f5d
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/23400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2018-02-22 09:57:12 +00:00
Subrata Banik e83d057c3e soc/intel/cannonlake: Add provision to make CSME function disable in SMM mode
TEST=lspci from Chrome OS shows CSME device is not visible over PCI tree.

Change-Id: I3e0a5b00758a4ce42f2f190748c293c5ce07390c
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23824
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-22 09:56:37 +00:00
Subrata Banik f9eaede518 soc/intel/common/block/smm: Add option to have SOC specific SMI Handler at finalize()
This patch ensures common code provides an option to register a
SOC specific SMI handler before booting to OS (specifically during ramstage).

Change-Id: I50fb154cc1ad4b3459bc352d2065f2c582711c20
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23810
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tung Lun Loo <tung.lun.loo@intel.com>
2018-02-22 09:56:12 +00:00
Subrata Banik 736a03fd24 soc/intel/common/block/pcr: Add function for executing PCH SBI message
This function performs SBI communication

Input:
 * PID: Port ID of the SBI message
 * Offset: Register offset of the SBI message
 * Opcode: Opcode
 * Posted: Posted message
 * Fast_Byte_Enable: First Byte Enable
 * BAR: base address
 * FID: Function ID
 * Data: Read/Write Data
 * Response: Response

Output:
 * 0: SBI message is successfully completed
 * -1: SBI message failure

Change-Id: I4e49311564e20cedbfabaaceaf5f72c480e5ea26
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23809
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-22 09:55:50 +00:00
Subrata Banik 5f1da55b49 device: Include devicetree in SMM stage
Allow bootblock to get access to the entire static device tree
as other stages can access independently.

TEST=SMM code now can access devicetree.cb variables.

Change-Id: I59537c16f0a459e48d8b1efb5c1b196302f13381
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-22 09:55:19 +00:00
Patrick Georgi a5baccfd03 skylake: remove legacy devices from ACPI
Once the FADT reports that they don't exist it makes no sense to have
them in ACPI's device tree.

Change-Id: Ice82f0de592b6ca955148479fecc8506a7cdcddc
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reported-by: dhaval.v.sharma@intel.com
Reviewed-on: https://review.coreboot.org/23835
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.corp-partner.google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-22 09:54:07 +00:00
Furquan Shaikh 95b4d0c25d soc/intel/skylake: Do not set ACPI_FADT_LEGACY_DEVICES
SKL/KBL PCH does not support legacy devices. This change removes the
setting of ACPI_FADT_LEGACY_DEVICES flag in FADT for SKL/KBL.

It helps Linux kernel to disable controllers required to support legacy 
devices only e.g. i8237 DMA controller.

BUG=b:72679357

Change-Id: Ie2a85a719997157f52b0eab7254689f5a56ba05b
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/23833
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.corp-partner.google.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-22 09:54:00 +00:00
Chris Ching 97ab880082 mainboard/google/kahlee: Add tis_plat_irq_status
For variants that have a cr50 tpm, this enables faster polling when
interacting with the tpm.

BUG=b:72838769
BRANCH=none
TEST=verified on grunt that irq is used and not timeouts for tpm

Change-Id: I5786d334b6c1cc70f4c7107c75b07a7e27ac4428
Signed-off-by: Chris Ching <chingcodes@chromium.org>
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/23626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-21 23:36:22 +00:00
Chris Ching 2269a3c328 soc/amd/stoneyridge: Add functions for GPIO interrupts
Add a function to configure interrupt settings for a GPIO.  This does
not currently configure GEVENT signals.

The second function returns the GPIO interrupt status and clears the
flag if set.

BUG=b:72838769
BRANCH=none
TEST=Update and test interrupt settings for GPIO_9 on grunt

Change-Id: I1addd3abcb6a57d916b1c93480bacb0450abddf2
Signed-off-by: Chris Ching <chingcodes@chromium.org>
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/23624
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-21 23:36:11 +00:00
Julien Viard de Galbert 235daa4bf6 driver/uart: Introduce a way for mainboard to override the baudrate
The rationale is to allow the mainboard to override the default
baudrate for instance by sampling GPIOs at boot.

A new configuration option is available for mainboards to select
this behaviour. It will then have to define the function
get_uart_baudrate to return the computed baudrate.

Change-Id: I970ee788bf90b9e1a8c6ccdc5eee8029d9af0ecc
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/23713
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-02-21 16:09:06 +00:00
Marc Jones fa650f5e8c soc/amd/stoneyridge: Add UMA save function
Save the UMA values from AGESA to use in resource
allocation in ramstage.

Change-Id: I2a218160649d934f615b2637ff122c36b4ba617e
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/23817
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-21 16:08:45 +00:00
Arthur Heymans 950332b6e4 driver/spi: Warn when probed SF size differs from CONFIG_ROM_SIZE
Some assumptions are made with respect to CONFIG_ROM_SIZE being the
actual size of the boot medium, e.g. when automatically creating an
fmap with and RW_MRC_CACHE region. With this patch the user is
warned when this is detected.

Change-Id: Ib5d6cc61ea29214d338d4c52ff799d6620a9cac7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23695
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-20 23:21:20 +00:00
Jonathan Neuschäfer 7be74dbb38 nb/x4x/raminit_ddr2: Refactor clock configuration slightly
The result is shorter and (IMHO) more readable code.

Change-Id: Ic51c05d7aa791250d775bd7a640213065d4caba0
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23710
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-20 23:20:34 +00:00
Gaggery Tsai cb304c1d85 mb/google/poopy/variants/nami: Add Pmax setting
This patch adds the Pmax setting in device tree. The Pmax is from
MAX(PL4_sku1, PL4_sku2, ..) + ROPmax. Given ROPmax is 30W and
the maximum PL4 is from U42, hence the Pmax = 71W + 30W = 101W.

BUG=b:72138778
BRANCH=None
TEST=USE=fw_debug emerge-nami chromeos-mrc coreboot chromeos-bootimage
         & ensure the Pmax value is passed to FSP-S.

Change-Id: Ief6a134dc5b6bd2b8e07b4a44450e99ff26402d9
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/23640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-20 23:18:50 +00:00
Richard Spiegel 9b3da9fc57 mb/google/kahlee/OemCustomize.c: Disable bank interleave
AmdInitPost returns AGESA_WARNING. This is because AGESA by default
enables bank interleaving, while the HW does not meet the requirements
for it. Disable bank interleaving, thus clearing AGESA_WARNING.

BUG=b:73118857
TEST= Build and run kahlee. Search for "agesawrapper_amdinitpost()
returned AGESA_SUCCESS".

Change-Id: Ice9270f9b10051dbb622344919223cf5439f5d7b
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23763
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-20 23:18:10 +00:00
Jonathan Neuschäfer 5268b76801 src/soc: Fix various typos
These typos were found through manual review and grep.

Change-Id: I6693a9e3b51256b91342881a7116587f68ee96e6
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-02-20 23:17:39 +00:00
Jonathan Neuschäfer e33f120cb8 payloads/external/GRUB2: Build only for supported architectures
GRUB2 doesn't support all architectures that coreboot supports.
Furthermore, coreboot's build script for GRUB2 doesn't support all of
these architectures.

Let the user select GRUB2 only when building for x86 and ARM, which are
known to work.

Change-Id: I5ef2020b2acb4cd008a57a2372734674f8b84a36
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-02-20 23:16:05 +00:00
Jonathan Neuschäfer 3934198418 mb/compulab: Mark Intense-PC as single board computer in board_info.txt
Based on the pictures at http://www.fit-pc.com/web/products/intense-pc/,
the Intense PC does not look like a laptop. In its documentation it is
described as "mini-PC" or "Single Board Computer".

This patches moves the Intense-PC into the correct category on the
Supported Motherboards page.

Due to thermal considerations, I have not removed the "select
SYSTEM_TYPE_LAPTOP" in Kconfig.

Fixes: de7f8d3a19 ("mainboard/compulab: add support for CompuLab Intense-PC")
Change-Id: I4343306a2f82eed8211981cbd3b084f5d112d30b
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23707
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-20 23:15:12 +00:00
Jonathan Neuschäfer 3af80a9377 util: make-spike-elf.sh: Fix busybox mktemp compatibility
Busybox mktemp does not support patterns with any characters after the XXXXXX
part. Drop the .o extension to make make-spike-elf.sh work on Alpine Linux.

Change-Id: I2e37ceef115c6d4d31eb617558481b2284dada83
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-20 23:14:06 +00:00
Jonathan Neuschäfer 61864143d4 arch/riscv: Delegate the page fault exceptions
These exceptions were new in the Privileged Architecture spec 1.10.
We need to delegate them to S-mode.

Change-Id: Iec15afe9656107b9aeea1677c5b8dc7d654fa746
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-02-20 20:46:53 +00:00
Jonathan Neuschäfer a5c49b8d43 arch/riscv: Update encoding.h and adjust related code
Update encoding.h to the version shipped with spike commit
0185d36 ("Merge pull request #165 from riscv/small_progbuf"),
and copy the license header from the LICENSE file.

Change-Id: I517042e5865986e88a589dc8623745f8d584d6b8
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23773
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-02-20 20:46:39 +00:00
Jonathan Neuschäfer 042a8336f3 arch/riscv: Pass the bootrom-provided FDT to the payload
The RISC-V boot protocol foresees that at every stage boundary (bootrom
to boot loader, boot loader -> OS), register a0 contains the Hart ID and
a1 contains the physical address of the Flattened Device Tree that the
stage shall use.

As a first step, pass the bootrom-provided FDT to the payload,
unmodified.

Change-Id: I468bc64a47153d564087235f1c7e2d10e3d7a658
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23797
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-02-20 20:46:12 +00:00