make it clearer why they are disabled (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2978 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- Use 'static' where appropriate.
- Use 'const' where appropriate.
- Indentation fixes.
- Add comment wrt init code which is only valid for VT8237R.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2974 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Reason: The existing code does not tell us why it sets the watchdog
clock at all, but since it appears in cache_as_ram_auto.c instead of
the usual place (Config.lb) there has to be some meaning to it.
Simply do what the proprietary bios does: Use the external clock source.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ward Vandewege <ward@gnu.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2973 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This enables us to have only one configuration and one set of code for
all revisions of the Gigabyte GA-M57SLI-S4.
Flash is now setup correctly for both SPI and LPC flash.
Detection of SPI flash in flashrom on rev. 2.x boards now hangs
instead of failing. However, that is just an effect of the combination
of incomplete initialization of the SPI controller and paranoid checks
in the flashrom SPI code.
If anyone wants to work on that, he needs a logic analyzer or creative
imagination. Hint: LPC-to-SPI read passthrough, clock signal.
Remaining issues for the M57SLI: Fan/environment control.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Harald Gutmann <harald.gutmann@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2972 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
iasl now defaults to put created files into the input file's path, not into the
current directory.
This (trivial) patch fixes the behavior for the northbridge specific ASL code.
Further checkins to be expected.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2968 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Attached is a patch that enables AMD Geode CS5536 chipset support. I
have tested it successfully on a MSM800 board from digital logic.
Signed-off-by: Lane Brooks <lbrooks@mit.edu>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2967 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Upon incoming SMAF message from CPU (C3 or FID/VID change), the SB will
assert SLP# which is connected to LDTSTOP_L on K8 CPUs. Question is for how
long. Imho for 100us. Which is more than plenty (2us required) I will try
to justify this once I know what bios to set in SB.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2965 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
a delay of 10 us after entering ID mode and this was insufficient for
the 29C020. The data sheet claims we have to wait 10 ms, but tests have
shown that 20 us suffice. Allow for variations in chip delays with a
factor of 2 safety margin.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2962 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
the other supported 440BX boards.
Fix up totally b0rked static device tree in Config.lb.
Drop useless and duplicated failover.c, use global one.
Make CPU init actually work (result: massive speed-up).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2960 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
it to 8X transfer rate (up to 1066 MB/s) similar code placed here would be
needed for VT8237A/S etc. Using VIA recommended values despite they are for
K8T890CF, this is K8T890CE (still dont know what is exactly different).
This patch enables the parity error reporting on V-Link, so it enables NMI
generation for the SERR# errors. The NMI may not be generated, maybe port
61h needs some tuning too.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2958 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Small cosmetic fixes (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2956 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
With this patch, flashing the parallel EEPROM on board revisions 1.x
finally works. Flashing the serial EEPROM of board revisions 2.x is just
one patch away.
Torsten Duwe says:
Flash erase on my board was failing reliably. Now it works!
Andreas B. Mundt says:
For the first time I was able to write with flashrom and LB.
$flashrom -Vv --write linuxbios.rom
[...]
Vendor ID: GIGABYTE, part ID: m57sli
Found chipset "NVIDIA MCP55", enabling flash write... OK.
[...]
SST49LF040B found at physical address 0xfff80000.
Flash part is SST49LF040B (512 KB).
LinuxBIOS last image size (not ROM size) is 4096 bytes.
Manufacturer: GIGABYTE
Mainboard ID: m57sli
This firmware image matches this motherboard.
Programming page: 0007 at address: 0x00070000
Verifying flash... VERIFIED.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Torsten Duwe <duwe@lst.de>
Tested-by: Andreas B. Mundt <andi.mundt@web.de>
Tested-by: Torsten Duwe <duwe@lst.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2955 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
PIRQ table to make most devices work. Random small fixes (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2953 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Fix IRQ tables (Thanks to Marc Jones)
Fix IRQ SLOT #
Comment out ram test in early startup.
make the debug print in lx/raminit.c a debug print, not emerg print
Set the default console log level to 3, but leave in the possibility of
running with more info (leave maximum at 11)
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2952 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
i82801xx code for the following parts:
- AC97 audio/modem
- Onboard network interface cards (NICs)
- USB 1.1 controllers
- SMBus controllers
Some other parts are still missing and will be added later.
Use PCI ID #defines from pci_ids.h everywhere. Constify various structs.
Also, fix some random cosmetic issues in the code.
All of this is relatively trivial and tested by manually building
all boards which currently use the i82801xx code.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2951 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
ARRAY_SIZE() can be used on ROMCC-dependent systems. Also adds stdlib.h
to vt8237r_early_smbus.c, so it'll build on those systems.
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2949 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
and c7 init are identical, according to the datasheets, so there's no
need for another folder. As the comment says, some of these model IDs
may never be produced, but they are reserved by Via for the c7.
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2948 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
(ICH/ICH0 up to the ICH9 family) in preparation for further
code improvements for the i82801xx southbridge code.
Small fixes in the 6300ESB PCI IDs.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2947 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
that board. Shift PCIe pin numbers downwards, and PCI int pins upwards.
This puts both PCI slots' int A and PCIe 16x int A into the right
position.
Signed-off-by: Torsten Duwe <duwe@lst.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2946 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Remove dead code
* Remove unused variables
* Fix bug where array was one element too small
* Fix error value truncation, the old code never entered the error path
* Remove warnings
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2945 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Rudolf's suggestion making the symbol weak is elegant, but let's allow
some more discussion.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2944 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
have PCIe MMCONFIG.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2941 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
ICH5/ICH5R (more to follow) in preparation of further 82801xx improvements.
Use human-readable names for the PCI ID #defines.
Rename *_ISA to *_LPC as per datasheet.
The 82801DBM only has 3 (not 4) USB devices, looks like a copy-paste error.
The fixes in southbridge code are only to keep the build working for now,
any real improvements will only go into the 82801xx code in future.
This is abuild-tested so it shouldn't break anything.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2938 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
the Jetway J7F2 patch that should be coming soon, and also moves most
defines into vt8237r.h. I've changed some of the values from u32 to u8,
because that's all they should ever need to be. Also includes
doxygenized comments!
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2937 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
MMCONFIG for memory mapped PCIe config.
However this patch is not enough to enable it on Linux, Linux do not trust
BIOSes too much, so a small patch to kernel to disable the check if this
region is e820 reserved.
PCI: BIOS Bug: MCFG area at e0000000 is not E820-reserved
PCI: Not using MMCONFIG.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2936 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2935 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2934 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
No functional code changes.
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2932 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2. Rename sisnb.c to sis761.c
3. Delete many mis-definition for sis device in
src/include/device/pci_ids.h
4. Trim trailing spaces for all files
Signed-off-by: Morgan Tsai <my_tsai@sis.com>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2931 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Ulf Jordan