be required for a series of later patches. Roughly it contains:
* fixed SMBus driver (was not compiled in before)
* fixed S-ATA/P-ATA combination
* Added warnings to drivers being called with a NULL dev->chip_info
* Set subsystem ids for those boards that have none specified in Options.lb
* Fix license headers. The code was originally released under GPL v2 but
some files sneaked in with a v2 or later header.
* some attempts to fix azalia/Intel HDA.. not working yet
* clean up and fix pci bridge handling code
* Add Config based GPI handling to LPC driver
* Add HPET enable function
* Enable clock gating where appropriate
* first attempt at USB debug console support (not working yet)
* Add required options to kontron board
* many other minor changes
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3991 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
a problem with IRQ 9, but besides that Linux is happy. BSOD in Windows still.
changes by file:
src/mainboard/tyan/s289X/Options.lb:
Add options and defaults for ACPI tables and resources.
src/mainboard/tyan/s289X/mainboard.c:
Add high_tables resource ala Stefan's code for the Kontron.
src/mainboard/tyan/s289X/acpi_tables.c:
Fill out the ACPI tables, using existing code where possible.
Only the madt is different between the boards, to be combined later.
src/mainboard/tyan/s289X/Config.lb:
Compile in acpi_tables.c and dsdt.dsl.
Turn on the parallel port and the real-time-clock.
src/mainboard/tyan/s289x/dsdt.dsl:
The board layout (thanks Rudolf) and interrupts from mptable.c
src/mainboard/tyan/s289x/mptable.c:
Minor formatting changes to make them diff better.
src/superio/smsc/lpc47b397/superio.c:
Correct the size of the real-time-clock so it can be where it belongs.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Rudolf Marek <r.marek@assembler.cz>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3989 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
changes by file:
src/northbridge/amd/amdk8/northbridge.c:
Add high tables code ala Stefan's code for the i945.
src/southbridge/nvidia/ck804/ck804_lpc.c:
Enable High Precision Event Timers.
Add pm_base for ACPI.
src/southbridge/nvidia/ck804/ck804_fadt.c:
Since fadt is only dependent on the Southbridge, add it here.
src/southbridge/nvidia/ck804/Config.lb:
Compile in ck804_fadt.c
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3988 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
whitespace differences between this file and the amdk8_util.asl from
asus/m2v_mxe.
It also enables SLIT filling if you have one, zeroes the unused fields in the
srat_lapic structure, and adds some declarations in acpi.h.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Rudolf Marek <r.marek@assembler.cz>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3986 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
The microcode is from Intel's Linux microcode file, so it's unproblematic.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3983 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
horribly broken and thus never used by any platform. This needs to get
straightened out so current chipsets drivers can use the full feature set.
Create wrapper functions similar to the io pci config space ones.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3981 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
doesn't make no sense. (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3977 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
with nonzero PCI bus operations, get_pbus() will get stuck in a silent
endless loop.
Detect the endless loop and break out with an error message.
Such a situation can happen if the device tree is not yet
initialized/walked completely.
This fixes the unexplainable hang if pci_{read,write}_config{8,16,32}was
used in early mainboard code for the AMD DBM690T. Instead, the code will
now die() with a meaningful error message.
Thanks to Ward Vandewege for testing my patches to track down that bug.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3972 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
The attached patch fixes this. I did not spotted that because the return arg is
moved just outside of method and I have overseen the closing }
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3968 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Rudolf Marek <r.marek@assembler.cz>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3967 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
sense, too). Have one u64 instead of three.
In order to use the old bios emulator, you have to do nothing. (Default, if
CONFIG_PCI_ROM_RUN is enabled)
In order to use yabel in your target, you need to add the following lines to
your config:
uses CONFIG_PCI_OPTION_ROM_RUN_YABEL
default CONFIG_PCI_OPTION_ROM_RUN_YABEL=1
In order to use vm86 in your target, you need to add the following lines to
your config:
uses CONFIG_PCI_OPTION_ROM_RUN_VM86
default CONFIG_PCI_OPTION_ROM_RUN_VM86=1
Note: vm86 only works on platforms with _RAMBASE in the lower megabyte.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Joseph Smith <joe@settoplinux.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3965 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
a long time ago. This will make it easier to port v2 boards forward to v3 at
some point (and other things)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3964 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
similar to what v3 does. This is required to have two source files with
the same name but in different directories. (As in, two different SuperIOs on
board, with a superio.c each)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3961 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
(in addition to their low locations)
This adds the kontron 986LCD-M and the i945 as a sample.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3960 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
removes the ugly binary DSDT patching and all other related stuff. Stick to
infrastructure in previous patch.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3955 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This patch converts mainboard_$VENDOR_$BOARD_ops to mainboard_ops and
mainboard_$VENDOR_$BOARD_config to mainboard_config.
Ron's part:
The config change that makes the naming change not break every build.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3954 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Add TOM2 to the K8 DSDT.
Thanks to Rudolf Marek for testing and fixing this patch.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3953 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
K8 and Fam10+ CPUs.
What this patch does:
1. Enable SSE (to get some more registers to play with)
2. Determine CPUID, and stash it in an XMM register, and reference
value for comparison in another XMM register (mangled somewhat to
simplify inequality comparisons)
3. Add a macro jmp_if_k8, which jumps if the CPU is K8
(using an SSE compare)
4. Replace #if CAR_FAM10 sections with runtime checks using jmp_if_k8.
This is pretty mechanical work. The macro uses local labels
(1: and 2:) to prevent namespace issues
5. At one time, CPU_ADDR_BITS is used to fill a register. This is
replaced with hardcoded values for both cases, and switched
appropriately.
6. Disable SSE
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3951 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- make uma_memory_base and uma_memory_size uint64_t as they may be 64bit BARs
on some platforms.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3949 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Bellongs to r3947
Following patch adds dynamically generated P-States infrastructure as well as
M2V-MX SE as example how to do that. It is based on AMD code and mine code for
ACPI generation.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3948 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Following patch adds dynamically generated P-States infrastructure as well as
M2V-MX SE as example how to do that. It is based on AMD code and mine code for
ACPI generation.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3947 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
M2V-MX SE as example how to do that. It is based on AMD code and mine code for
ACPI generation.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3946 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
The company is dead.
It causes builds to fail, and that is not a problem we need to have.
Removing it to remove the problems it causes.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3945 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
If high SMM memory is used (and needs to be uncached for whatever reason; it
shouldn't in my opinion), we should do it the same way.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3942 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
clause.
An ITE87427 Super I/O does not exist. Use the real name (IT8712F) of
the chip on the DBM690T board.
Use decimal values for KELV, THOT and TCRT on the Pistachio board for
better readability.
Tested by Maggie Li on DBM690T and Pistachio.
Tested by Carl-Daniel Hailfinger on Asus M2A-VM.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3939 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Fix reference to documentation.
Use __FUNCTION__ instead of hardcoding function names in printk
messages.
No functional changes.
I'm slowly getting to the point where adding another RS690 board is
really easy and needs almost no changes to the existing target.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3938 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Reorder HDA (HD Audio) init:
The reordering was based on what order things happen in the BIOS
Developers guide, RPR, and SATA driver. I fixed the order of the devices
that didn't matter to clean up the change log.
1. Enable the Chip
2. Setup the SMBus registers
3. Setup the Device Registers
4. Look for Codec
5. Init Codec
The codec init was changed to match the description in the RRG pg 235.
Mem Reg: Base + 08h Bit 0. There were unneeded things happening.
Added 1ms delay to match the BKDG while waiting for BAR+0xe to set its
bits.
Signed-off-by: Dan Lykowski <lykowdk@gmail.com>
Tested on AMD DBM690T and AMD Pistachio by Maggie Li. Works.
Tested on Asus M2A-VM by Carl-Daniel Hailfinger. Improves the situation,
but some warnings remain.
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3930 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
new AML code generator. Compile-tested on all changed targets. I think it should
work because it works for Asus M2V-MX SE.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3929 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
if I did not made any mistake.
Works for mine CPU ;)
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3928 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
generate run-time ACPI ASL code.
Moreover it demonstrates its use on Asus M2V-MX SE where the SSDT table is
generated by new function k8acpi_write_vars (technically similar to
update_ssdt). But lot of nicer.
x
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3925 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
functional changes, only a little bit of (mostly formatting) cleanup to
make merging easier.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3924 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
