Commit Graph

38775 Commits

Author SHA1 Message Date
Angel Pons bb19d39487 sb/intel/x/smbus.c: Rename parameter
This is for consistency among the various southbridges.

Change-Id: Id0dcfeef6e220861212ce665201ce8cd31f3b054
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48362
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-12-10 15:54:37 +00:00
TingHan.Shen be404c22aa soc/mediatek/mt8192: Init SSPM
SSPM is "Secure System Power Manager" that provides power control in
secure domain. The initialization flow is to load SSPM firmware to
its SRAM space and then enable.

Signed-off-by: TingHan.Shen <tinghan.shen@mediatek.com>
Change-Id: Ia834852af50e9e7e1b1222ed1e2be20e43139c62
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47786
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-10 14:05:27 +00:00
Huayang Duan 916e2efad4 soc/mediatek/mt8192: Init DPM
DPM is a hardware module for DRAM power management and for better
power saving in low power mode.

BUG=none
TEST=Boots correctly on Asurada

Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Change-Id: I16b341ad63940b45b886c4a7fd733c1970624e40
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46393
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-10 14:04:59 +00:00
Tan, Lean Sheng 344f68be10 mb/intel/ehlcrb: Add EHL CRB memory initialization support
Update memory parameters based on memory type supported by
Elkhart Lake CRB:

1. Update spd data for EHL LPDDR4X memory
   - DQ byte map
   - DQS CPU-DRAM map
   - Rcomp resistor
   - Rcomp target
2. Add configurations for vref_ca & interleaved memory
3. Add EHL CRB on board LPDDR4X SPD data bin file
4. Update mainboard related FSPM UPDs as part of memory
   initialization

Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: Ifd85caa9ac1c9baf443734eb17ad5683ee92ca3b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-12-10 10:49:15 +00:00
Tan, Lean Sheng ed42c7ef51 mb/intel/ehlcrb: Update ehl_crb device tree
Update Elkhartlake CRB devicetree devices based on EHL EDS.

Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: I88097ced03f4376f309487b9d5207473f77742ef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48124
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-12-10 10:48:58 +00:00
Tan, Lean Sheng 7d83309eb2 mb/intel/ehlcrb: Remove JSL sku id info in SMBIOS
Remove JSL specific SMBIOS sku id info as it is not required by
EHL.

Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: Ib672eb456ba62f2eb7f941630c4fbb34823664f5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48123
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-10 10:48:36 +00:00
Tan, Lean Sheng 1ec9284e14 mb/intel/ehlcrb: Remove IPU & MIPI related support from EHL CRB
THis patch removes IPU & MIPI related support from EHL CRB as they
are not supported in EHL.

Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: I3eb038009daaabd048f40c7953cb2c111cd4fe63
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-12-10 10:48:25 +00:00
Tan, Lean Sheng 170f2edadb mb/intel/ehlcrb: Remove board ID detection via EC
Since there is no EC support on EHL CRB, this patch removes board
ID detection via EC (board_id.c & board_id.h) and its related
files. Temporarily removes variant_memcfg_config function in
romstage_fsp_param.c, will be added back when updating memory
configs later.

Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: I40d96285dc05ec5faabc123950b6b3728299e99a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48121
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-10 10:48:11 +00:00
Tan, Lean Sheng d0789cd6f0 mb/intel/ehlcrb: Remove ChromeOS EC related headers
Since EHL CRB does not support ChromeOS, this patch removes
ChromeOS EC related headers (ec.h & gpio.h) and #includes.

Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: I9c0c3722065c041769081f3d564646ce6a565a9b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48119
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-12-10 10:48:02 +00:00
Tan, Lean Sheng 64d749d863 mb/intel/ehlcrb: Remove ChromeOS EC support from smihandler
Since there is no ChromeOS support for EHL CRB, drop smihandler.c
which just deals with ChromeOS support.

Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: Id474c3b04a82c03dda6514cc4565b58fb790b9c1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-12-10 10:47:52 +00:00
Tan, Lean Sheng b5fed68ab9 mb/intel/ehlcrb: Remove ChromeOS support from mainboard
Since ChromeOS is not officially supported for EHL CRB, removing
ChromeOS related codes. Here are the change details:

- Remove ChromeOS related kconfig switches, including
  SOC_INTEL_CSE_LITE_SKU which has dependency on ChromeOS flag
- Remove chromeos.c file
- Remove ChromeOS dsdt related codes from dsdt.asl & mainboard.c
- Remove ChromeOS GPIO related codes from variants.h & gpio.c

Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: I4aabd40a4b46d4e64534b99e84e0523eaeaff816
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48117
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-12-10 10:47:39 +00:00
Tan, Lean Sheng 1057106db8 mb/intel/ehlcrb: Add missing 'include <console/console.h>'
"Die()" needs <console/console.h>, as per this patch:
https://review.coreboot.org/c/coreboot/+/45540

Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: I0f9fae4a1e43477ca8e78ebbebd8c0729f8b7668
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48116
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-10 10:09:22 +00:00
Tan, Lean Sheng d2afd87b0d mb/intel/ehlcrb: Add initial mainboard code
This is a initial mainboard code cloned entirely from jasperlake_rvp
aimed to serve as base for further mainboard check-ins.

This patch is based on TGL_upstream series patches:
https://review.coreboot.org/c/coreboot/+/37868

List of changes on top off initial jasperlake_rvp clone:
1. Replace "Jasperlake" with "Elkhartlake"
2. Replace "jsl" with "ehl"
3. Replace "jslrvp" with "ehlcrb"
4. Remove unwanted SPD file, add empty SPD as placeholder
6. Empty romstage_fsp_params.c, to fill it later with SOC specific
   config
7. Empty GPIO configurations, to be filled as per board
8. Empty memory.c configurations, to be filled as per board
9. Add board support namely BOARD_INTEL_ELKHARTLAKE_CRB
10. Replace jslrvp variant with ehlcrb variant

Changes to follow on top of this:
 1. Add correct memory parameters, add SPDs
 2. Clean up devicetree as per tigerlake SOC
 3. Add GPIO support
 4. Update ehl fmd file to replace 32MB chromeos.fmd

Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: I2cbe9f12468318680b148739edec5222582e42a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47707
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-12-10 10:09:13 +00:00
Tan, Lean Sheng b89ce115da soc/intel/elkhartlake: Fix EHL mainboard build fail errors
When EHL initial mainboard patch is uploaded, there are some build
errors caused by EHL soc codes. Here are the fixes:
1. include gpio_op.asl to resolve undefined variables in scs.asl
2. remove unused variables in fsp_params.c
3. rearrage sequences of #includes to fix build dependency of
   soc/gpio_defs.h in intelblocks/gpio.h
4. add the __weak to mainboard_memory_init_params function
5. add the missing _len as per this patch changes
   https://review.coreboot.org/c/coreboot/+/45873

Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: Idaa8b0b5301742287665abde065ad72965bc62b3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47804
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-10 10:01:20 +00:00
Patrick Rudolph 40dc53a1a1 cpu/x86/64bit/exit32.inc: Don't invalidate cache in CAR
Change-Id: I4a4e988d38b548e1c88ffcc5f5ada2e91ff6ba91
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-12-10 07:30:56 +00:00
Patrick Rudolph 547e5572cf arch/x86/smbios.c: Fix compilation on x86_64
Change-Id: I07780f9a6fa577d7b6bb63884071a7e1ce1bdbfa
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48454
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-12-10 07:25:43 +00:00
Patrick Rudolph d147d43617 drivers/crb/tpm: Fix compilation on x86_64
Change-Id: I19cce90f44b54e4eb6dd8517793ae887f0bd1e22
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48453
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-12-10 07:25:23 +00:00
Yidi Lin f4bf8f5fab soc/mediatek/mt8192: Load MCUPM firmware and boot up MCUPM
MCUPM is the MediaTek proprietary firmware for MCU power management.

TEST=1. emerge-asurada coreboot chromeos-bootimage;
     2. See following log during booting.
        load_blob_file: Load mcupm.bin in 35 msecs, size 115668 bytes
     3. Test suspend/resume by:
        a. suspend (on DUT): powerd_dbus_suspend
        b. resume (on host): dut-control power_state:on

Change-Id: I50bea1942507b4a40df9730b4e1bf98980d74277
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46392
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-10 03:22:54 +00:00
Roger Lu a5f472bf57 soc/mediatek/mt8192: add spmfw loader
This patch adds support for loading spm firmware from cbfs to spm sram.
Spm needs its own firmware to enable spm suspend/resume function which
turns off several resources such as DRAM/mainpll/26M clk when linux
system suspend.

BUG=b:159079649
TEST=suspend with command `powerd_dbus_suspend` and
     wake up the DUT by powerkey

Signed-off-by: Roger Lu <roger.lu@mediatek.com>
Change-Id: I6478b98f426d2f3e0ee919d37d21d909ae8a6371
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-12-10 03:22:36 +00:00
Yidi Lin eb69dd60ef soc/mediatek/mt8183: Use mtk_init_mcu to init SSPM
Use mtk_init_mcu API to load and run sspm firmware.

TEST=emerge-kukui coreboot

Change-Id: I63c4b99342bdebb2a94cbf0c6380b0a6817853e7
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-12-10 03:22:24 +00:00
Yidi Lin c221d56478 soc/mediatek/mt8183: Add DRAM_DMA section
mtk_init_mcu uses DRAM_DMA section as CBFS buffer.
The change "mediatek/mt8183: Remove DRAM_DMA section" is reverted
for using mtk_init_mcu.

On mt8173 and mt8192, this region is used by DMA hardware and is
marked as non-cacheable resource. On mt8183, this region is reserved
as CBFS buffer, so it is not necessary to be marked as non-cacheable
resource.

Change-Id: I7ce9f68883e2787ee7f3c5066f4c47c5ca315633
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48232
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-12-10 03:22:01 +00:00
Yidi Lin 7ba3775114 soc/mediatek/common: Add common API for loading firmwares
Add mtk_init_mcu to load the firmware to the specified memory address
and run the firmware. This function also measures the load time and the
blob size. For example:

mtk_init_mcu: Loaded (and reset) dpm.pm in 15 msecs (14004 bytes)

Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Change-Id: Ie94001bbda25fe015f43172e92a1006e059de223
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46930
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-12-10 03:21:19 +00:00
Michael Niewöhner 6bc1296cbd mb/supermicro/x11ssm-f: enable AER for PCIe root ports
Follow vendor and enable Advanced Error Reporting for PCIe root ports.
This enabled the Linux AER driver, which handles PCIe error conditions.

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I9d9b5afca0ca891e2812445db1d42a46ba16199e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48369
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-10 02:27:53 +00:00
Michael Niewöhner 0bae5a72c5 mb/supermicro/x11ssm-f: add subsystem ids to PCI ports and devices
Add the subsystem ids to PCI ports and devices, which were dumped on
vendor firmware using `lspci`.

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: Idb36c5c72e1b0b8303439ae5dce772822f551d2d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48368
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-10 02:27:40 +00:00
Michael Niewöhner fb7a06b5b7 mb/supermicro/x11ssm-f: enable LTR for all root ports
Follow vendor and enable LTR on all root ports to optimize for devices'
latency requirements and also optimize power management while preventing
failure due to wrongly guessing idle states, which happens without LTR.

Tested successfully. No errors show up in dmesg.

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I8f72087c71e291d2412dc7b3e16ee7f419e2ca0c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48367
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-10 02:27:08 +00:00
Michael Niewöhner ffa2f4fb35 mb/supermicro/x11-lga1151-series: drop HAVE_ACPI_RESUME
All X11 boards currently supported have Intel SPS without support for
S3/S5. Thus, drop it from Kconfig.

Note: not all X11 boards are server boards. When a X11 desktop or
workstation board should be added, this can be selected by the boards,
where S3/S5 work.

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: Ie75c9217078d38c42eba2b30c078b8bb1c2ca694
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48366
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-10 02:26:58 +00:00
Michael Niewöhner f105c4164e mb/supermicro/x11ssm-f: (re)configure unconnected pads
Correct unconnected pads that are configured different currently by
copying vendor configuration while porting the board.

Add internal pull resistors to all unconnected pads, that do not have an
external pull resistor, to prevent floating.

The pads have been determined by dissecting a dead board. This commit
only changes pads, that are not connected at all and don't have any via,
so we can be absolutely sure there is no other connection.

Change-Id: I991fe270b42f430f7447712236e0f80b3d5bba2a
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-10 02:26:22 +00:00
Michael Niewöhner 7f623f8e46 mb/supermicro/x11ssm-f: (re)configure and document various pads
(Re)configure various pads found by dissecting a dead board and vendor
firmware, as well as the BMC firmware:

- GPP_B14: input connected to jumper JBR1 - could be used to implement
  "BIOS Recovery" ("Top-Block Swap") functionality; external pull-up

- GPP_C20: output to BMC alert CPU_THROTTLED# - can be used to notify
  the BMC about a thermal throttling event. Not implemented in vendor
  firmware.

- GPP_C23: input connected to the CPU's CATERR# output; external pull-up
  Not actively used by vendor firmware.

- GPP_D1: output connected to on-board and front panel power LEDs

- GPP_D18: output connected to PERST# of both CPU PCIe Slots. Can be
  used for testing/debugging only, since it resets both slots at once.
  Not actively used by vendor firmware.

- GPP_D19: output connected to PERST# of both PCH PCIe Slots. Can be
  used for testing/debugging only, since it resets both slots at once.
  Not actively used by vendor firmware.

- GPP_D22: input connected to the BMC enable/disable jumper JPB1; Will
  be used later in CB:48096 and CB:48097; external pull-up

- GPP_G0 - GPP_G3: dedicated/integrated CPU switching; probably not
  useful, since the IGD is not connected to any ports on this board.
  External pulls ensure correct function of a dGPU even without driving
  the gpios. Not used by vendor firmware.

- GPP_G12 - GPP_G16: inputs for binary SKU_ID; external pulls

- GPP_G20: PWRFAIL# input from JPI2C1 (pin 3); external pull-up; Not
  used by vendor firmware.

Also add comments for documentation. While at it, mark ME-owned pads as
reserved.

Change-Id: I9f9328e9ce6f7e291b171f776bb98bc617b64b93
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
2020-12-10 02:25:13 +00:00
Felix Held 5d7fa16c5c soc/amd/picasso/reset: use port and bit defines from cf9_reset.h
The register name and the name of one bit are slightly different, but
have the same functionality.

Change-Id: I025f1c7b2c7643afe245f2275ae6ef45e64b951a
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48487
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-10 01:22:06 +00:00
Felix Held 1e63e361c6 soc/amd/picasso/reset: remove leftover PCI includes
On Stoneyridge some PCI registers were accessed in this compilation
unit, but on Picasso this is no longer the case.

Change-Id: Ifbf65f9724a14d4847af98930759c865453775b4
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48486
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-10 01:21:53 +00:00
Xi Chen 63eb64be26 Makefile.inc: Fix empty output when processing C struct files in CBFS
When passing $(@) to eval command, $(@) is replaced by empty string,
Also, the $(@) in cbfs-files-processor-struct is a temporary file name,
so we should quote it by an extra '$' or use the arg ($1 or $2)
directly.

For example:
  cbfs-files-processor-struct= \
      $(eval $(2): $(1) $(obj)/build.h $(KCONFIG_AUTOHEADER); \
		# **  $(@) is empty string instead of $(2)   **
		printf "    CC+STRIP   $(@)  \n"; \
		# **  $(1) contains the name of source file  **
		printf "    CC+STRIP   $(1) \n"; \
	......)

Signed-off-by: Xi Chen <xixi.chen@mediatek.com>
Change-Id: Id6a66e25d7dfe8fe6410e517593ed22a438d2f82
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48201
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-09 23:18:10 +00:00
Sheng-Liang Pan 5c08c31775 mb/google/volteer/variant/volta: add Synaptics touchpad.
add new Synaptics touchpad for volta.

BUG=b:174802144
TEST=emerge-volteer coreboot and check touchpad function work.

Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: I7fc8d08b8b2229ca9252618f159fc9c6f91f9d7f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48395
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-09 21:54:40 +00:00
Felix Held 10252035ce soc/amd/cezanne: print APU family and model in bootblock_soc_init
Change-Id: I457188c905167affc1ebcea835a36df822ecb23c
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48476
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-09 18:44:51 +00:00
Felix Held 153f92adbe soc/amd/cezanne: add basic early FCH initialization to bootblock
Change-Id: I1c6d32a5498a7adcee3c8c3145f85e9dba26bf7e
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48475
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-09 18:44:40 +00:00
Felix Held 4be064a1d8 soc/amd/cezanne: add common SMBus code to build
Since the IOAPIC in the FCH gets set up in the SMBus code, also select
IOAPIC in Kconfig.

Change-Id: I4163e28ca9e68e5fd36421d90aafc20bce43a174
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48474
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-09 18:42:59 +00:00
Julius Werner 34cf073220 cbfs: Allow mcache to be found after the first lookup
This patch addresses the same problem as CB:48429, but hopefully this
time correctly. Since the mcache is not guaranteed to be available on
the first CBFS lookup for some special cases, we can no longer treat it
as a one-time fire-and-forget initialization. Instead, we test
cbd->mcache_size to check if the mcache has been initialized yet, and
keep trying on every lookup if we don't find it the first time.

Since the mcache is a hard requirement for TOCTOU safety, also make it
more clear in Kconfig that configurations known to do CBFS accesses
before CBMEM init are incompatbile with that, and make sure we die()
rather than do something unsafe if there's a case that Kconfig didn't
catch.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I4e01e9a9905f7dcba14eaf05168495201ed5de60
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48482
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-09 17:44:52 +00:00
Julius Werner d2777b8485 Revert "cbfs: Skip mcache in post-RAM stages before CBMEM is online"
This reverts commit b652aaef99. It was
dumb and didn't actually fix anything.

Change-Id: I074135dd12face1226105e0706c78ae8ecba18e0
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48481
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-09 17:44:28 +00:00
Felix Held 4911c3e352 soc/amd/cezanne: call bootblock_main_with_basetime in bootblock_c_entry
Change-Id: Iaac661fcb7581236ace4b5bf057b3e70289f1c8b
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48473
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-09 17:42:08 +00:00
Felix Held 0645347d0b soc/amd/picasso,stoneyridge: drop unused BIOSRAM offset defines
The two Socs don't use this functionality and biosram.c in the common
code is the only place where those defines are used, but it doesn't
include soc/iomap.h and has its own definitions instead.

Change-Id: I973df4ab39a94e89ea2ed6ffb639c5a85b8df456
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48470
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-09 15:28:12 +00:00
Raul E Rangel f56b784227 soc/amd/picasso: Rename SD_EMMC_EMMC_DDR_52 to SD_EMMC_EMMC_DDR_104
The number at the end actually means the max MiB/s. So 52 MHz clock @ 8x
data width, sampled on each clock edge = 104 MiB/s.

According to JEDEC Standard No. 84-B51A (JESD84-B51A), maximum bandwidth
& clock frequency for various MMC bus speed modes are (at x8 bus width):
MMC_Legacy: 26 MB/s at 26 MHz Single Data Rate (SDR)
MMC_HS: 52 MB/s at 52 MHz SDR
MMC_DDR52: 104 MB/s at 52 MHz Dual Data Rate (DDR)
MMC_HS200: 200 MB/s at 200 MHz SDR
MMC_HS400: 400 MB/s at 200 MHz DDR

BUG=b:159823235
BRANCH=zork
TEST=build zork

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I7818d8cb5ed5974c60a900477a0aa2ecc904db0c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48309
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-09 14:25:19 +00:00
Kyösti Mälkki b3621f811d soc/amd: Remove Kconfig BOOTBLOCK_ADDR
Due the location of X86_RESET_VECTOR, the anchor point
for linking the bootblock is at the end, which equals
ROMSTAGE_ADDR.

Change-Id: I2d25911582393c9a10fd3afa1a484eda2604d95a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-09 14:23:43 +00:00
Kyösti Mälkki 8d187f4d22 soc/amd: Remove Kconfig X86_RESET_VECTOR
The architectural requirement is for the address to be
located at the end of bootblock -0x10 bytes, so the
definition was redundant with other Kconfig variables.

Change-Id: Ia014470cfadf0b401a12a2de6dce3b1fc1862137
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-09 14:23:31 +00:00
Srinidhi N Kaushik 8dcd62d705 soc/intel/common/dmi: Add support for locking down SRL
This change adds support to lock down the DMI configuration
in dmi_lockdown_cfg() by setting Secure Register Lock (SRL)
bit in DMI control register.

BUG=b:171534504

Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I98a82ce4a2f73f8a1504e5ddf77ff2e81ae3f53f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48258
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-09 14:23:22 +00:00
Srinidhi N Kaushik 876b422641 soc/intel/common/dmi: Move DMI defines into DMI driver header
Move definitions of DMI control register and Secure Register
Lock (SRL) bit into common/block/dmi driver header file.

BUG=b:171534504

Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: Iefee818f58f399d4a127662a300b6e132494bad0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48257
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-09 14:23:15 +00:00
Furquan Shaikh 640f0ce93f mb/google/volteer: Reorganize FMAP
This change reorganizes FMAP for volteer to make use of the lower
16MiB of the SPI flash for RW_SECTION_A and RW_MISC in addition to
RW_LEGACY. This is now possible because TGL supports memory mapping of
BIOS region greater than 16MiB.

Following changes are made in chromeos.fmd as part of this:
1. Move RW_SECTION_A and RW_MISC to lower 16MiB.
2. Reduce size of RW_LEGACY to 2MiB since we longer need to use it as
a placeholder in the lower half of the SPI flash.
3. Reduce size of RW_ELOG to 4KiB as coreboot does not support a
larger region for ELOG.
4. Increase WP_RO to 8MiB to allow larger space for firmware
screens. GBB size is thus increased to 448KiB.

BUG=b:171534504

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I0c3c0af94183a80c23d196422d3c8cf960b9d9f5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48187
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-12-09 14:23:06 +00:00
Furquan Shaikh ba75c4cc49 soc/intel/tigerlake: Enable support for extended BIOS window
This change enables support for extended BIOS window by selecting
FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW and providing base and size of the
extended window in host address space.

BUG=b:171534504

Cq-Depend: chromium:2566231
Change-Id: I039155506380310cf867f5f8c5542278be40838a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
2020-12-09 14:22:58 +00:00
Stanley Wu f078ce1e46 mb/google/dedede: Update Boten GPIO setting for PEN detection.
AP_PEN_DET_ODL isolated by a diode and need to pull up internally.

BUG=b:160752604
BRANCH=dedede
TEST=Build and confirm waveform by google EE parter.

Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: I85f3d0209094af07891a5c0cc218443da586e6e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48294
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-09 13:31:36 +00:00
John Su e1c7cd9fb7 mb/google/zork/var/vilboz: Update telemetry settings
Update telemetry settings.

VDD Slope : 32643 -> 26939
VDD Offset: 208   -> 125
SOC Slope : 22742 -> 20001
SOC Offset: -83   -> 168

BUG=b:171668654
BRANCH=zork
TEST=1. emerge-zork coreboot
     2. pass AMD SDLE test report

Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: Ic63e069310aa4a66cd4c9058790dbed37e6967f4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48288
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-09 10:19:23 +00:00
V Sowmya a6051440e2 mb/intel/adlrvp: Add PMC.MUX.CONx device config for Conn2
This patch adds the PMC MUX and CONx devices for adlrvp for
conn2.

BUG=b:170607415
TEST=Built and booted adlrvp. Verified the PMC.MUX CONx objects
in SSDT tables.

Change-Id: I52afbd429750cfa416f4ed93aeb1be590f8c3a5c
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48230
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-09 08:22:16 +00:00
Tim Chen 2082196e95 mb/google/dedede/var/metaknight: Support Elan/Synaptics touchpad
Add Elan and Synaptics touchpad settings.

BUG=b:169813211
BRANCH=None
TEST=build metaknight firmware

Change-Id: Ice0a86cd5610db269d44acb1d51cb652110d9b0c
Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47441
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raymond Wong <wongraymond@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-12-09 06:55:53 +00:00