There are 2 cores visible to the OS and both need to be
brought up. Therefore, provide the proper number of cores.
BUG=chrome-os-partner:31545
BRANCH=None
TEST=Built and noted CONFIG_MAX_CPUS=2.
Change-Id: I8a99891506af0fb3aa0284475c3c4be8bb69268b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: efa6c0343521dd98b86eacc94737f3497b721f95
Original-Change-Id: Id31b0a3046e40e1aec09bf2ee66b1e2f0b27fd21
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214661
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9006
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Increase TZ carveout region size to 4MiB. TTB lives in the first 1MiB of the
trust zone. Rest of the TZ memory can be used by el3 monitor.
BUG=chrome-os-partner:31615
BRANCH=None
TEST=Compiles successfully and boots to kernel
Change-Id: I448574860186815992c15a358a1481faecf224bd
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: de0f3f8016a4e566a2bacb967ef92213648d8257
Original-Change-Id: I1f25b7b119037cba7055a1bd61997f020a0b1010
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/214370
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9003
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
In order to more easily bring up the 2nd core refactor
the cpu startup logic. A common 32bit_entry.S is compiled
both for romstage and ramstage to provide the common 32-bit
entry point.
BUG=chrome-os-partner:31545
BRANCH=None
TEST=Built and booted ryu to the kernel. Also, can get the 2nd
core up out of reset.
Change-Id: I0c2c9f637189009767e8d5510732678c64e62a2a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7394b271bf67dfad8a601f41faaac8f07ae6d4a5
Original-Change-Id: Id810df95c53d3dc8b36d8bd21851d3b0006a8bc2
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/213850
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9001
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Instead of requiring the mainboards to know the magic
literals for the bus numbers provide an easier name to
number to handle all the weird ordering.
BUG=chrome-os-partner:31106
BRANCH=None
TEST=Built and booted on ryu.
Change-Id: I4a90f5f5f3ed1d936e2eee23f4726069adc49cc7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b028e90650384c947a3d0ee84c6d1346a22b22b9
Original-Change-Id: Id4d773d3049a43b186711900c61935ba7f3562ce
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/213491
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8996
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This provides are barebones initialization for tegra132 GIC
on CPU0. It routes all interrupts to CPU0, moves them all
into group 1, and attempts to allow non-secure access for
all registers (doesn't appear to be implemented, though).
BUG=chrome-os-partner:31449
BRANCH=None
TEST=Built and booted past smp init in the kernel. Timers
appear to be flowing now since jiffies are updated.
Change-Id: Id45c13cc23e50feed3d88da13420c9eb694498a0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 81bad0a53083baa7af0f1fd5f82fef0538ee62df
Original-Change-Id: I69dd9ae53f259e876a9bc4b9d7f65330150d2990
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/212795
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8995
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
In order to access secure device register space the cpu
needs to have the page tables marked as secure memory. In
addition the page tables need to live within secure memory
otherwise the accesses default to non-secure.
Therefore move the page tables to the trustzone region. Remove
the TTB_* config options as well as removing the TTB reservations
from coreboot's resource list.
BUG=chrome-os-partner:31355
BUG=chrome-os-partner:31356
BRANCH=None
CQ-DEPEND=CL:213140
TEST=Built and booted into kernel.
Change-Id: I1fc8dda932c36935f8523792bc1147f6b0743d11
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1522a83bb57e33749843d5b3ea5545ded97a3953
Original-Change-Id: Ia4b9d07ef35500726ec5b289e059208b9f46d025
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/213141
Reviewed-on: http://review.coreboot.org/8994
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
I2C6 has a special mux in the SOR/DC domain, so there's a ton
of devices that need to be clocked, SOR unpowergated, and then
the I2C6 muxing done in the DPAUX_HYBRID_PADCTL register.
BUG=none
BRANCH=none
TEST=none, built rush/ryu AOK
Change-Id: Ibeeda763b7fb30fabaee85d03fbf7d5efb42a30a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0b4da98e20a89b045f2d5b5033a27cd7ab855f35
Original-Change-Id: I4aaa74ef1b3009da621d1a2ef6f79de8ebf545e2
Original-Signed-off-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/212887
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8992
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Added distinct functions for clock_enable and clock_clear_reset,
and rewrote clock_enable_clear_reset() to use them. Useful when
unpowergating SOR partition, for instance, where we need to
enable a bunch of periph clocks, unclamp SOR, then take all of
those periphs out of reset.
BUG=none
BRANCH=none
TEST=none, built rush/ryu OK.
Change-Id: I92edf3104adc8eb7637c47a5e000788fd55f1452
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4fd76a6d0d0fb7922c6beacbc1cfcb365b6537b2
Original-Change-Id: I6fef5a72421cb4e3d7edb33a66f62b6e14865a32
Original-Signed-off-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/212916
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8991
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tegra132 has 2 different paths for booting and resuming from
sleep. The boot path uses the typical bootblock, romstage,
and ramstage. However, the resume path is completely orthogonal.
cbmem_initialize() attempts to recover the cbmem area, but
that functionality should not be used from romstage because
tegra132 is by definition in a fresh boot if it is executing
romstage. Therefore, use cbmem_initialize_empty() so that cbmem
is always initialized from scratch on each boot.
BUG=chrome-os-partner:31239
BRANCH=None
TEST=Built and ran on ryu. Was able to enter recovery and stay in
recovery without entering a reboot loop.
Change-Id: I0453c15e57a873a7ce7a63190dceafb75e4c9342
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 28ebc092e6721552c18db03e7578424c23a64b64
Original-Change-Id: I2016146fdc3aea493a78bab31ea8c8cbd78935c5
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/211424
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8990
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
1. Fixed some errors in selftest compare to reference.
2. Some WA steps for xhci in sleep trap is only for lpt.
BUG=chrome-os-partner:28234
TEST=compile ok, run selftest on auron to verify
boot to OS
BRANCH=None
Signed-off-by: Kane Chen <kane.chen@intel.com>
Original-Change-Id: Iaccb087581d5f51453614246bf80132fcb414131
Original-Reviewed-on: https://chromium-review.googlesource.com/215646
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Commit-Queue: Kane Chen <kane.chen@intel.com>
Original-Tested-by: Kane Chen <kane.chen@intel.com>
(cherry picked from commit 97761b4ad3073fff89aabce3ef4f763383ca5cad)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I2b1d5be4f8a13eb00009a36a199520cd35a67abf
Reviewed-on: http://review.coreboot.org/8971
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
some clock gating and pcie settings are missed in original code
BUG=chrome-os-partner:28234
BRANCH=None
TEST=build and boot on samus
verify registers between samus and crb
Original-Change-Id: I931276adb2f2667c4f9e7611acfd709b7232d492
Original-Signed-off-by: Kane Chen <kane.chen@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/214568
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
(cherry picked from commit 57e42c781d435092a08238461f0605dbf092e576)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ia62a50f28a411bbd2ba51b94de17ca70051ea093
Reviewed-on: http://review.coreboot.org/8967
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This can be used to know if HSIO registers need updating in ramstage
but it is not possible to query the ME for HSIO version after sending
the DRAM-init-done message.
BUG=chrome-os-partner:28234
BRANCH=samus
TEST=build and boot on samus, check for HSIO version messages in log
Original-Change-Id: Id6beeaf57287e8826b9f142f768636a9c055d7eb
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214259
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 637cbf5c1a1d922dab3f8a5cd4b3cd05617d1b92)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I29ce907804e892afde5f91e0b21688a50217cf13
Reviewed-on: http://review.coreboot.org/8966
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
This macro is incorrect and should be counting by dword instead of byte.
The effects of this were subtle: incorrect events in ELOG and hanging when
waking from USB input because PME_B0 was not disabled properly.
BUG=chrome-os-partner:31611
BRANCH=none
TEST=test wake from suspend with USB keyboard
Original-Change-Id: I7caf1d46283071787550a9765703897181774957
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214258
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 3cfc4a1812466cb1c1317b8f21321aafee623857)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I3e2f8190d824692ecb961615becf65319a6ffd8b
Reviewed-on: http://review.coreboot.org/8965
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
- The SATA CAP register setup was moved outside the refcode blob we run
so it needs to be set up by coreboot again...
- Slight tweak to fast ramp voltage for broadwell CPU
BUG=chrome-os-partner:25491
BRANCH=None
TEST=Build and boot on samus
Original-Change-Id: I7bdc0811ad8f28ab0912972036dca59d229b0173
Original-CSigned-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-CReviewed-on: https://chromium-review.googlesource.com/214024
Original-CReviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 5d166a0c4d206eaa885ecebaa0c3cefefdc59280)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Id58d3bee5e713139edf6e8fda8cdf4c48ba95bd1
Reviewed-on: http://review.coreboot.org/8964
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
This can be shared between mainboards, they are still free
to override if needed.
BUG=chrome-os-partner:28234
BRANCH=none
TEST=build and boot on samus
Change-Id: I85fae6e254adcbda1c52410d5ba046f3f05b54c0
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/213792
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 3e40cb804e7a95ce2183ebb3ef5d86820aef61b5)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/8961
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
The original code won't set power gating for disabled port correctly,
due to it must be set before Lock
BUG=chrome-os-partner:28234
BRANCH=None
TEST=build and boot on samus
verify bit 24, 26 is set in RCBA(0x3a84) for samus
Original-Signed-off-by: Kane Chen <kane.chen@intel.com>
Original-Change-Id: Id78d391ac657665a972cb4fd1810df6304a5a6ab
Original-Reviewed-on: https://chromium-review.googlesource.com/213561
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Tested-by: Kane Chen <kane.chen@intel.com>
Original-Commit-Queue: Kane Chen <kane.chen@intel.com>
(cherry picked from commit 066c8c81df8be9ae9ab7b33342a93b0b3ea7b240)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ic7c87b04863f93de5665d72e0f95b4105b1d4d3b
Reviewed-on: http://review.coreboot.org/8960
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
fixed a coding error and sync sata configuration with ref code
BUG=chrome-os-partner:28234
BRANCH=None
TEST=build and boot on samus
verify registers between samus and crb
Original-Change-Id: I09dd80a9772ac82b841363a540c9b7a8689e04a9
Original-Signed-off-by: Kane Chen <kane.chen@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/213137
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
(cherry picked from commit 0fbb59e3c5117a513ef19117560bb41dfe8c0d71)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I99a389b06f4ec077c298100ca878c68ef69debfa
Reviewed-on: http://review.coreboot.org/8959
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
This was a merge error when I was pulling in some of the
code into this file I put it after the read of CAP2 but
before it is modified and written back. In the end the
DEVSLP bits are getting set/cleared that need to but the
other bits in the register may be wrong. Also when enabling
devslp set the devslp-present bit in each enabled port.
Also remove much of the 0:1f.2@0x98 setup and the attempt
to write (the write once) CAP register that is already
being written in the reference code.
BUG=chrome-os-partner:28234
BRANCH=None
TEST=build and boot on samus
Original-Change-Id: I467f3c15b9f4d4c814ba0ef8baf95739b4bc6662
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/212308
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 9110a42982183b2954c865abbf18e008a39c997c)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I7db5c7ccf619aa28856388dd40f59495ef6d7e77
Reviewed-on: http://review.coreboot.org/8958
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
In order to prevent possible TPM lockout due to PLTRST assertion
shortly after powering up add a small delay before the reset.
This will affect cold power up only, reboot/resume/warmboot will
all have the flex ratio locked already so this reset is unneeded.
BUG=chrome-os-partner:29859
BRANCH=None
TEST=build and boot on samus. I tried unsuccessfully to trigger the
TPM lockout, but I was not able to do that consistently without this
patch so it is unknown yet whether this is 100% effective.
Original-Change-Id: Ief8c9261c0268b0f90a3022213ebd2b06633b481
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/211893
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 20413f2eafa144f5f381eb6f92d8b959415ca049)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I665e9ed1faa65e88d988660a24bdad40a4c5ab7e
Reviewed-on: http://review.coreboot.org/8957
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
TCO registers are 16bit not 32bit. Also do not log the
TCO reset event in S3 resume path to avoid it being logged
when TCO is not actually tripping.
BUG=chrome-os-partner:28234
BRANCH=None
TEST=manual:
1) build and boot on samus
2) modify kernel command line with nmi_watchdog=0
3) while sleep 1 ; do echo -n V ; done > /dev/watchdog &
4) fg 1
5) ctrl-Z
6) wait for reboot
7) check event log for TCO event
8) check suspend/resume path to ensure no TCO event logged
Original-Change-Id: I9cd8627de8498b280deb088f3a8e1e20546e2f96
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/211840
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 5952fe4672d07bd39e345f2048c2bfc510bf9f2a)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I6cdeffb8b50c5001d714edd3a1264cf117cd1ad6
Reviewed-on: http://review.coreboot.org/8954
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
- ADSP IRQ should be exclusive
- HDA should write reg 0x43 even if disabled
- A few clock gating tweaks based on ref code changes
- Move SATA clock gating to sata.c where SIR changes are done
- Add support for enabling Deep SX in AC/DC modes
- CLKREQ VR Idle for enabled PCIE ports
BUG=chrome-os-partner:28234
BRANCH=None
TEST=build and boot on samus
Original-Change-Id: Icece58e32b7a5d2b359debd5516a230cae3fd48c
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/211611
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit c0e22ba043ed96bdddca4989b2f29d0e989f6fef)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: If5f5e1666aa9660e31305ee6369f2febf6757b99
Reviewed-on: http://review.coreboot.org/8952
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Workaround for auto shutdown issue on broadwell SKU.
Now we can see C7 transition, and MRC fastboot
BUG=chrome-os-partner:29787,chrome-os-partner:29117
BRANCH=None
TEST=build ok and boot on samus
Original-Signed-off-by: Kane Chen <kane.chen@intel.com>
Original-Commit-Id: 932152b16c3943b00bd317e7370402dda451529f
Original-Change-Id: Id1f174b67fa3e6f248dd8b21aee25e6e01abf33e
Original-Reviewed-on: https://chromium-review.googlesource.com/210870
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Tested-by: Kane Chen <kane.chen@intel.com>
Original-Commit-Queue: Kane Chen <kane.chen@intel.com>
(cherry picked from commit 932152b16c3943b00bd317e7370402dda451529f)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ie9fb792635b39d33136cef576ae5559013d5947a
Reviewed-on: http://review.coreboot.org/8950
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Instead of using rela_time use the stopwatch API as the
semantics fit perfectly with the expiration usage.
BUG=None
BRANCH=None
TEST=None, but similar usage tested on tegra132.
Change-Id: I91ef59212a2dd1b48640b1aaaab6acacf4e9b3e6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b1dd8380f04641f4f73caa3441f349d9eca6be05
Original-Change-Id: Iff3293debc2f85553c9e9b765084e5c00720012c
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/219713
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8895
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Depending on the needs of the mainboard certain regions of the address
map may need to be adjusted. Allow for that.
BUG=chrome-os-partner:31293
BRANCH=None
TEST=With ryu patches able to insert a non-cacheable memory region.
Change-Id: I68ead4a0f29da9a48d6d975cd41e2969db43ca55
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 88342562885b09c4350ba1c846b725b5f12c63d9
Original-Change-Id: Iaa657bba98d36a60f2c1a5dfbb8ded4e3a53476f
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/212161
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8925
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
BUG=None
BRANCH=None
TEST=Built rush and ryu, ran on rush into recovery mode.
I2C6 is in the SOR domain, so a lot of further init is
needed before it can be used. A follow-on patch will do this.
Change-Id: I5701bfcf1d0bb8c6edd3d885b1b7dd14e67ba73a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 69908f2489d1a918bb109d43e713932214741b46
Original-Change-Id: I1160a182ee6e2b2b56479384efc6a9063590448f
Original-Signed-off-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/212671
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8940
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Continuing down the path of easing mainboard maintenance
provide a way to bring up the USB 2.0 ports through funit.
BUG=chrome-os-partner:31251
BRANCH=None
TEST=With ryu patch was able to get same sporadic USB communication.
Change-Id: Ic75821acf1d48a9f1659849fa007251c61658640
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5183c5081a95219f84c4d6dfca70926b383abc1a
Original-Change-Id: Iee5ca30b3c8b876a9cae7b91db096fef933a8412
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/212332
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8938
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
BUG=chrome-os-partner:31293
BRANCH=None
TEST=With non-cacheable memory region and dma range addition, booting from usb
reaches the same point as mmc.
Change-Id: I218c751f41fb881af4fed0bcccc378dde1fd07b4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a26e07b58f454c598bf5b7a4940c238135548bbd
Original-Change-Id: I1083f8de2bfbe9a233d317b29b8fc56f47c7061d
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/211039
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8937
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The clk_rst.h file wasn't including files that had
functionality it was using resulting in broken builds
if just this file was included.
BUG=None
BRANCH=None
TEST=Built with just this file included -> no more errors.
Change-Id: I229cb3890f1320edc3bc3e82469b301cbaff0f72
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 03b455aa9da64d6e110690206db65939ca023c27
Original-Change-Id: I8dc0fcab363e1089587e6dc8ff04c2a76c5e364c
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/212331
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8936
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Make sure the array size matches the number of supported
FUNITs. Also remove the FUNIT_NONE enumeration so that
there isn't an empty slot in the array at index 0.
BUG=chrome-os-partner:31251
BRANCH=None
TEST=Built when array wasn't large enough. Compiler threw an error.
Change-Id: I1b83ddff799a56ea39efa23a91dca1a9e0f10862
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4cbe74905bbeb815e9f20bcc0fad3751a3133b04
Original-Change-Id: I0bb37c51311d202729b7fb9731d6eec0a28dc040
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/212330
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8935
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
To provide easier access to the base addresses of the controllers
by funit identifier add the base addresses to the data structure.
BUG=chrome-os-partner:31251
BUG=chrome-os-partner:31106
BRANCH=None
TEST=Built.
Change-Id: I427d432beef36e6342c188d607c0e33b3845c0e1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c8f09e61e3dbfbc96980b98ad25e09554fd49a8d
Original-Change-Id: Iff5564b250dcf2038252d54a4caec3df5f7f3de7
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/212169
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8934
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Provide consistently named base address enumerations as well
as provide some that were missing.
BUG=chrome-os-partner:31251
BRANCH=None
TEST=Built.
Change-Id: I2551bbaa83d1d2c158b87d239098c22fba4d3961
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 07954a231f3c11c4102f9db0a2d35654abda208f
Original-Change-Id: I75030598f7da7dacf8e8eff1d7427c5bf202814f
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/212168
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8933
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
In order to prepare for USB initialization move the clock
configuration into a separate routine in the funit library.
BUG=chrome-os-partner:31251
BRANCH=None
TEST=Built and booted into recovery mode.
Change-Id: I090b5d12c5805f0179c29cfc62499fad2f245c01
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f7adaf969762b8296034f4373f550a902d1ed06b
Original-Change-Id: Iea6cd2fbe8369a91c06b15d94b63c409ae83124f
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/212167
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8932
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Just use direct pointers to the registers in the pre-filled
data structures. In 64-bit the sizes increase, but it's small.
The fields now directly point to the correct register so no
need to do any arithmetic to identify the correct register.
BUG=chrome-os-partner:31251
BRANCH=None
TEST=Built and booted on ryu into recovery.
Change-Id: I0de85c486c005aed23b6118ec91b45dd39acdfb0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 358b78c1c4cb72e0166f91b36011676e65576666
Original-Change-Id: I186bf5d145437472126067960e62d7ed6a25f295
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/212166
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8931
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Pull out the common usb setup utmip functions from t124 into tegra usb.h. These
can be reused for t132 as well.
BUG=chrome-os-partner:31293
BRANCH=None
TEST=Compiles successfully for nyan, big and blaze
Change-Id: Idddd40e409b56875436db6918d05f2889d83870b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 12f12cb30a033cce645f53457d13a987aeec22a1
Original-Change-Id: I83f83bafad0f52ad651fe5989430f41142803f2b
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/211200
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8927
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The high address field was being shifted in the wrong direction
resulting in the lower 12 bits of the upper address being dropped.
BUG=chrome-os-partner:30572
BRANCH=None
TEST=Was able to run on ryu and not hang while wiping memory.
Change-Id: If1d7ef1c63ce79c143af3c5012b206ee297cd889
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6b0da6fa391db2ec2bc1e0bec9325f4e74b5286c
Original-Change-Id: I7bf173bb0373d2d25ce9014c80236fb55cc8e17e
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/211941
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-on: http://review.coreboot.org/8923
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This api provides a common interface to initialize various clock sources,
dividers as well as enabling the clock for various functional units.
BUG=chrome-os-partner:31251
BRANCH=None
TEST=Compiles successfully for rush and boots till last known good point.
Change-Id: I2b8df5abf7301bc940315427af4cb38a635f07f8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9814f93a9f99fc9df6267167f991ebef427e9ae3
Original-Change-Id: I7abb193d6a9cfa448df1c48c346b4edbad802329
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/211765
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8921
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The current 2 boards were setting up clocks and enabling
peripherals that apply to the SoC generically. Therefore,
move the common pieces into the SoC code.
BUG=chrome-os-partner:31105
BRANCH=None
TEST=Built and booted through depthcharge on ryu.
Change-Id: I94ed4b5cc4fafee508d86eefe44cf3ba6f65dc3b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6dad573c8689b79bb4aa615811a10f44e7d8c809
Original-Change-Id: I6df1813f88362b8beaf1a716f4f92e42e4b73406
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/211191
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-on: http://review.coreboot.org/8917
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The original intent was to set the equivalent flags by default
for the PAD_CFG_* macros so as not to make the usage too chatty.
The GPIO_INPUT variant didn't have the PINMUX_INPUT_ENABLE field
set. Therefore, automaticaly set it for PAD_CFG_GPIO_INPUT().
BUG=chrome-os-partner:29981
BRANCH=None
TEST=Built and ran on ryu.
Change-Id: Iab058874314430de08010912c3fc758a98b73eb0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 535cdb354efc067caf32d32641846f11fb0cd2ee
Original-Change-Id: Ifb630601cf04d2984542933382aace16540863ad
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/211133
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8913
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The tegra132 SoC provides the monotonic timer API. Therefore,
ensure the reset of the coreboot infrastructure is aware.
BUG=None
BRANCH=None
TEST=Built and ran on Ryu. Noted that ramsgage is showing timings
for each bootstate.
Change-Id: Ifc2d5b7eb318ffac0ad79bfbc3d1b61a7ba4b10c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b691572c63a43a01a290f1c00f71097028d1415e
Original-Change-Id: I9b8fcf38cba9bdaaf0455701df1d6328bf1927c1
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/211132
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8912
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
coreboot already has a reset API. Utilize it by selecting
HAVE_HARD_RESET. The tegra132 boards have to provide the
hard_reset() implementation as that involves board-specific
bits. The tegra132 code then provides a cpu_reset() routine
that just promotes that call to a hard_reset().
For the existing tegra132 boards remove the unnecessary files
from the build.
BUG=chrome-os-partner:30784
BRANCH=None
TEST=Ensured hard_reset() does something on Ryu.
Change-Id: I6d5aa928fec95b361175e35e0a26812829ffdfc3
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 31edd4ff7486ded87d2525cd360d48959b6aef7c
Original-Change-Id: I1e1b014062dafb5d81fb9da40006c5405073a95d
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/211131
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8911
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The gpio_index_to_port() incorrectly was dividing by
GPIO_PORTS_PER_BANK on a value including the bit number. After
masking off the BANK offset just divide by the number of gpios
in a port to get the port offset.
BUG=chrome-os-partner:29981
BRANCH=None
TEST=Built and ran through to depthcharge. Printed bank, port, and
bit numbers for validation.
Change-Id: I3fbbb90f369bace90e787148a58795b7b1b40c1b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 97e1f830b4a8e948673433bfa6d81586204b6ee2
Original-Change-Id: I8bb50e922c9fd7c0a1c247ba95394f6deb9f1533
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/210909
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8908
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
I erroneously added GPIO_NONE_INDEX at the beginning of the
enum block effectively putting every GPIO index off by 1.
Instead, move it to the end.
BUG=chrome-os-partner:29981
BRANCH=None
TEST=Built and ran through to depthcharge on rush. Also
printed out banks, port, and bit offsets to validate.
Change-Id: I4f6510c1b6fcdddddbe36ff738299b4439ffc597
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4c020c2125b9a2378a7faa17209d1b78e019c7df
Original-Change-Id: I0471480e8658de9e534beb859a1f5027a961d73e
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/210908
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8907
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
It's helpful to be able to track this information. Therefore
dump it in to the console log.
BRANCH=None
BUG=chrome-os-partner:31126
TEST=Built and ran on rush. Revision information is put out on the
console.
Change-Id: I22e7d222259c1179b90edda6d7807559357f6725
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 18d318331b696a6a32e0a45b8f903eb740896b02
Original-Change-Id: Ic95382126a6b8929d0998d1c9adfcbd10e90663f
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/210903
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8905
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
