Add fan speed rpm control for DPTF based Active2 policy as per
document #626708, by utilizing existing FAN0 variable from
src/ec/google/chromeec/acpi/emem.asl#18.
There is no corresponding EC change required for this policy
support because EC fan code already exporting this rpm value
using EC_MEMMAP_FAN for FAN0.
BUG=b:224457192
BRANCH=None
TEST=Built and booted on ADL-P based Brya system and
verify the fan speed in rpm under sysfs path
cat /sys/bus/acpi/devices/INTC1048\:00/fan_speed_rpm.
Change-Id: Ibb1646b1fb1659fd853ece97d97bb9dee2a3f57e
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62789
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Sabrina uses the SVI3 spec for VID tables which is incompatible with the
SVI2 spec used on PCO/CZN. Move the defines from common to soc and
update the decoding for sabrina.
See NDA docs #56413 for SVI3 and #48022 for SVI2 VID tables
TEST=timeless builds on mandolin/majolica for PCO/CZN
build chausie and verify pstate power is correct in ACPI tables
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I915e962f11615246690c6be1bee3533336a808f2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65001
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Currently, custom TianoCore builds are allowed, but those may need
different parameters. Add a Kconfig option to specify additional
parameters to be appended to build command.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Change-Id: I025459ae94592103b4be0c68b422100b7c649d34
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62497
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
When the CMOS option `power_profile` is set to Power Saver, disable
Burst.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I4d9367306b3c0e83252cea3ee4c2733c8729d10c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65011
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Shotzo is not a laptop (it is a Chromebase), therefore deselect
BASEBOARD_DEDEDE_LAPTOP.
BUG=b:235303242
BRANCH=dedede
TEST=build
Change-Id: I4669ef163e4bd8f2de556a051197802ee2d54927
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65015
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Create the shotzo variant of the waddledee reference board by
copying the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0.).
BUG=b:235303242
BRANCH=dedede
TEST=util/abuild/abuild -p none -t google/dedede -x -a
make sure the build includes GOOGLE_SHOTZO
Change-Id: Ia3dc9ea6d1b369b54a966ad86f1531305b8a7f57
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65014
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
mainboard_vbt_filename() is to decide which VBT to return,
but moli only has one VBT, so it doesn't need this function.
BUG=b:234521809
TEST=emerge-brask coreboot.
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: Ia9c1495c8cb7bf7b47d9c616891a791a32b9d805
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64848
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch drops enable_bios_reset_cpl() as FSP sets the BIOS Reset
CPL before performing Graphics PM init (as part of FSP-S), hence,
enable_bios_reset_cpl() function getting called inside systemagent.c
is meaningless.
Also, drop 1ms delay after setting the BIOS reset CPL.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I87beb444d3910f212a5a627cb449031db6cae38d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64837
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch provides an option for CPU programming where coreboot
expected to load second microcode patch after BIOS Done bit is set
and before setting the BIOS Reset CPL bit.
BUG=b:233199592
TEST=Build and boot google/taeko to ChromeOS.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I426b38cb1200e60398bc89515838e49ce0a98f06
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64836
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add Kconfig option `SOC_INTEL_ALDERLAKE_S3` which will adjust
the ACPI to not offer D3Cold when using S3.
This patch is the Alder Lake equivalent of CB:59024.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I04df8e106f9d53337b9eb5d2b9041b44a0e36684
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Support up to 10 PCIe source clock out, including source clock out 7, 8, 9.
This allows boards to use source clock 7, 8, 9.
BUG=b:233252409
BRANCH=firmware-brya-14505.B
Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com>
Change-Id: I0296974fb8557de1edea7f9ca2d96db0afd8a743
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63943
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
1. add timeout for root port detection and pass to FSP.
2. add 'slot implemented' flag and pass to FSP.
3. PcieRpSlotImplemented needs to be set when the root port is set to
hotplug. There is an assertion in FSP checking this.
4. PcieRpSlotImplemented is updated only when it is built-in as it is
default to slot implemented in FSP.
BRANCH=firmware-brya-14505.B
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I13feb1d2d67eaba634a3e700685132fba39e1525
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63942
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Create new variant of Brya "ghost4adl".
Memory config and device tree was sourced from the schematics
(revision 7670d041f40279b5126990f20ec8f90c0538440c).
GPIO overrides have not been added yet. This is to be added in a
follow-on CL.
BUG=b:234626939
BRANCH=firmware-brya-14505.B
TEST=FW_NAME=ghost4adl emerge-brya chromeos-bootimage
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I43c663d700ce8b53248fe203f0becc52610ddb70
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64879
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Override the type-C USB2 port setting from `USB2_PORT_TYPE_C` to `USB2_PORT_MAX_TYPE_C`.
The change is required to detect USB2 device on type-C port of Agah boards.
BUG=b:233554817
TEST=build and test USB2 hub could be detected on both the Type-C ports.
=================================================================
usb 3-3: New USB device found,idVendor=1a40,idProduct=0801,bcdDevice= 1.00
usb 3-3: New USB device strings: Mfr=0, Product=1, SerialNumber=0
usb 3-3: Product: USB 2.0 Hub
hub 3-3:1.0: USB hub found
hub 3-3:1.0: 4 ports detected
=================================================================
Change-Id: I856402aa128db0c4ba092e1c2a66e29bc9165c40
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64988
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add craaskbowl supported memory parts in mem_parts_used.txt, generate
SPD id for this part.
1. Samsung K3LKBKB0BM-MGCP
2. Hynix H9JCNNNCP3MLYR-N6E
BUG=b:235134420
TEST=Use part_id_gen to generate related settings
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: I5f6d1b1b988468d0918df20a34a3145af30a65d2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64858
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add commonlib/bsd/elog dependency in libpayload. This will allow other
payloads (e.g. depthcharge) to implement their own eventlog read and
write utilities.
Also include commonlib/bsd/elog.c source to libc-srcs. This ensure
payloads could utilize commonlib elog helper functions.
Change-Id: I64d0fdd2a8eff1d89a1ac451d37b61787b5564e7
Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63115
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Sumeet Pawnikar