Commit Graph

48727 Commits

Author SHA1 Message Date
Martin Roth eaa21ae171 southbridge: Add SPDX identifiers to files missing them
This adds SPDX identifiers to the remaining source files in the
southbridge directory that don't already have them.

Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: If74aa82a7c40293198e07e81ceac52bd8ca8ad27
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66500
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-11 17:52:52 +00:00
Martin Roth f7319225e9 drivers: Add SPDX identifiers to files missing them
This adds SPDX identifiers to the remaining source files in the
drivers directory that don't already have them.

Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: I97f96de857515214069c3b77f3c781f7f0555c6e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66499
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-11 17:52:38 +00:00
Martin Roth c0f85e7a18 src/mb: Add SPDX identifiers to files missing them
This adds SPDX identifiers to the remaining source files in the
mainboard directory that don't already have them.

Change-Id: I1adc204624f3ab6fcafd8fbb239e6d69e057973a
Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66498
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2022-08-11 17:52:19 +00:00
Srinidhi N Kaushik 9f6e25d6b0 src/soc/intel/mtl: Add VPU support
This change adds support for enabling VPU on MTL SoC.

BUG=b:240665069
TEST=build coreboot mtlrvp

Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: Ie79b45f34a669b9ff777599cb85217abac6cb74e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2022-08-11 07:35:41 +00:00
Mark Hsieh 7a0eff6b8e mb/google/nissa/var/joxer: Add WiFi SAR table
Add WiFi SAR table for joxer.

BUG=b:239788985
TEST=build FW and checked SAR table can load by WiFi driver.

Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: Ia8dddf454e441840233fa4405704ee1f0a8ed86c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66522
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-10 19:26:18 +00:00
Lance Zhao 7ef330304b docs/utils/ifdtool: Fix waning of malformed table
Signed-off-by: Lance Zhao <lance.zhao@gmail.com>
Change-Id: Idc90c6e8186320979a72563fb5dcdc8fce760e72
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66562
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-10 19:24:16 +00:00
Frans Hendriks f4040e63c8 soc/intel/tigerlake: Add USBOTG and CrashLog to irq table
FSP reports missing IRQ for devices.

Add USBOTG (D20:F1) and CrashLog & Telemetry (D10:F0) to irq_constrain.

Bug = N/A
TEST = Build and boot Siemens AS-TGL1

Change-Id: Ic02d33045a07a6888ba97d8f2c6fa71bc7e363e8
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-08-10 19:21:06 +00:00
Martin Roth f67a1aa76a util/lint & LICENSES: Add PDDC as a "license" for coreboot
The Creative Commons Public Domain Dedication and Certification is not
a license in the common sense in that it's stating that the associated
file is already in the public domain (having no copyright), and is not
actually putting it in the public domain like the CC-C0 license does.

The use for this in coreboot is for unlicensable files - either blank
files or files with no creative content.  This allows these files to
have the SPDX identifier to identify them as having no known copyright
for open source license compliance.

If CC-PDM-1.0 is ever included in the list of SPDX licenses, that would
probably fit better, but because the public domain mark isn't actually
a license, and because "public domain" isn't well defined, CC-PDM was
rejected as a SPDX identifier.

For further information:
https://web.archive.org/web/20201018194411/https://github.com/spdx/license-list-XML/issues/988

Change-Id: Ibb300ecd066cde2a016195c2beca76a460c588e3
Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66496
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-08-10 19:07:20 +00:00
Martin Roth afa3e5aa49 util/lint & LICENSES: Add GCC-exception-3.1 to license exceptions
The gcov files in the lib directory are licensed GPL 3.0 with the GCC
runtime library exception.

Add this as a valid license so that the files can get a correct SPDX
identifier.

Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: I1cf9c3125592741923c9b4481038055f24fe6ab1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-08-10 19:07:02 +00:00
Martin Roth 34f0f05158 LICENSES: Add missing licenses and exceptions
These licenses and exceptions are allowed by coreboot's license checker,
but the copies of the licenses were missing from the LICENSES directory.

Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: Ic4233e556de08275fe50f1ec83828f9470b4b566
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66494
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-08-10 19:06:46 +00:00
Raul E Rangel 30edb46e8c mb/google/zork: Set vw_irq_polarity from low to high
The EC used on zork uses a level high interrupt. This change configures
the polarity correctly.

The eSPI config is baked into RO verstage. The zork ToT build doesn't
use signed verstage since it's incompatible with the ToT version of
vboot. This means we can safely switch the keyboard IRQ polarity.

NOTE: Do not cherry pick this into the Zork firmware branch!

BUG=b:160595155
TEST=On morphius verify keyboard works as correctly and no spurious
interrupts are thrown on S0i3 resume. Also verified keyboard and mouse
work correctly in windows.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I8d3195522f3bd5e477635494c7156683aae0ff0a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66291
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-08-10 17:13:07 +00:00
Raul E Rangel 74bce48f1d mb/google/{zork,guybrush,skyrim},soc/amd/espi: Fix vw_irq_polarity
The default state for the IRQ lines when the eSPI controller comes out
of reset is high. This is because the IRQ lines are shared with the
other IRQ sources using AND gates. This means that in order to not cause
any spurious interrupts or miss any interrupts, the IO-APIC must use a
low polarity trigger.

On zork/guybrush/skyrim the eSPI IRQs are currently working as follows:
* On power on/resume the eSPI controller drives IRQ 1 high.
* eSPI controller gets configured to not invert IRQ 1.
* OS configures IO-APIC IRQ 1 as Edge/High.
* EC writes to HIKDO (Keyboard Data Out) which causes the EC to set IRQ1
  high.
* eSPI controller receives IRQ 1 high, doesn't invert it, and leaves IRQ
  1 as high. This results in missing the first interrupt.
* When the x86 reads from HIKDO, the EC deasserts IRQ1. This causes the
  eSPI controller to set IRQ1 to low. We are now primed to catch the
  next edge high interrupt. This is generally not a problem since the
  linux driver will probe the 8042 with interrupts off.

On S3/S0i3 resume since the eSPI controller comes out of reset driving
the IRQ lines high, we trigger a spurious IRQ since the IO-APIC is
configured to trigger on edge high. This results in the 8042 controller
getting incorrectly marked as a wake trigger.

By configuring the IO-APIC to use low polarity interrupts, we no longer
lose the first interrupt. This also means we can use a level interrupt
to match what the EC actually asserts.

We use the `Interrupt` keyword instead of the `IRQ` keyword in the ACPI
because the linux kernel will ignore the level/polarity parameters
for the `IRQ` keyword and default to `edge/high. `Interrupt` doesn't
have this problem.

The PIC is not currently configured anywhere and it defaults to an
edge/high trigger. We could add some code to configure the PICs trigger
register, but I don't think we need the functionality right now.

For zork and guybrush, this change is a no-op. eSPI is configured in
verstage which is located in RO, and we have already locked RO for
these devices. We will need to figure out how to properly set the
`vw_irq_polarity` for these devices.

BUG=b:218874489, b:160595155, b:184752352, b:157984427, b:238818104
TEST=On zork, guybrush and skyrim
$ suspend_stress_test --post_resume_command 'cat /sys/devices/platform/i8042/serio0/wakeup/wakeup35/active_count'
Verify keyboard works as expected and no interrupt storms are observed.

On morphius I verified keyboard and mouse work on windows as well.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I4608a7684e34ebb389e0e55ceba7e7441939afe7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54924
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-08-10 16:30:19 +00:00
Kapil Porwal 423bc1a379 MAINTAINERS: Add lists for soc/intel/meteorlake and mb/google/rex
Change-Id: Ia5def4cf86b47ac96ba5fc6ec86a139d5ad2765e
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-08-09 19:24:00 +00:00
Stanley Wu c8ffc82734 mb/google/nissa/var/pujjo: Enable USB3.0 port 3 for WWAN
Pujjo support WWAN device, enable USB3.0 port 3 for WWAN device

BUG=b:241322361
TEST=Build and boot on pujjo

Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: Iafe2ea18663794138e0a27879fc108d23eb81456
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-08-09 19:23:02 +00:00
Martin Roth 298b00776a utils: Add initial version of "remove_unused_code" script
This script creates a patch to remove all of the coreboot code that a
platform doesn't use.  This is useful for auditing the codebase for an
individual platform or releasing a platform's code.

Unlike the script that Sage used that did something similar, this keeps
the entire Kconfig tree (Though in a single file), all makefiles that
are required to build, and the standard build tools can still be used.
This will allow for much easier re-integration back into the coreboot
codebase if code is released after running this.

This is just the initial version and more features needed to be added to
make it fully functional.
- It should be able to build multiple configurations to retain the code
for all of those configurations.
- Flag to remove submodules files as well
- Additional variable flags to replace hardcoded values.
- The list of makefiles that need to be kept is pretty long, and could
be updated so that they aren't needed by the top level makefiles.
- Add flag to show changed files
- Show number of files before and after script is run

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Iec69db2ad1358846d649db627b6d60ac8c2204e4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-08-09 19:22:31 +00:00
Kevin Chowski a31b7ea7f7 mb/google/brya/var/ghost: update arbitrage gpio.c header
This update follows suggestions from Martin Roth about the contents of
the comment.

Change-Id: Ic296bcd6a0fb250426f5d75aac69a3fa0f2aaf32
Signed-off-by: Kevin Chowski <chowski@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66555
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-08-09 17:03:31 +00:00
Karthikeyan Ramasubramanian e5af14ace6 util/amdfwtool: Fix ISH_B directory offset
On boards which use both PSP recovery A/B layout as well as VBOOT A/B
layout, ISH_B directory entry is pointing directly to PSP Level2
directory. This is not correct and either ISH_B should be marked as not
present or it should point to the ISH_A directory itself which in turn
point to PSP L2 directory. Fix it by choosing the latter option.

BUG=None
TEST=Build and boot to OS in Skyrim with PSP verstage.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I0a7a56e98de3f85669ff8ec2fcd1687aa33576a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66445
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-08-09 16:44:47 +00:00
Meera Ravindranath 5e80bcfaea mb/google/brya: Select SOC_INTEL_COMMON_UFS_SUPPORT for Nissa
BUG=b:238262674
TEST=Build and check ufs.c file gets compiled for Nissa boards

Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: Idc5ad922b97bd1e65e5023f9126c43e42cfc38a5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66064
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-08 18:08:16 +00:00
Marshall Dawson 26d7d737c1 soc/amd/sabrina: Rename PSP SPL default
Change the SPL file from the 'cezanne' placeholder to a mendocino
filename.  Also, move the default location to blobs/mainboard since
it's not board-agnostic.

BUG=b:241543152
BUILD=Enable feature and build amd/chausie

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I47647c5d926484e25e3f893e72c671554e277a56
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66465
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-08-08 16:59:30 +00:00
Marshall Dawson 84fef892dd soc/amd/sabrina: Rename PSP whitelist default
Change the name of the whitelist file from the 'cezanne' placeholder
to a mendocino path/to/file.  Also, as whitelist files won't be pushed
into a public repo, modify the path to point to site-local.

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I49bbf1335606567735e36ed9bda1314bfc6247d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66464
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-08-08 16:59:30 +00:00
Marshall Dawson 336e25a3b7 soc/amd/sabrina: Use new mendocino amd_blobs
Modify sabrina's fw.cfg to point to the proper directory and use the
standard names, as released by AMD.

The name 'sabrina' was an alias used for the Mendocino product.  The
public-facing builds have been using Cezanne blobs, renamed as Sabrina
or SBR, but can now take advantage of the appropriate blobs.

BUG=b:239072117
TEST=Build amd/chausie

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: Id646844e41980802be1e39dce96e5adaace4311d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66463
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-08-07 19:57:06 +00:00
Marshall Dawson cdaefbbdd9 3rdparty/amd_blobs: Advance submodule pointer
This picks up the following changes
  83c44ad mendocino: Add additional SPI configs
  5141d91 mendocino: Add all blobs from PI 1.0.0.1
  3b29a7d cezanne: Upgrade microcode patch to 00A50F00h

BUG=239072117

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I1060dc7bec8f436dccf270bc3abde75cb09bb591
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66462
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-08-07 19:56:38 +00:00
Jon Murphy 156aa9b4c7 mb/google/skyrim: Resolve boot behavior
Move GPIO init for SSD_AUX_RESET_L to ensure that eMMC devices
will be initialized in time for the nominal boot flow.

BUG=b:237701972
TEST=Boots to OS
BRANCH=none

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I610966fd9d31581f15d8bcd51f8a116c27fd6311
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66461
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-07 19:55:36 +00:00
Jack Rosenthal ebd5be3f66 mb/google/brya/var/ghost: Pull EN_PP3300_TCHSCR high
This gets the display working.

BUG=b:240884260
BRANCH=firmware-brya-14505.B
TEST=display works in both depthcharge and linux

Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I03edac865d68ef48e86d47a04f27ed84894f2f7f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66395
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
2022-08-07 19:55:19 +00:00
Michał Kopeć a7a40a5b10 superio/ite/common/early_serial.c: ite_kill_watchdog: set timeout to 0
Set the watchdog timeout to 0 in ite_kill_watchdog, as in some ITE
models it is set to non-zero by default, activating the watchdog despite
us setting the control register to 0.

Based on:
- "ITE IT8786E-I Preliminary Specification V0.4.1 (For D Version)"
- Linux it87_wdt driver

Change-Id: I1e78e2acc96e9dd0f283c5c674d3277d26cdee26
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66189
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-08-07 19:54:43 +00:00
Marshall Dawson 0700940bb7 mb/amd/chausie: Add Kconfig prompts to EC strings
Make the default Microchip EC firmware path/to/file values overridable
by adding prompts to the strings.

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I300f78a11960dbe193165fcb379b7190e3de4545
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-08-07 19:53:07 +00:00
Bill XIE 385e43274e pciexp_device: Handle unsupported requests in pciexp_get_ext_cap_offset()
Looking into pciexp_get_ext_cap_offset() it seems a little hackish
and prone to endless loops. Either it should limit the loop or bail
out when pci_read_config32() returns 0xffffffff, meaning "Unsupported
Requests".

This commit fixes an endless loop when the queried PCIe device is
downstream of a legacy PCI bus which doesn't support extended config
space, thus pci_read_config32() will return 0xffffffff, for example,
the combination below with CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS
enabled.

TEST=Build and boot to OS in ASUS P8C WS with the following
peripherals and CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS enabled:

00:1c.4 PCI bridge [0604]: Intel Corporation 7 Series/C210 Series
	Chipset Family PCI Express Root Port 5 [8086:1e18] (rev c4)

00:1c.4/00.0 SATA controller [0106]: Marvell Technology Group Ltd.
	88SE9170 PCIe 2.0 x1 2-port SATA 6 Gb/s Controller [1b4b:9170]
	(rev 13)

00:1e.0 PCI bridge [0604]: Intel Corporation 82801 PCI Bridge
	[8086:244e] (rev a4)

00:1e.0/00.0 PCI bridge [0604]: PLX Technology, Inc. PEX 8111 PCI
	Express-to-PCI Bridge [10b5:8111] (rev 21)

00:1e.0/03.0 FireWire (IEEE 1394) [0c00]: VIA Technologies, Inc.
	VT6306/7/8 [Fire II(M)] IEEE 1394 OHCI Controller [1106:3044]
	(rev c0)

00:1e.0/00.0/00.0 Network controller [0280]: Qualcomm Atheros AR93xx
	Wireless Network Adapter [168c:0030] (rev 01)

with 00:1c.4/00.0 being successfully tuned with pciexp_tune_dev(), and
00: 1e.0/00.0/00.0 not tuned as expected.
Change-Id: Ibb92548c47288b40e851fcc0a8a37937e8bdbf3c
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66439
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-08-07 19:49:35 +00:00
Sean Rhodes 02f2b19384 payloads/tianocore: Remove the option for CorebootPayloadPkg
Recent changes to both coreboot and edk2 means that UefiPayloadPkg
seems to work on all hardware. It has been tested on:
* Intel Core 2nd, 3rd, 4th, 5th, 6th, 8th, 8th, 9th, 10th,
  11th and 12th generation processors
* Intel Small Core BYT, BSW, APL, GLK and GLK-R processors
* AMD Stoney Ridge and Picasso

This includes the problematic Lenovo X230s. The most likely fixes are:
* Configuring the PCI Base and Length in edk2
* Fixes to the HostBridgeLib in edk2
* Adjustment to the SD/eMMC initialisation timeout

This means we can now remove the already deprecated option for
CorebootPayloadPkg and the legacy 8254 timer build option.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ice7b7576eb3d32ea46e5138266b7df3fbcdcf7ea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65721
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-08-07 19:48:17 +00:00
Jeremy Compostella 7f96c05280 soc/intel/alderlake: Fix RPL-P 282 15W GT ICC MAX
The software used to read the document listing the VR settings turns
out to not be perfectly compatible. Indeed, it displays a value of 55A
for RPL-P 282 15W GT ICC MAX while the correct value actually is 40A.

After a thorough review using the software used to create the
document, it is the only value presenting a discrepancy.

BRANCH=firmware-brya-14505.B
BUG=b:239797178
TEST=build and boot

Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Change-Id: Iee293c87a66f0cd32714766e3ad81eee1a411723
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66057
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.corp-partner.google.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-08-07 19:46:52 +00:00
Karthikeyan Ramasubramanian b2af2e35f4 soc/amd/sabrina: Enable PSP Crypto Co-Processor (CCP) DMA
Boot issue while using FW slot A has been root-caused to the usage of
same TLB to map HW Crypto engines and SPI flash. With upcoming PSP
release, this TLB usage conflict has been resolved. Hence enable CCP
DMA.

BUG=b:240175446
TEST=Build and boot to OS in Skyrim with PSP verstage using CCP DMA.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I2b12adb7e94e489bf07963a6f9a829cf4b36ad5c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66444
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-08-07 19:45:00 +00:00
Karthikeyan Ramasubramanian 8b1c6c6cb3 soc/amd/sabrina: Re-init eSPI in bootblock
Currently bootblock does not initialize eSPI if it is already done in
PSP verstage. But some other component is clobbering the eSPI
configuration causing timeouts in EC communication after the boot flow
hits x86. To workaround this issue, re-initialize eSPI in bootblock.

BUG=b:217414563
TEST=Build and boot to OS in Skyrim with PSP verstage.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I41c0b2816a106a6a547f3cb372693e1bb7f23734
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-08-07 19:44:15 +00:00
Tarun Tuli 1c718519f4 mb/google/rex: Remove depedency on board id for early GPIO config
This adds a default early GPIO table in the case of us not being
able to identify a valid board ID.

Primarily, this is useful in the case of EC issues to ensure
that debug interfaces (e.g. UART) are always up and available.

BUG=b:238165977
TEST=Boots and no errors on simics

Signed-off-by: Tarun Tuli <taruntuli@google.com>
Change-Id: I135dc6c29bc23195afe5c78eb79992691652d9e4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66394
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-08-07 19:43:20 +00:00
Bill XIE 513d359dad pci_device: Add a function to find PCI capability ID recursively
Some PCI capabilities should only be enabled if it is available not
only on a device, but also all bridge upstream of it. Checking only
the device and the bridge just above it may not be enough.

Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: I1237d3b4b86dd0ae5eb586e3c3c407362e6ca291
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66383
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-07 19:41:38 +00:00
Bill XIE a43380e3d5 pciexp_device: Fix a bug in pciexp_enable_ltr()
'parent_cap' should be found from 'parent' instead of 'dev'.

Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: I99dab83d90287ca924d30dc4aeac0ff96e877e5c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66385
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-08-07 19:40:28 +00:00
Saurabh Mishra debb8085c6 vc/intel/fsp: Update ADL N FSP headers from v3222.03 to v3267.01
Update generated FSP headers for Alder Lake N from v3222.03 to v3267.01.

Changes include:
- Add UPD Lp5BankMode
- Update UPD Offset in FspmUpd.h

BUG=b:240373012
BRANCH=None
TEST=Build using "emerge-nissa intel-adlnfsp"and boot Nissa.

Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com>
Change-Id: I7b921e2aa467593a1c764fc554e2e83e8bb522e8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66222
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-07 19:39:43 +00:00
Tony Huang df864709a5 mb/google/brya/variants/agah: update dptf setting
1. Add active policy
2. Set critical policy trigger point to 105C
3. Correct TSR location

BUG=b:240634844
TEST=emerge-draco coreboot
     values provided and verified by thermal team

Change-Id: I0d91bad03cbdeea5c84b533580ac98072ce0110b
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-08-07 19:35:52 +00:00
Tim Wawrzynczak 66d090b664 mb/google/brya/acpi: Fix PERST# handling in GC6 exit
PERST# is supposed to be de-asserted in GC6 exit, but the original
patch used the CTXS Method, which drives a GPIO low, instead of
STXS, because PERST# is active-low. This patch fixes that.

BUG=b:214581763

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ib0adb8efe5e2cc733ae2228614c58c124ba3f11b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66402
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-08-07 19:34:23 +00:00
Caveh Jalali f85e3cd269 mb/google/brya/var/ghost: Disable LID_SHUTDOWN
The lid sensor is on a daughterboard which can cause unintended
shutdowns when not connected. Disable lid sensor based shutdown behavior
in depthcharge until we have a better solution.

BUG=b:240005819
BRANCH=firmware-brya-14505.B
TEST=booted ghost, no longer shuts down due to missing lid sensor

Change-Id: I69f70255dee1b69e05b112c0174f5f52d1368837
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-08-07 19:33:32 +00:00
Frans Hendriks fd1a53f5c1 soc/intel/tigerlake: Expose In-Band ECC config to mainboard
Support for feature "In-Band ECC" not available for Tiger Lake

Similar to Elkhart Lake, Tiger Lake also provides this feature.
Ported from Elkhart Lake (CB:55668)

Bug = N/A
TEST = Build and boot Siemens AS-TGL1

Change-Id: Ie54d5f6a9747fad0105d0f8bf725be611bb8cf60
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66372
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-08-07 19:30:43 +00:00
Tim Wawrzynczak 1750877ffd mb/google/brya/acpi: Fix NVJT subfunction IDs
The POWERCONTROL and PLATPOLICY NVJT subfunctions were incorrectly set
to 2 and 3, respectively. While looking at the ACPI code, Nvidia noticed
these are supposed to be 3 and 4, also respectively, so this patch fixes
that.

BUG=b:214581763

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I0f808aba7072b943ee2fad20e06ff39a9b54903d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66374
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-08-07 19:28:56 +00:00
Reka Norman abbfa555b0 commonlib/timestamp_serialized: Add comment explaining "ignore for x86"
BUG=b:240624460
TEST=None

Signed-off-by: Reka Norman <rekanorman@chromium.org>
Change-Id: I8542c9bb624a366bc1bb01f6eae66ba97520d19c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66381
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-07 19:28:09 +00:00
Tarun Tuli d454f86ed8 mb/google/rex: Add memory config for rex
Configure the rcomp, dqs and dq tables based on the schematic
dated July 17/2022 and Intel Kit #573387.

TEST=Built successfully

Signed-off-by: Tarun Tuli <taruntuli@google.com>
Change-Id: I092f42db252052382d377a4ae48dc25f73080a3b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66202
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-06 15:15:53 +00:00
Subrata Banik 151dcf49a6 util/elogtool: Mark redundant boot mode event type as `deprecated`
This patch adds `_DEPRECATED_` tag to ChromeOS boot mode related event
logging types as below:

* ELOG_TYPE_CROS_RECOVERY_MODE <---- to record recovery boot reason
                                     while booting into recovery mode
* ELOG_TYPE_CROS_DEVELOPER_MODE <--- if the platform is booted into
                                     developer mode.
* ELOG_TYPE_CROS_DIAGNOSTICS <---- if the platform is booted into
                                     diagnostic mode.

Drop static structure `cros_deprecated_recovery_reasons` as it has been
replaced by vb2_get_recovery_reason_string() function.

ELOG_TYPE_FW_BOOT_INFO event type is now used to record all those
related fw boot info along with ChromeOS boot mode/reason etc.

BUG=b:215615970
TEST=Build and boot google/kano to ChromeOS.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I932952ce32337e2d54473667ce17582a90882da8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65802
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-08-06 14:06:33 +00:00
Robert Chen 3a53da1632 mb/google/brya/var/vell: Set GPP_B2 NC for RGB keybaord
When GPP_B2 output high, there is a leakage path. This patch fix it by
setting the pin NC.

BUG=b:233959105
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot

Change-Id: I3c833d5d62c715960dcb27494a0b9b93c91e8f2f
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66382
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-08-05 22:26:11 +00:00
Srinidhi N Kaushik 15b439e264 vc/intel/fsp/mtl: Update header files from 2253_00 to 2304_01
Update header files for FSP for Meteor Lake platform to
version 2304_01, previous version being 2253_00.

FSPM:
1. Removed CpuCrashLogDevice
2. Address offset changes

FSPS:
Includes below new UPDs
1. VpuEnable
2. SerialIoI3cMode
3. ThcAssignment
4. PchIshI3cEnable

BUG=b:240665069
TEST=emerge-rex intel-mtlfsp

Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I9740e5877af745124d573425da623e814d8df5d7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66289
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-05 17:48:03 +00:00
Srinidhi N Kaushik 1adba03884 soc/intel/mtl: Remove deprecated FSP option
Remove the reference to `CpuCrashLogDevice` UPD since FSP v2304.01 has deprecated this UPD.

BUG=b:240665069
TEST=build rex coreboot

Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I23223fd7936a60d974229b553de255a7dcf4416b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66357
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-08-05 17:47:39 +00:00
Nick Vaccaro 648c28f5a0 mb/intel/adlrvp: shorten MAINBOARD_PART_NUMBER to fix build
Building firmware for Brya is currently broken due to the RO_FWID region
for adlrvp_m_ext_ec bloating past 64 characters.

The CONFIG_MAINBOARD_PART_NUMBER is catenated onto the
CONFIG_MAINBOARD_VENDOR string, which for Intel, makes for a very long
trunk string that the kernel version will then be added to form the
RO_FWID string. For Intel, that trunk string is already pretty long at :
"Intel Corporation_Alder Lake Client Platform".

Shortening the CONFIG_MAINBOARD_PART_NUMBER should address this issue
for now.

BUG=b:241273391
TEST="emerge-brya coreboot chromeos-bootimage" and verify it builds
successfully

Change-Id: Ie862c87dd9a24743f249f1b10862ca6f3295db23
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2022-08-04 23:55:20 +00:00
Felix Held 300f7ea18d soc/amd/cezanne/cppc: drop duplicate newline
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I774be6d80e0aae725ecb1027501c8d66e0bf5a08
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66399
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2022-08-04 22:50:00 +00:00
Felix Held 9a7670f1a3 soc/amd/cezanne/cppc: reduce visibility of cpu_init_cppc_config
This function is only called from the same compilation unit, so turn it
into a static function.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5c2deaa46f69c763df9612e39415b37c60d631be
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2022-08-04 22:50:00 +00:00
Jonathon Hall 5ec1c14058 MAINTAINERS: Update maintainer for Purism mainboards
Change-Id: Ie5c2d01e13cafdbfd629ebe52af8b1f0cc8f20be
Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66378
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-08-04 15:08:11 +00:00