Increase the number of total dimm to 16 to support system with more
than 8 dimms. Also, remove unneeded comment.
TESTED=On S9S, dmidecode -t 17 shows expected results.
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: Iead53e96f37c55ba1b7a13fb62db1a1c10fa2e1f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58440
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add system wake-up type in smbios type 1 - system information.
TESTED=On S9S, can override original value and show expected result
using "dmidecode -t 1".
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: If79ba65426f1f18ebb55a0f3ef022bee83c1a93b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58436
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Correct GPIO GPP_R6 and GPP_R7 setting to NF2 (DMIC_CLK1 and DMIC_DATA1).
BUG=b:202913826
TEST=FW_NAME=kano emerge-brya coreboot and verify it builds
without error.
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ibf8ff0e48c4bab435d082dee27bcd53bc85b088d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: CT Lin <ctlin0@nuvoton.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
M.2 spec describes PERST# should be sequenced after power enable.
BUG=b:197385770
TEST=emerge-brask coreboot and verify it builds without error.
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ia7e5c7b1a2194d53d98865d33cf1bc6111572876
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58463
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Some elements in the ACPI CPPC table allow static DWORDs. Instead of
using a fake register resource, use a tagged union with the two types
"register" and "DWORD" and respective macros for CPPC table entries.
Test: dumped SSDT before and after do not differ.
Change-Id: Ib853261b5c0ea87ae2424fed188f2d1872be9a06
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57886
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
SOC_PEN_DETECT_ODL, SOC_SAR_INT_L and WWAN_AUX_RESET_L are not connected
in nipperkin. Override those GPIO configurations.
BUG=None
TEST=Build and boot to OS in Nipperkin.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I7e497f83593472ecf4927e5379e1dd7786e77e62
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58379
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
WWAN_AUX_RST_L is asserted during S0i3 entry. But it needs to be
de-asserted before PCIe link training during S0i3 resume. Otherwise the
concerned gpp_bridge_2 PCIe device is not enumerated on Soi3 resume.
This change feeds in the WWAN_AUX_RST_L GPIO in the DXIO descriptor so
that SMU de-asserts this reset on S0i3 resume.
BUG=b:199780346
TEST=Build and boot to OS in Guybrush. Perform suspend/resume cycles for
500 iterations. Ensure that the PCIe devices enumerate fine.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I588c490bf3f8a7beffefc3bfd8ca5167fcbcb9a5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58459
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Instead of a const port descriptor, make it configurable. This will help
to avoid adding duplicate tables for every minor configuration updates.
BUG=None
TEST=Build and boot to OS in Guybrush. Perform suspend/resume, warm and
cold reboot cycles for 10 iterations each.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: If616a08ba54fddab25e5d0d860327255dfd43cbe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58378
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Using cb_err as return type clarifies the meaning of the different
return values. To not change the return types of mp_run_on_aps which is
exposed outside of this compilation unit to keep the scope of this patch
limited, the return value of run_ap_work gets translated to the int
values in mp_run_on_aps. This could also be done by a cast of the
run_ap_work return value to int, but an explicit translation of the
return values should be clearer about what it does there.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id346c8edf06229a929b4783498d8c6774f54a8b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58490
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Using cb_err as return type clarifies the meaning of the different
return values. To not change the return types of mp_init_with_smm which
is exposed outside of this compilation unit to keep the scope of this
patch limited, the return value of mp_init gets translated to the int
values in mp_init_with_smm. This could also be done by a cast of the
mp_init return value to int, but an explicit translation of the return
values should be clearer about what it does there.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4129c1db06a877c47cca87782af965b62dcbbdc2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58489
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Using cb_err as return type clarifies the meaning of the different
return values. Also restructure the implementation of wait_for_aps to
not need a local timeout variable.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I86b8c8b0849ae130c78125b83d159147ce11914c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58488
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Using cb_err as return type clarifies the meaning of the different
return values. Also restructure the implementation of apic_wait_timeout
to not need a local timeout variable.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2fe32c761492d252b154d2f50f2a330cf4f412d5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58487
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Using cb_err as return type clarifies the meaning of the different
return values.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifb64b5908b938bb162153433e5f744ab0b95c525
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58486
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Using cb_err as return type clarifies the meaning of the different
return values.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I95f36ba628c7f3ce960a8f3bda730d1c720253cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58485
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
We now pre-populate cpu_info before jumping to the C handler. We no
longer need this parameter.
I moved the stack alignment closer to the actual invocation of the C
handler so it's easier to reason about.
BUG=b:194391185, b:179699789
TEST=Boot guybrush to OS and verify all CPUs still function
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I8997683b6613b7031784cabf7039a400f0efdea1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This will reduce the number of AP init paths we need to support.
BUG=b:194391185, b:179699789
TEST=Boot guybrush to OS and see all CPUs initialized correctly
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I05beb591bd7b3a26b6c51c10d4ffd6f8621c12eb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58146
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
There are two possible code sections where the cpu_info macros can be
included: .code32 and .code64
Doing a `push %eax` while in a .code64 section will result in a compiler
error. This macro manually pushes the 32-bit register onto the stack so
we can share the code between 32 and 64 bit builds.
We also can't implicitly dereference per_cpu_segment_selector because
it's a 32-bit address. Trying to do this results in the following:
E: Invalid reloc type: 11
E: Illegal use of 32bit sign extended addressing at offset 0x1b2
If we load the address first, then dereference it, we can work around
the limitation.
With these fixes, 64-bit builds can now use CPU_INFO_V2.
BUG=b:179699789
TEST=Boot qemu 64 bit build with CPU_INFO_V2 and 4 CPUs. See AP init
work as expected.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I4e72a808c9583bb2d0f697cbbd9cb9c0aa0ea2dc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58232
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Enable the CnviBtAudioOffload UPD and program the corresponding
BT VPGIOs.
BUG=b:202913826
TEST=emerge-brya coreboot and verify it builds without error.
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Id81cba82742f552c098ec3719a0b453b752dc5c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58415
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Add cross-toolchain version file to the release tarball, which can be
used for pre-setting the variables used in buildgcc.
Change-Id: Iad1e0adaa95b71f161caf978276bfb0a63eac8f4
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58399
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
For reproducibility, a version string is appended to the version of the
tools used in the cross-toolchain. Currently, git is used to determine
that version string at runtime of this script. There are cases, where
it's not possible to determine that version string, e.g. when a release
tarball is used, and if so, the version string is just `v_`.
Thus, allow pre-setting the variable `CROSSGCC_VERSION`.
Change-Id: I888ccd877c93436b5e033528c43bd8667b8d2f10
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58396
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This change adds LTE power off sequence for bugzzy.
BUG=None
BRANCH=dedede
TEST=FW_NAME=bugzzy emerge-dedede coreboot
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Change-Id: I6be0e23b9c2c2bed9745011920394006fdaabae6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Enable/disable LTE function based on DB_PORTS field of FW_CONFIG.
- GPIO control
- USB port setting
BUG=None
BRANCH=dedede
TEST=FW_NAME=bugzzy emerge-dedede coreboot
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Change-Id: I8363f8e7052ff9cfa423063a7e8f5a0f9ce1df2c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58442
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
When CONFIG_X86_AMD_INIT_SIPI was set, the second/final SIPI that
afterwards checks if all APs have checked in was skipped and if it got
so far, start_aps returned CB_SUCCESS despite not having checked if all
APs had checked in after the SIPI. This patch makes start_aps skip the
first SIPI in the CONFIG_X86_AMD_INIT_SIPI case so we use the proper
timeouts and error handling for the final and this case only SIPI and
signal the caller an error when not all APs have checked in after the
SIPI.
A timeless build for lenovo/x230 which is a mainboard that doesn't
select X86_AMD_INIT_SIPI results in identical binary, so this doesn't
change the behavior of the !X86_AMD_INIT_SIPI case.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I39438229497c5d9c44dc7e247c7b2c81252b4bdb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58456
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Support Parade ps8640 as the second source edp bridge for some trogdor
board variants/revisions.
BUG=b:194741013
BRANCH=trogdor
TEST=verified firmware screen works on lazor rev9
Change-Id: Iae5ccd8d9d33d60e4c37011ecffdd7a05af59ab2
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58437
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
In preperation to CB:58396, add the parameter `-W|--print-version`,
which allows printing the content of `CROSSGCC_VERSION`. In
combination with CB:58396, this can be used to pre-set the variable
in case of the git history is not accessible.
Change-Id: I9a205ca0ecb0ece47eb5d8fa73706478354512ff
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
For reproducibility, the buildgcc script is copied to the destination
folder of the toolchain. `CROSSGCC_COMMIT` is used as a file name
extension for the script and was introduced when `CROSSGCC_VERSION`
didn't contain the commit yet. Since this is not the case anymore,
remove it.
Change-Id: Id0a0b657eb828b2728ff787228eaa38be83d9517
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58450
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Rework Kconfig file that each variant has its own config option with
their specific selects / configuration and move common selects to
`BOARD_INTEL_ADLRVP_COMMON`, which is used as base for each
variant.
Also, move selects from Kconfig.name to Kconfig that the configuration
is at one place and not distributed over two files.
Built each variant with `BUILD_TIMELESS=1` and all generated
coreboot.rom files remain identical. Excluded the .config file by
disabling `INCLUDE_CONFIG_FILE` to make this reproducible.
Change-Id: If68c118f22579cc0a3db570119798f0f535f9804
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56221
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Using cb_err as return type clarifies the meaning of the different
return values.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Icb96f28b4d59b3d00638a43c927df80f5d1643f9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58455
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since during AP startup it's not guaranteed that no AP console output
will be printed between consecutive printk calls in send_sipi_to_aps,
add a new line character to all printks to make sure to have the outputs
from the APs on separate lines. For consistency also add a final new
line character to the printk call in start_aps.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3983b8a0e6b272ba5fb2a90a108d17a0c480c8b8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58454
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Apart from the SIPI number in the debug message the two instances of the
SIPI sending code in start_aps are identical, so factor it out into a
new send_sipi_to_aps function.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6a921b81fce77fbf58c7ae3b50efd8c3e6e5aef3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58453
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Using types.h as include instead of stddef.h and stdint.h will also
provide commonlib/bsd/cb_err.h which will be used in follow-up patches.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I08a68dc827d60c6c9a27b3ec8b74b9c8a2c96d12
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58452
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When using `DECLARE_OPTIONAL_REGION`, it is assumed that
REGION_SIZE(name) == 0 if the region was not defined in the memlayout.
When using non-rmodule stages (i.e., bootblock, romstage, etc), this
assumption holds true, but breaks down in rmodule (i.e., ramstage)
stages.
The rmodule tool is not currently omitting undefined externals from the
relocation table. e.g.,
extern u8 _##name##_size[];
This means that when the rmodule loader runs, it will rewrite the symbol
from 0 (which is the default the linker assumed) to 0 + offset. This is
wrong since the symbol doesn't actually exist. Instead we need to omit
the relocation so it continues to keep the default value of 0.
BUG=b:179699789
TEST=Print out REGION_SIZE(cbfs_cache) in ramstage and verify it is set
to 0.
I also see the following printed by the rmodtool now:
DEBUG: Omitting relocation for undefined extern: _watchdog_tombstone_size
DEBUG: Omitting relocation for undefined extern: _watchdog_tombstone
DEBUG: Omitting relocation for undefined extern: _watchdog_tombstone
DEBUG: Omitting relocation for absolute symbol: _stack_size
DEBUG: Omitting relocation for absolute symbol: _program_size
DEBUG: Omitting relocation for absolute symbol: _cbmem_init_hooks_size
DEBUG: Omitting relocation for absolute symbol: _payload_preload_cache_size
DEBUG: Omitting relocation for absolute symbol: _payload_preload_cache
DEBUG: Omitting relocation for absolute symbol: _payload_preload_cache_size
DEBUG: Omitting relocation for absolute symbol: _payload_preload_cache
DEBUG: Omitting relocation for undefined extern: _cbfs_cache
DEBUG: Omitting relocation for undefined extern: _cbfs_cache_size
As you can see the _watchdog_tombstone will also be fixed by this CL.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ib57e263fa9014da4f6854637000c1c8ad8eb351a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Instead of using two variables, one for the boolean value and one for
the path, use just one with the path. Since an empty string evalutes to
false, this simplification does not change behaviour.
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I2f1171789af6815094446f107f3c634332a3427e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Instead of substituting the delimiter later, put $inside_choice together
right in the first place.
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: Ia713510a683101c48c86a1c3722ebb1607a29288
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
The SPI DMA controller can only perform transactions on a cache line
boundary. This change removes the magic number and uses the #define to
make it clear.
BUG=b:179699789
TEST=Boot guybrush to OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ie7b851dc2433e44a23224c3ff733fdea5fbcca0c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58377
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
For PchFivrExtVnnRailSxEnabledStates, vnn_enable_bitmap config is used
by mistake, instead of the expected vnn_sx_enable_bitmap
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: Idf100be3ac4d6d97335c627e790c1870558d1210
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58430
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
These changes include ELAN touchpad to ACPI tables and configure GPIO's.
BUG=None
Test=Boot board, touchpad should be functional
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: I78e5e133f7d3af47395819a79638a90fee4fd19e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
psp_efs.h now has embedded_firmware struct which is copied from
amdfwtool. Remove psp_ef_table from psp_verstage and use it instead to
remove duplicates.
TEST=boot on zork and guybrush
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: Ia362445cb7fc565b2d963f264461d833dc0338d0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Anahera has 4 thermal sensors, so add the missing sensors settings.
BUG=b:203187535
TEST=build and verified by thermal team.
Change-Id: I0e5c0d9c09c88cc95fdfd77b96800a0f4929d7d2
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58369
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Because of a change in the chromium OS kernel machine driver for
the MAX98357A, a _HID that matches MAX98360A has to be used.
(https://chromium-
review.googlesource.com/c/chromiumos/third_party/kernel/+/3070268/)
BUG=b:200778066
TEST=FW_NAME=anahera emerge-brya coreboot
Change-Id: Ic68373920d9135e614ff792149079de451ec6e60
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58365
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Based on the latest schematics, change eMMC CLKREQ from CLKREQ#2 to CLKREQ#6
BUG=b:197850509
TEST=build and boot into eMMC
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Change-Id: I0fc87c864b62a37fc3fa7a4a9a7722bf286c007b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58366
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Add supported memory parts in the mem_parts_used.txt and generate the
SPD ID for the memory parts. The memory parts being added are:
1. Samsung K4U6E3S4AB-MGCL
BUG=None
TEST=emerge-dedede coreboot
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Change-Id: I0720a51336f374f709c392c4bae4ad3e4c580a2f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Add supported memory parts in the mem_parts_used.txt and generate the
SPD ID for the memory parts. The memory parts being added are:
1. Samsung K4U6E3S4AB-MGCL
BUG=None
TEST=emerge-dedede coreboot
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Change-Id: I91183f33b92569dd49967ef866d58043d79c287b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58408
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Do not run or include any code in case the user did not explicitly
enable SGX through `SOC_INTEL_COMMON_BLOCK_SGX_ENABLE`.
Also move the ifdef inside the ASL file.
Change-Id: Iec4d3d3eb2811ec14d29aff9601ba325724bc28c
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58426
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tim Chu