GNUBoot/coreboot-kgpe-d16
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Author SHA1 Message Date
Stefan Reinauer
d1cb0eecd1 sb800: move spi prefetch and fast read mode to sb bootblock. 
So we don't waste time on the first cbfs scan.

Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
[adapt persimmon with the same change, and work around romcc bug
 in bootblock code: it doesn't like MEMACCESS[idx] |= value;]

Change-Id: Ic4d0e53d3102be0de0bd18b1b8b29c500bd6d997
Reviewed-on: http://review.coreboot.org/9
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Marc Jones <marcj303@gmail.com>
 2011-06-20 19:08:05 +02:00
Scott Duplichan
fb93178f13 Correct amd persimmon romstage code for early SPI prefetch enable. 
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Scott Duplichan <scott@notabs.org>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6601 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-20 17:50:14 +00:00
Scott Duplichan
20aad25e6e Move the ACPI FACP table to the front of the RSDT list. This is done to work around a Windows XP or Server 2003 setup failure where an error message such as: "An unexpected error (805262864) occurred at line 1768 of d:\xpclient\base\boot\setup\arcdisp.c" occurs. This change updates AMD reference board projects, but could applied to others as well. 
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6600 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-20 00:06:09 +00:00
Marc Jones
44d3c3dade Remove multiple mmconf settings and just use kconfig setting. 
Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6596 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-15 23:13:54 +00:00
Scott Duplichan
8c46263721 Cosmetic cleanup. 
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6594 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-15 22:10:15 +00:00
Scott Duplichan
5d878ad312 1) Remove unused kconfig options. 
2) Correct UMA graphics PCI device ID.

Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6593 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-15 22:09:09 +00:00
Scott Duplichan
a64ab46b62 Update gpp port configuration. 
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6592 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-15 22:07:56 +00:00
Scott Duplichan
769527e523 Enable rom cache early to reduce boot time. 
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6591 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-15 22:06:09 +00:00
Scott Duplichan
3c639e7df8 Fix memory allocation problem in amdInitLate. Disabled until further debug. 
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6590 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-15 22:05:00 +00:00
Scott Duplichan
0b886ae3c3 Remove some non-essential agesa options to reduce boot time. 
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6589 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-15 22:03:45 +00:00
Scott Duplichan
dbbbca3f33 Declare legacy video frame buffer so that Windows generic VGA driver will work. 
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6588 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-15 22:02:27 +00:00
Scott Duplichan
0ebefd27c8 Declare RTC as not PIIX4 compatible to match AMD hardware. 
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6587 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-15 22:00:23 +00:00
Scott Duplichan
254a6d6ea7 Make fadt revision match its length. Solves Windows 7 checked build assert. 
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6586 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-15 21:59:19 +00:00
Scott Duplichan
b7e068305c Enable SPI cacheline prefetch early to reduce boot time. 
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6585 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-15 21:56:03 +00:00
Scott Duplichan
2cc5f550c7 Enable SPI cacheline prefetch early to reduce boot time. 
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6584 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-15 21:54:04 +00:00
Scott Duplichan
d9a634c756 Switch processor cores to pstate 0 early to reduce boot time. 
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6583 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-15 21:51:31 +00:00
Scott Duplichan
e73fc20886 Enable 33 MHz fast mode SPI read early to reduce boot time. 
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6582 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-15 21:48:22 +00:00
Scott Duplichan
dc312cca53 Move mmconf base from e0000000 to f8000000 to avoid conflict with UMA BAR. 
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6578 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-15 21:26:04 +00:00
Scott Duplichan
444c49c68c Match DIMM SPD addressing to implemented slots. 
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6575 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-15 21:13:00 +00:00
Scott Duplichan
6719c23a47 Size mmconf according to CONFIG_MMCONF_BUS_NUMBER. 
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6574 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-15 21:11:41 +00:00
Scott Duplichan
b0b4063d6a 1) Use D18F1xF4 VGA Enable to simplify legacy video I/O support. 
2) Extend PCI MMIO limit from dfffffff to fecfffff.
3) Add AMD recommended non-posted mapping for SB800 legacy devices.

Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6573 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-15 21:10:20 +00:00
Scott Duplichan
6f7375c24c 1) Set I/O APIC ID according to BKDG recommendation 
2) Correct I/O APIC ID reported by mptable

Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6572 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-15 21:07:43 +00:00
Stefan Reinauer
42fa7fe28b run uart_init() from console_init, just like the other console initialization functions. 
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6531 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-04-20 20:54:07 +00:00
Sven Schnelle
91321028ec Use subsystem id from devicetree.cb instead of Kconfig and move 
all boards to the new config scheme.

Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Peter Stuge <peter@stuge.se>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6421 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-03-01 19:58:47 +00:00
Frank Vibrans
69da1b676c Add IBASE DB-FT1 and AMD Inagua motherboards. Patch 8 of 8. 
This code provides support for IBASE Technology DB-FT1 (AMD code name Persimmon) and AMD Inagua platforms. It is dependent on all other patches in this set.

Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6352 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-02-14 19:04:45 +00:00