Until now, autoport used to create a dummy "romstage.c", then write
romstage code to "early_southbridge.c". While it works, it makes more
sense to write to "romstage.c" instead, as virtually all mainboards do.
Change-Id: If9f9375f9a659e7e685de5f884163813261fa656
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28851
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
acpidump now creates dumps with 4 spaces instead of 2 in front of the hex dump,
so be a bit smarter about the input with regexp.
Tested with X220 autoport logs: Still creates the same coreboot code.
Change-Id: I8d48c09cdff9432f394b350540ea9765fc942781
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/28054
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Since only a handful of boards have descriptor blobs in the tree, it makes no
sense to have `HAVE_IFD_BIN` enabled by default then disabled on each mainboard.
This patch flips the default value of said variable, rendering all current
overrides unnecessary. The few boards which have an IFD in the blobs repo use
`select HAVE_IFD_BIN` to enable adding the IFD by default.
Since `HAVE_ME_BIN` depends on `HAVE_IFD_BIN`, the former has been removed
alongside the latter, and has been added to the boards with a ME blob as
`select HAVE_ME_BIN`.
Both `HAVE_IFD_BIN` and `HAVE_ME_BIN` have been removed from autoport as well.
Change-Id: I330c4886f8bea4b1a8ecad6505a0e5cc381654d1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/27218
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Descriptions are taken from the files themselves or READMEs. Description
followed by a space with the language in marked up as code.
Change-Id: I5f91e85d1034736289aedf27de00df00db3ff19c
Signed-off-by: Tom Hiller <thrilleratplay@gmail.com>
Reviewed-on: https://review.coreboot.org/27563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Use of device_t is deprecated.
Change-Id: I6adc0429ae9ecc8f726d6167a6458d9333dc515f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/27036
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Correct spelling mistakes and punctuation, and improve some wording.
Change-Id: I2c976bd62d8fa508373747b3fb3cf31490d5f631
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/25338
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
There are boards that don't use ports 0x62 and 0x66 for EC, e.g. Dell
Latitude E6230 uses 0x930 and 0x934.
Change-Id: Ie3005f5cd6e37206ef187267b0542efdeb26b3af
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/23430
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
As seen on ASUS P8Z77-V Pro
Change-Id: I9fce9a35174b5120f67c2345a0807db1b843eb48
Signed-off-by: Dan Elkouby <streetwalkermc@gmail.com>
Reviewed-on: https://review.coreboot.org/25661
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
ff4025c5f "sb/intel/bd82x6x: Reduce function-disable mess"
Removed most of the writes to RCBA(FD) and renamed the function to
mainboard_rcba_config.
Writes to FD are properly handled in ramstage, so no need to do it in
romstage.
Change-Id: I4edb75569ceec2d2f1308755a66d286202ca0ae6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23486
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The readme.md file was missing the instruction to also compile superiotool,
because autoport errors out without a working version of it.
Change-Id: Ic426b7312f68d59e2e0503d61da694adc9d4fb3f
Signed-off-by: Christoph Pomaska <cp_public@gmx.de>
Reviewed-on: https://review.coreboot.org/23282
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
This file is no longer there since ACPI pirq routing is now done in an
automated fashion in SSDT.
Change-Id: I8bafafbf670fe0fc2f20b46b5d8abee722931c6d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23323
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christoph Pomaska <cp_public@posteo.de>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This won't compile since '-' is an operator in C.
Change-Id: Icf900c959cbcbd0b07cd83a1f6866bf255fdcf01
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23321
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christoph Pomaska <cp_public@posteo.de>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The warning is printed using Printf syntax but actually Println is used
resulting in printing the format string first and the arguments second:
"%s. (%s) Default:%s WARNING: [...]"
Change-Id: I411fc47832dd7a82752f233c4909b98190340ccb
Signed-off-by: Maximilian Schander <coreboot@mimoja.de>
Reviewed-on: https://review.coreboot.org/22352
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
When autoport is run on a system without supported southbridge
it won't populate the coresponding data structure. By sanitiy
checking after PCI detection autoport can exit cleanly and
provide a sufficient error message.
Error was:
panic: runtime error: invalid memory address or nil pointer dereference
[signal SIGSEGV: segmentation violation code=0x1 addr=0x30 pc=0x4be595]
goroutine 1 [running]:
main.FIXMEEC(0xc42014af80, 0x14, 0xc42014afe0, 0x1a, 0xc4200a914f,
0x4, 0xc4200a916f, 0xf, 0xc420149e60, 0x28, ...)
/coreboot/util/autoport/ec_fixme.go:14 +0x105
Change-Id: I6b0fcda76d33b0d3a0379c279f492160ce5add84
Signed-off-by: Maximilian Schander <maxschander@googlemail.com>
Reviewed-on: https://review.coreboot.org/22203
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
The idea behind this not to enforce a license on autogenerated code
but is simply out of convenience in the case one wants to make the
result public (in which case it needs to have these license headers).
Change-Id: I1d6b48762b1249bb0becb178a30e1396bf6978fc
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19510
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This generates better gpio.c files where structs are initialised as
static to be able to drop some entries since those would be
initialised as 0.
This makes these files less cluttered since only relevant things are
shown:
* GPIO direction, level, invert, blink depend on GPIO mode
* GPIO level is read only on input
* GPIO invert is only valid on input
* only show when GPIO are inverted, blinking, reset by RSMRST#
Change-Id: I83382d38a4a3b7ed11b8e7077cc5fbe154e261a7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19508
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
AFAIR from reviews, writing the PMIR (aka. ETR3) register never turned
out to do anything useful.
Change-Id: I119fb1212f360a59b695e2dfef68e19c330d01ca
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/20817
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Sync map_oprom_vendev() and autoport with the list of PCI ids in the
`gma.c` driver, remove one obsolete Kconfig default override.
Change-Id: I12f24f415b695c516fbb947114e09c873af2e439
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/20814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
All affected boards did the same USE_NATIVE_RAMINIT distinction or
actually selected USE_NATIVE_RAMINIT. Also update autoport.
Change-Id: I924c43cec1e36e84db40e4b8e1dd0e05cad2b978
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/20813
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
The coreboot sites support HTTPS, and requests over HTTP with SSL are
also redirected. So use the more secure URLs, which also saves a
request most of the times, as nothing needs to be redirected.
Run the command below to replace all occurences.
```
$ git grep -l -E 'http://(www.|review.|)coreboot.org'
| xargs sed -i 's,http://\(.*\)coreboot.org,https://\1coreboot.org,g'
```
Change-Id: If53f8b66f1ac72fb1a38fa392b26eade9963c369
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/20034
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This adds one of the Xeon labeled PCI IDs used in Sandy-/Ivy Bridge
generation processors. This ID is used by the non-Xeon i7 3770K.
Change-Id: Iad7745136efeb10ff745001413f4ccb6488b5ec0
Signed-off-by: Omar Pakker <omarpakker+coreboot@gmail.com>
Reviewed-on: https://review.coreboot.org/19516
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The AFC—Additional Flash Control Register is set by
southbridge code.
Remove redundant calls and get rid of it in autoport.
Change-Id: I627082e09dd055e3b3c4dd8e0b90965a9fcb4342
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19493
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
This fixes the build for the generated code for boards with PS/2
keyboard, since commit 448e386309 updated the pc_keyboard_init()
function.
Change-Id: I776b49b847985296eaca4af6d6e49ab5d6abbafe
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/18242
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Variable name of inteltoolArgs was fixed.
The way of passing arguments to inteltool was changed from "-a -f"
to "-af" which is better as the string seems to be parsed
as a single argument.
Change-Id: I0c48fb1e912261748ba9e2b91c291bac28b9e856
Signed-off-by: Sebastian 'Swift Geek' Grzywna <swiftgeek@gmail.com>
Reviewed-on: https://review.coreboot.org/18050
Reviewed-by: Stefan Tauner <stefan.tauner@gmx.at>
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reorder drivers to fit src/drivers/[X]/[Y]/ scheme to make
them pluggable.
Also, fix up the following driver subdirectories by switching
to the src/drivers/[X]/[Y]/ scheme as these are hard requirements
for the main change:
* drivers/intel
* drivers/pc80
* drivers/dec
Change-Id: I455d3089a317181d5b99bf658df759ec728a5f6b
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14047
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Sandy and Ivy Bridge processors use the same socket, and a mainboard
with the socket can support both types of CPUs. However, they use
different native graphics init code for LVDS and cause a crash if
running the wrong code.
This change detects the CPU type and then selects the right code to
run. It will add some more code in ramstage. It also merges the
{SANDY,IVY}BRIDGE_LVDS symbol to one SANDYBRIDGE_IVYBRIDGE_LVDS.
Tested on a Lenovo T520 with i7-2630qm and i7-3720qm
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Change-Id: I4624759f9c92d56d547db1ab4b9a1d611a182a91
Reviewed-on: https://review.coreboot.org/12087
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Tested-by: build bot (Jenkins)
In accordance to change I8bd981c4696c174152cf41caefa6c083650d283a
change autoport as well, as suggested by Vladimir.
Change-Id: I7cdaa779c11fd3f791a3ad213c24d927b5da76b9
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/13731
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
In the same time remove few native gfx options which were improperly set
and only added dead code to the binary.
Change-Id: I4ed3fec03a1655ae0a779c3aa3845de273cb12e1
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13649
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
This is needed for stout EC init.
Change-Id: I5c73499c17763229840152a473a2d820802ee2f6
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13535
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
It encourages users from writing to the FSF without giving an address.
Linux also prefers to drop that and their checkpatch.pl (that we
imported) looks out for that.
This is the result of util/scripts/no-fsf-addresses.sh with no further
editing.
Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/11888
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Those are actually board specific. Keep the old value as defaults,
though. The defaults are included by all affected boards.
Change-Id: Ib865c7b4274f2ea3181a89fc52701b740f9bab7d
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/11705
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Only one value would work with corresponding gma code currently (which one
depends on board). Going forward, it's possible to compute which number can
be used, so there is no need to keep this info around.
Change-Id: Iadc77ef94b02f892860e3ae8d70a0a792758565d
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/11862
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Based on the info by Felix Held.
Change-Id: Iab84dd8a0e3c942da20a6e21db5510e4ad16cadd
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/11857
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This is a sad story. We have three different code paths for
sandybridge and ivybridge: proper native path, google MRC path, and,
everyone's favorite: Intel FSP path. For the purpose of this patch,
the FSP path lives in its own little world, and doesn't concern us.
Since MRC was first, when native files and variables were added, they
were suffixed with "_native" to separate them from the existing code.
This can cause confusion, as the suffix might make the native files
seem parasitical.
This has been bothering me for many months. MRC should be the
parasitical path, especially since we fully support native init, and
it works more reliably, on a wider range of hardware. There have been
a few board ports that never made it to coreboot.org because MRC would
hang.
gigabyte/ga-b75m-d3h is a prime example: it did not work with MRC, so
the effort was abandoned at first. Once the native path became
available, the effort was restarted and the board is now supported.
In honor of the hackers and pioneers who made the native code
possible, rename things so that their effort is the first class
citizen.
Change-Id: Ic86cee5e00bf7f598716d3d15d1ea81ca673932f
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11788
Tested-by: build bot (Jenkins)
Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
After commit with Change-Id Ia1839ed3 (sandy/ivy: Include
IRQ routes from platform), update autoport to include
that file into the DSDT.
Change-Id: I14534438d0b433895f384539c8b413eaa53d943a
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10612
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
cbfs_get_file_content was replaced with cbfs_boot_map_with_leak but
36f8d27ea9 failed to get it into account.
Change-Id: I0c7840043b2ea6abaf8e70f4bf1a63c96aedebc1
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10403
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
Previously I tried to see if Linux think that port 0x60 is in use by keyboard.
Unfortunately it always thinks that it is. Instead just base off real input
busses used.
Change-Id: I4bb744938f623d29f38396165a1694fee78c3d32
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10376
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
It was reversed between Lenovo and non-Lenovo cases.
Change-Id: I52c3b928abda2851e97ec0b40b7da5c5191217f5
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10374
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Apple is named Apple Inc in DMI but is "apple" in coreboot naming.
For other vendors we should follow similar pattern.
Change-Id: I7975b19faaf942c5bd44a704bcee994815499ceb
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10372
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
This allow an easy creation of standalone "autoport pack".
Change-Id: Ibe9e38aa3b4bbd7260104e1c2a11630790ff4d2f
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10370
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
This should be able to generate bootable ports for sandy/ivy, possible with
minor fixes. Howto is in readme.md
Change-Id: Ia126cf0939ef2dc2cdbb7ea100d2b63ea6b02f28
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7131
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Angel Pons