Commit Graph

8878 Commits

Author SHA1 Message Date
Paul Menzel ac6ea04b62 Lenovo ThinkPad T60: Add support for `EARLY_CBMEM_INIT` needed for CBMEM console
Add code to support `EARLY_CBMEM_INIT` needed for CBMEM console
support by copying GNUtoo’s commit for the Lenovo ThinkPad X60.

    commit 4560ca5003
    Author: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
    Date:   Fri Apr 26 12:21:41 2013 +0200

        Lenovo ThinkPad X60: Init CBMEM early for CBMEM console support.

        Reviewed-on: http://review.coreboot.org/3142

Change-Id: I0c4ca5a5e60f4bb3b91653a133ec71039fcca6ab
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3187
Tested-by: build bot (Jenkins)
Reviewed-by: Denis Carikli <GNUtoo@no-log.org>
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Nico Huber <nico.huber@secunet.com>
2013-05-26 18:01:22 +02:00
Gabe Black c6d1da0b18 snow: Add a name to the serial console UART choice block.
This allows other boards to have the same choice block without confusing
kconfig.

Change-Id: Iea5a7f2d1c263aa7992f504b832ca9c862833c3f
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3293
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2013-05-26 15:19:04 +02:00
Roman Zippel 330bb6acc8 kconfig: fix choice dependency check
Properly check the dependency of choices as a group.
Also fix that sym_check_deps() correctly terminates the dependency loop
error check (otherwise it would continue printing the dependency chain).

Signed-off-by: Roman Zippel <zippel@linux-m68k.org>
Signed-off-by: Sam Ravnborg <sam@ravnborg.org>

=======

Cherry-picked from the Linux kernel.

Change-Id: I0c98760dd0f55cf2ff70c53e0b014288b59574c8
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3290
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-26 11:50:11 +02:00
Roel Kluin 48757668a5 kconfig: reversed borderlines in inputbox
Fix reversal of dlg.border.atr and dlg.dialog.atr for draw_box()
Makes the inputbox look like expected

Signed-off-by: Roel Kluin <12o3l@tiscali.nl>
Signed-off-by: Sam Ravnborg <sam@ravnborg.org>

=======

Cherry-picked from the Linux kernel.

Change-Id: I596915aab0204ef0e392fefa56fad8e25204e207
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3289
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-26 11:49:30 +02:00
Roman Zippel 543aa7ba7b kconfig: add named choice group
As choice dependency are now fully checked, it's quite easy to add support
for named choices. This lifts the restriction that a choice value can only
appear once, although it still has to be within the same group,
but multiple choices can be joined by giving them a name.
While at it I cleaned up a little the choice type logic to simplify it a
bit.

Signed-off-by: Roman Zippel <zippel@linux-m68k.org>
Signed-off-by: Sam Ravnborg <sam@ravnborg.org>

=======

Cherry-picked from the Linux kernel.

Change-Id: If0f00d1783907d606220cda5307b8960d3bfc38d
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3291
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-26 11:49:12 +02:00
Ronald G. Minnich 5750fddcba Intel GM45, 945, SNB: Move `multiply_to_tsc()` to `tsc.h`
multiply_to_tsc was being copied everywhere, which is bad
practice. Put it in the tsc.h include file where it belongs.
Delete the copies of it.

Per secunet, no copyright notice is needed.

This might be a good time to get a copyright notice into tsc.h
anyway.

Change-Id: Ied0013ad4b1a9e5e2b330614bb867fd806f9a407
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/3242
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.huber@secunet.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-05-25 14:22:06 +02:00
Paul Menzel 60c54cc017 cpu/amd/agesa/Kconfig: Select LAPIC_MONOTONIC_TIMER
Thanks to Aaron Durbin coreboot provides monotonic timers. Select
the LAPIC monotonic timer for the AMD AGESA CPUs.

The following is an excerpt from serial log of the ASRock E350M1.

    $ grep usec seriallog-20130502_100902.log
    01.016: Root Device init 1578 usecs
    01.029: CPU_CLUSTER: 0 init 112415 usecs
    01.029: PCI: 00:00.0 init 3240 usecs
    01.088: PCI: 00:01.0 init 104572 usecs
    01.088: PCI: 00:01.1 init 1663 usecs
    01.088: PCI: 00:11.0 init 1662 usecs
    01.088: PCI: 00:14.0 init 1662 usecs
    01.088: PCI: 00:14.3 init 8665 usecs
    01.088: PCI: 00:14.4 init 1665 usecs
    01.088: PCI: 00:18.0 init 1662 usecs
    01.088: PCI: 00:18.1 init 1663 usecs
    01.088: PCI: 00:18.2 init 1663 usecs
    01.088: PCI: 00:18.3 init 1663 usecs
    01.088: PCI: 00:18.4 init 1663 usecs
    01.088: PCI: 00:18.5 init 1665 usecs
    01.088: PCI: 00:18.6 init 1664 usecs
    01.088: PCI: 00:18.7 init 1663 usecs
    01.088: PNP: 002e.2 init 1576 usecs
    01.088: PNP: 002e.5 init 1577 usecs
    01.088: PNP: 002e.a init 1590 usecs
    01.088: PNP: 002e.b init 30144 usecs
    01.088: PCI: 03:00.0 init 1663 usecs

So the graphics device needs around 100 ms for being initialized.

The full serial log is in the Gerrit comments.

Change-Id: Ia7b3012e51fcf94b0f22290cdef2b4424295ad6d
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3172
Tested-by: build bot (Jenkins)
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-05-24 08:11:57 +02:00
Paul Menzel 4e01cfb6d5 cpu/intel/haswell/Kconfig: Intend help text with two spaces
Commit »haswell: 24MHz monotonic time implementation« (c46cc6f1) [1]
added the Kconfig variable `MONOTONIC_TIMER_MSR` with a help text,
but only used one space instead of the suggested two spaces for
indentation. So add one space.

»Lines under a "config" definition are indented with one tab, while
help text is indented an additional two spaces.« [2]

[1] http://review.coreboot.org/3153
[2] https://www.kernel.org/doc/Documentation/CodingStyle
    (Chapter 10: Kconfig configuration files)

Change-Id: I39cf356bfd54c66a2f1b837c6667dcc915e41f29
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3262
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-05-24 07:57:33 +02:00
Paul Menzel 87b9bf5bad include/timer.h: Fix typo in in*iti*alize in comment
Correct a typo in a comment introduced in commit »coreboot:
introduce monotonic timer API« (a421791d) [1].

[1] http://review.coreboot.org/3152

Change-Id: Ia0abc5304547d419478db1ae37b5525406fa19cc
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3261
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-05-23 20:17:37 +02:00
Paul Menzel 51837f9dac Intel Sandy Bridge: udelay.c: Change comparison from <= to <
Currently code in `udelay.c` differs between the Intel northbridges
GM45, 945 on the one hand and Sandy Bridge on the other hand.

The reason for this is that a wrong comparison > was used.

The following commit

    commit 784ffb3db6
    Author: Sven Schnelle <svens@stackframe.org>
    Date:   Tue Jan 10 12:16:38 2012 +0100

        i945: fix tsc udelay()

        Reviewed-on: http://review.coreboot.org/530

fixed the sign from > to <, whereas Stefan Reinauer changed it from
> to <= before adding the Sandy Bridge port in the following commit.

    commit 00636b0dae
    Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Date:   Wed Apr 4 00:08:51 2012 +0200

        Add support for Intel Sandybridge CPU (northbridge part)

        Reviewed-on: http://review.coreboot.org/854

As there are no technical reasons for this difference, unify this
between the chipsets. See the discussion of the other patch set in
Gerrit [1].

[1] http://review.coreboot.org/#/c/3220/1/src/northbridge/intel/i5000/udelay.c

Change-Id: I64f2aa1db114ad2e9f34181c5f3034f6a8414a11
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3259
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.huber@secunet.com>
2013-05-23 10:44:36 +02:00
Paul Menzel 1e24f4b37f Kconfig: Remove duplicate entry for `USE_OPTION_TABLE`
The following commit

    commit eb50c7d922
    Author: Edwin Beasant <edwin_beasant@virtensys.com>
    Date:   Tue Jul 6 21:05:04 2010 +0000

    Re-integrate "USE_OPTION_TABLE" code.

added a duplicate entry `config USE_OPTION_TABLE`. Remove it again.

Change-Id: I3ff64c360bad531439e74fa1b25a06c4a447a33f
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3165
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-05-23 10:42:41 +02:00
Nico Huber 393619b9a6 intel/gm45: Add more debug output to read/write training
Add debug output for the timing values of the edges found during
read and write training.

Now, output for one DIMM of DDR3-1066 in a roda/rk9 looks like:

[...]
Lower bound for byte lane 0 on channel 0: 0.0
Upper bound for byte lane 0 on channel 0: 8.4
Final timings for byte lane 0 on channel 0: 4.2
Lower bound for byte lane 1 on channel 0: 0.0
Upper bound for byte lane 1 on channel 0: 10.2
Final timings for byte lane 1 on channel 0: 5.1
Lower bound for byte lane 2 on channel 0: 0.0
Upper bound for byte lane 2 on channel 0: 7.5
Final timings for byte lane 2 on channel 0: 3.6
Lower bound for byte lane 3 on channel 0: 0.0
Upper bound for byte lane 3 on channel 0: 11.4
Final timings for byte lane 3 on channel 0: 5.6
Lower bound for byte lane 4 on channel 0: 0.0
Upper bound for byte lane 4 on channel 0: 9.4
Final timings for byte lane 4 on channel 0: 4.6
Lower bound for byte lane 5 on channel 0: 0.0
Upper bound for byte lane 5 on channel 0: 11.2
Final timings for byte lane 5 on channel 0: 5.5
Lower bound for byte lane 6 on channel 0: 0.0
Upper bound for byte lane 6 on channel 0: 8.4
Final timings for byte lane 6 on channel 0: 4.2
Lower bound for byte lane 7 on channel 0: 0.0
Upper bound for byte lane 7 on channel 0: 10.4
Final timings for byte lane 7 on channel 0: 5.2
Lower bound for group 0 on channel 0: 1.7.5
Upper bound for group 0 on channel 0: 2.2.2
Final timings for group 0 on channel 0: 1.10.7
Lower bound for group 1 on channel 0: 1.6.1
Upper bound for group 1 on channel 0: 2.0.2
Final timings for group 1 on channel 0: 1.9.1
Lower bound for group 2 on channel 0: 2.0.7
Upper bound for group 2 on channel 0: 2.8.1
Final timings for group 2 on channel 0: 2.4.4
Lower bound for group 3 on channel 0: 2.4.7
Upper bound for group 3 on channel 0: 3.0.0
Final timings for group 3 on channel 0: 2.8.3
[...]

Final timings are always the average of the two bounds. The last dots
separate eights (not decimals) and the middles are elenvenths or twelfths
depending on the clock speed (twelfths in this case).

Change-Id: Idb7c84b514716c7265b94890c39b7225de7800dc
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3257
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-05-22 18:07:22 +02:00
Nico Huber 12276acfd7 intel/gm45: Handle overflows during DDR3 write training
We halted the machine on any overflow during the write training.
However, overflows during the search for a good to bad edge are
non-fatal, and should be ignored.

Change-Id: I45ccbabc214e208974039246d806b0d2ca2fdc03
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3256
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-05-22 18:05:34 +02:00
Nico Huber 08bee23f7e intel/gm45: Refactor DDR3 write training
Split some code in individual functions. It's the refactoring part of
a bigger change, following...

Change-Id: Id19be4588ad8984935040d9bcba4d7c5f2e1114f
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3255
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-05-22 18:04:11 +02:00
Nico Huber 35e45c0780 intel/gm45: Handle overflows during DDR3 read training
We halted the machine on any overflow during the read training. However,
overflows during the search for a good to bad edge are non-fatal, and
should be ignored.

Change-Id: I77085840ade25bce955480689c84603334113d1f
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3254
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-05-22 18:02:24 +02:00
Nico Huber 26a6435123 intel/gm45: Refactor DDR3 read training
Split some code in individual functions. It's the refactoring part of
a bigger change, following...

Change-Id: Ied551a011eaf22f6f8f6db0044de3634134f0b37
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3253
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-05-22 18:00:56 +02:00
Nico Huber 0da92863a7 intel/gm45: Fix interpretation of VT-d disable bit
When configuring the GTT size for the integrated graphics, the state
of VT-d was read wrong. Bit 48 of CAPID0 (D0F0) is set when VT-d is
_disabled_.

In the log of a VT-d enabled roda/rk9 we have now:

[...]
VT-d enabled
[...]
IGD decoded, subtracting 32M UMA and 4M GTT
[...]

Without this patch, only 2M GTT were reported.

Change-Id: I87582c18f4769c2a05be86936d865c0d1fb35966
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3252
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-05-22 17:59:10 +02:00
Nico Huber 0f43af2ebb intel/i5000: Remove unused copy of udelay.c
It's a copy from i945 and looks like not beeing included in a
build at all.

If you should ever want to use that file for the Intel 5000,
please copy it from another chipset like the Intel 945 as it
is going to be improved.

Change-Id: I5c113bb0b2fed7b93feb3dcb1b5d962e1442963a
Reported-by: Ronald G. Minnich <rminnich@gmail.com>
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3219
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Sven Schnelle <svens@stackframe.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-21 17:46:02 +02:00
Paul Menzel 883b03f323 AMD AGESA Hudson: Include `stdint.h` and `io.h` to fix build
Apparently the files `smbus.{h,c}`, where never used and therefore
build beforehand. Needing one function in them for the ASUS F2A85-M
the build fails as some headers are missing. Including the headers
`stdint.h` and `io.h` fixes the following errors.

    […]
        CC         southbridge/amd/agesa/hudson/smbus.romstage.o
    In file included from src/southbridge/amd/agesa/hudson/smbus.c:23:0:
    src/southbridge/amd/agesa/hudson/smbus.h:67:24: error: unknown type name 'u32'
    src/southbridge/amd/agesa/hudson/smbus.h:67:43: error: unknown type name 'u32'
    src/southbridge/amd/agesa/hudson/smbus.h:67:55: error: unknown type name 'u32'
    src/southbridge/amd/agesa/hudson/smbus.h:68:25: error: unknown type name 'u32'
    src/southbridge/amd/agesa/hudson/smbus.h:68:44: error: unknown type name 'u32'
    src/southbridge/amd/agesa/hudson/smbus.h:68:56: error: unknown type name 'u32'
    src/southbridge/amd/agesa/hudson/smbus.h:68:69: error: unknown type name 'u8'
    src/southbridge/amd/agesa/hudson/smbus.h:69:24: error: unknown type name 'u32'
    src/southbridge/amd/agesa/hudson/smbus.h:69:43: error: unknown type name 'u32'
    src/southbridge/amd/agesa/hudson/smbus.h:70:24: error: unknown type name 'u32'
    src/southbridge/amd/agesa/hudson/smbus.h:70:43: error: unknown type name 'u32'
    src/southbridge/amd/agesa/hudson/smbus.h:70:55: error: unknown type name 'u8'
    src/southbridge/amd/agesa/hudson/smbus.h:71:20: error: unknown type name 'u32'
    src/southbridge/amd/agesa/hudson/smbus.h:71:35: error: unknown type name 'u32'
    src/southbridge/amd/agesa/hudson/smbus.h:71:49: error: unknown type name 'u32'
    src/southbridge/amd/agesa/hudson/smbus.h:71:59: error: unknown type name 'u32'
    src/southbridge/amd/agesa/hudson/smbus.h:71:69: error: unknown type name 'u32'
    src/southbridge/amd/agesa/hudson/smbus.h:72:20: error: unknown type name 'u32'
    src/southbridge/amd/agesa/hudson/smbus.h:72:35: error: unknown type name 'u32'
    src/southbridge/amd/agesa/hudson/smbus.h:72:49: error: unknown type name 'u32'
    src/southbridge/amd/agesa/hudson/smbus.h:72:59: error: unknown type name 'u32'
    src/southbridge/amd/agesa/hudson/smbus.h:73:20: error: unknown type name 'u32'
    src/southbridge/amd/agesa/hudson/smbus.h:73:32: error: unknown type name 'u32'
    src/southbridge/amd/agesa/hudson/smbus.h:73:44: error: unknown type name 'u32'
    src/southbridge/amd/agesa/hudson/smbus.h:73:54: error: unknown type name 'u32'
    src/southbridge/amd/agesa/hudson/smbus.c: In function 'smbus_delay':
    src/southbridge/amd/agesa/hudson/smbus.c:27:2: error: implicit declaration of function 'outb' [-Werror=implicit-function-declaration]
    src/southbridge/amd/agesa/hudson/smbus.c:27:2: error: implicit declaration of function 'inb' [-Werror=implicit-function-declaration]
    […]

Probably all the (AMD(?)) `smbus.{h,c}` suffer from this and
should be fixed. Even better, as these function do not differ
between most boards, the file should be moved out from the
specific southbridge directories.

[1] http://qa.coreboot.org/job/coreboot-gerrit/6168/testReport/junit/(root)/board/i386_asus_f2a85_m/

Change-Id: I285101fa06a365da44fa27b688c536e614d57f50
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3202
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2013-05-20 18:34:18 +02:00
Paul Menzel b2cddd4c12 ASUS F2A85-M: romstage.c: Set RAM voltage for non 1.5 Volt case
Currently the code in the if statement

    if (!byte)
    	do_smbus_write_byte(0xb20, 0x15, 0x3, byte);

only gets executed if `byte == 0x0`, that means only in the
default case where RAM voltage is 1.5 Volts. But the RAM voltage
should be changed when configured for the non-default case.

So negate the predicate to alter the RAM voltage for the
non-default cases.

To prevent the build error

    OBJCOPY    cbfs/fallback/coreboot_ram.elf
    coreboot-builds/asus_f2a85-m/generated/crt0.romstage.o: In function `cache_as_ram_main':
    /srv/jenkins/.jenkins/jobs/coreboot-gerrit/workspace/src/mainboard/asus/f2a85-m/romstage.c:106: undefined reference to `do_smbus_write_byte'
    collect2: error: ld returned 1 exit status
    make: *** [coreboot-builds/asus_f2a85-m/cbfs/fallback/romstage_null.debug] Error 1

add `southbridge/amd/agesa/hudson/smbus.c` providing the function
`do_smbus_write_byte` to ROM stage in `Makefile.inc`. That can
actually be used after the needed header files are included in a
previous commit.

Change-Id: I89542479c4cf6d412614bcf4586ea98e097328d6
Reported-by: David Hubbard <david.c.hubbard+coreboot@gmail.com>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3200
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-05-20 18:33:23 +02:00
Nico Huber 963bed546f Make: Use unaltered object list for dependency inclusion
It looks like the inclusion of dependency files was broken for all
ramstage objects since the list of those gets processed through the
ramstage-postprocess macro. Fix that by taking the unaltered list
for dependency files.

The output of `make printall` (look for DEPENDENCIES=) shows which
dependency files will be included.

See also:

    commit 79f9010e80
    Author: Patrick Georgi <patrick@georgi-clan.de>
    Date:   Sun Nov 25 14:31:08 2012 +0100

        build system: Add hook to postprocess classes (object lists)

and:

    commit f33e395213
    Author: Patrick Georgi <patrick@georgi-clan.de>
    Date:   Sun Nov 25 17:10:47 2012 +0100

        build system: Split linking into multiple steps

Change-Id: If93b1773c5d53240f98382aab11bf7f5a4649ee8
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3258
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-05-20 10:28:25 +02:00
Stefan Reinauer b0fb2234be Drop llshell
This feature has not been used and was never fully integrated.
In the progress of cleaning up coreboot, let's drop it.

Change-Id: Ib40acdba30aef00a4a162f2b1009bf8b7db58bbb
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/3251
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-20 08:42:28 +02:00
Bruce Griffith d433acb816 AMD Inagua: PlatformGnbPcie.c: Allocate exact needed size for buffer
The following commit

    commit 05f3b117dd
    Author: Paul Menzel <paulepanter@users.sourceforge.net>
    Date:   Tue May 14 09:28:26 2013 +0200

        AMD Inagua: PlatformGnbPcie.c: Allocate exact needed size for buffer

        Reviewed-on: http://review.coreboot.org/3246

changed one calculation for the size of the array PortList[] to
reflect only four elements, but neglected three additional calculations
of the size of the same table.

Correct that by setting the size for four array elements in all four
calculations.

[1] http://review.coreboot.org/#/c/3239/3/src/mainboard/amd/inagua/PlatformGnbPcie.c

Change-Id: Ib66b7b2b388d847888663e9eb6d1c8c9d50b9939
Reported-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/3250
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-05-17 18:50:23 +02:00
Paul Menzel 05f3b117dd AMD Inagua: PlatformGnbPcie.c: Allocate exact needed size for buffer
The following commit

    commit d0790694b0
    Author: Kerry Sheh <shekairui@gmail.com>
    Date:   Thu Jan 19 13:18:37 2012 +0800

        Inagua: Inagua GNB ddi lanes and pcie lanes config update

        Reviewed-on: http://review.coreboot.org/544

assigns lanes 4 and 5 to PCI device number 4, but does not
adapt the rest of the code.

After the commit above, the array `PortList []` only has four
elements, but the buffer size `AllocHeapParams.RequestedBufferSize`
is set to a size as it still has five elements.

Correct that by setting the size for four array elements.

[1] http://review.coreboot.org/#/c/3239/3/src/mainboard/amd/inagua/PlatformGnbPcie.c

Change-Id: I3ff07f308ffd417d2bf73117eda9da2a1a05f199
Reported-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3246
Tested-by: build bot (Jenkins)
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2013-05-16 06:06:50 +02:00
Aaron Durbin 5b54d353aa haswell: enable cache-as-ram migration
The haswell code allows for vboot ramstage verification.
However, that code path relies on accessing global cache-as-ram
variables after cache-as-ram is torn down. In order to avoid
that situation enable cache-as-ram migration.

cbmemc_reinit() no longer needs to be called from romstage
because it is invoked automatically by the cache-as-ram
migration infrastructure.

Change-Id: I08998dca579c167699030e1e24ea0af8802c0758
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/3236
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-05-16 01:30:25 +02:00
Aaron Durbin 2ad6bd23a7 cbmem console: use cache-as-ram API and cleanup
Allow for automatic cache-as-ram migration for the cbmem
console. The code was refactored in the thought of making
it easier to read. The #ifdefs still exist, but they are no
longer sprinkled throughout the code. The cbmem_console_p
variable now exists globally in both romstage and ramstage.
However, the cbmem_console_p is referenced using the
cache-as-ram API. When cbmem is initialized the console
is automatically copied over by calling cbmemc_reinit()
through a callback.

Change-Id: I9f4a64e33c58b8b7318db27942e37c13804e6f2c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/3235
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-05-16 01:30:17 +02:00
Aaron Durbin 677e1558c3 chromeos: use cache-as-ram migration API for vbnv
It's possible that the vbnv global variables may be accessed
in romstage after cache-as-ram is torn down. Therefore use
the cache-as-ram migration API. Wrappers were written to
wrap the API to keep the existing code as close as possible.

Change-Id: Ia1d8932f98e00def0a44444a1ead0018a59d3d98
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/3234
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-05-16 01:30:09 +02:00
Aaron Durbin cb997d3710 pc80/tpm: allow for cache-as-ram migration
As the TPM driver can be accessed in romstage after
cache-as-ram is torn down use the cache-as-ram migration
API to dynamically determine the global variable address.

Change-Id: I149d7c130bc3677ed52282095670c07a76c34439
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/3233
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-05-16 01:29:59 +02:00
Aaron Durbin 716738a6b8 x86: add cache-as-ram migration option
There are some boards that do a significant amount of
work after cache-as-ram is torn down but before ramstage
is loaded. For example, using vboot to verify the ramstage
is one such operation. However, there are pieces of code
that are executed that reference global variables that
are linked in the cache-as-ram region. If those variables
are referenced after cache-as-ram is torn down then the
values observed will most likely be incorrect.

Therefore provide a Kconfig option to select cache-as-ram
migration to memory using cbmem. This option is named
CAR_MIGRATION. When enabled, the address of cache-as-ram
variables may be obtained dynamically. Additionally,
when cache-as-ram migration occurs the cache-as-ram
data region for global variables is copied into cbmem.
There are also automatic callbacks for other modules
to perform their own migration, if necessary.

Change-Id: I2e77219647c2bd2b1aa845b262be3b2543f1fcb7
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/3232
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-05-16 01:29:50 +02:00
Dave Frodin adc300d88b libpayload: Fix the logic for hardware-less serial consoles
This fixes the configuration where serial console output is
being sent to non-existant hardware to be captured with I/O
trapping. In this configuration where there isn't serial
hardware present we still want to init the consoles. We just
never want to read non-existant hardware.

Change-Id: Ic51dc574b9c0df3f6ed071086b0fb2119afedc44
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/3249
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-15 16:56:33 +02:00
Ronald G. Minnich 4bd7b0cbad EXYNOS5250/SNOW: fix the build script. Add a script to get the bl1.
build-snow got broken when the snow makefile improved. So fix it.

While we're at it, create a script like the update-microcode
scripts that gets the bl1. I thought about making this a common
script but the various names and paths always evolve, leaving
me thinking it's not worth it. This script is just a
piece of the snow build script.

Change-Id: I65c0f8697a978c62fe12533c4f0152d14dbaefda
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/3238
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-05-14 22:03:07 +02:00
Paul Menzel 3a1457137e AMD Fam15tn boards: BiosCallOuts.c: Declare codec arrays as `static`
These arrays are declared as `static` for AMD SB800 based boards,
so do the same for this generation.

Rudolf Marek just changed `const CODEC_TBL_LIST` to `static const`
in [1]. Adapt all Fam15tn based boards (AMD Parmer, AMD Thatcher,
ASUS F2A85-M) to keep the differences between them small.

[1] http://review.coreboot.org/#/c/3170/3/src/mainboard/asus/f2a85-m/BiosCallOuts.c

Change-Id: I353b38bd8bc77ba500a4b7fe9250e9aa3071c530
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3198
Tested-by: build bot (Jenkins)
2013-05-14 15:58:34 +02:00
Rudolf Marek cd1cef4438 AMD Fam15tn boards: Document lane ID mapping from BKDG
To make it easier to fill in the values, place the table
from the BIOS and Kernel Developer’s Guide (BKDG) [1]
as a comment.

[1] http://www.coreboot.org/Datasheets#AMD_Fam15

Change-Id: I218f76e9fa2dc88d47af51ea6c062e315afb0000
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3221
Tested-by: build bot (Jenkins)
2013-05-14 15:53:14 +02:00
Aaron Durbin 38c326d041 x86: add thread support
Thread support is added for the x86 architecture. Both
the local apic and the tsc udelay() functions have a
call to thread_yield_microseconds() so as to provide an
opportunity to run pending threads.

Change-Id: Ie39b9eb565eb189676c06645bdf2a8720fe0636a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/3207
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-14 05:24:18 +02:00
Aaron Durbin 4409a5eef6 coreboot: add thread cooperative multitasking
The cooperative multitasking support allows the boot state machine
to be ran cooperatively with other threads of work. The main thread
still continues to run the boot state machine
(src/lib/hardwaremain.c).  All callbacks from the state machine are
still ran synchronously from within the main thread's context.
Without any other code added the only change to the boot sequence
when cooperative multitasking is enabled is the queueing of an idlle
thread. The idle thread is responsible for ensuring progress is made
by calling timer callbacks.

The main thread can yield to any other threads in the system. That
means that anyone that spins up a thread must ensure no shared
resources are used from 2 or more execution contexts. The support
is originally intentioned to allow for long work itesm with busy
loops to occur in parallel during a boot.

Note that the intention on when to yield a thread will be on
calls to udelay().

Change-Id: Ia4d67a38665b12ce2643474843a93babd8a40c77
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/3206
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-14 05:18:47 +02:00
Paul Menzel 8c8af592ca AMD Brazos/Trinity boards: PlatformGnbPcie.c: Reserve correct amount of memory
In `PlatformGnbPcie.c` AGESA functions are used to reserve memory
space to save the PCIe configuration to. This is the

With the following definitions in `AGESA.h`

    $ more src/vendorcode/amd/agesa/f14/AGESA.h
    […]
    /// PCIe port descriptor
    typedef struct {
      IN       UINT32               Flags;                    /**< Descriptor flags
                                                               * @li @b Bit31 - last descriptor in complex
                                                               */
      IN       PCIe_ENGINE_DATA     EngineData;               ///< Engine data
      IN       PCIe_PORT_DATA       Port;                     ///< PCIe port specific configuration info
    } PCIe_PORT_DESCRIPTOR;

    /// DDI descriptor
    typedef struct {
      IN       UINT32               Flags;                    /**< Descriptor flags
                                                               * @li @b Bit31 - last descriptor in complex
                                                               */
      IN       PCIe_ENGINE_DATA     EngineData;               ///< Engine data
      IN       PCIe_DDI_DATA        Ddi;                      ///< DDI port specific configuration info
    } PCIe_DDI_DESCRIPTOR;

    /// PCIe Complex descriptor
    typedef struct {
      IN       UINT32               Flags;                    /**< Descriptor flags
                                                               * @li @b Bit31 - last descriptor in topology
                                                               */
      IN       UINT32               SocketId;                 ///< Socket Id
      IN       PCIe_PORT_DESCRIPTOR *PciePortList;            ///< Pointer to array of PCIe port descriptors or NULL (Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST).
      IN       PCIe_DDI_DESCRIPTOR  *DdiLinkList;             ///< Pointer to array DDI link descriptors (Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST).
      IN       VOID                 *Reserved;                ///< Reserved for future use
    } PCIe_COMPLEX_DESCRIPTOR;
    […]

memory has to be reserved for the `PCIe_COMPLEX_DESCRIPTOR` and,
as two struct members are pointers to arrays with elements of type
`PCIe_PORT_DESCRIPTOR` and `PCIe_DDI_DESCRIPTOR`, space for these
times the number of array elements have to be reserved:
a + b * 5 + c * 2.

      sizeof(PCIe_COMPLEX_DESCRIPTOR)
    + sizeof(PCIe_PORT_DESCRIPTOR) * 5
    + sizeof(PCIe_DDI_DESCRIPTOR) * 2;

But for whatever reason parentheses were put in there making this
calculation incorrect and reserving too much memory.

    (a + b * 5 + c) * 2

So, remove the parentheses to reserve the exact amount of memory
needed.

The ASRock E350M1 still boots with these changes. No changes were
observed as expected.

Rudolf Marek made this change as part of his patch »ASUS F2A85-M:
Correct and clean up PCIe config« [1]. Factor this hunk out as it
affects all AMD Brazos and Trinity based boards.

[1] http://review.coreboot.org/#/c/3194/

Change-Id: I32e8c8a3dfc5e87eb119eb17719d612e57e0817a
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3239
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2013-05-14 04:49:03 +02:00
Peter Stuge c49ae3c655 Revert "PC Engines ALIX.1C: Add CMOS defaults."
Revert commit f90071faee [1] as
it was merged without its dependencies and therefore the source
tree currently does not build [2][3].

        OPTION     option_table.h
        GEN        build.h
        SCONFIG    mainboard/pcengines/alix1c/devicetree.cb
        CC         arch/x86/lib/cbfs_and_run.romstage.o
        CC         arch/x86/lib/memcpy.romstage.o
        CC         arch/x86/lib/memset.romstage.o
        CC         arch/x86/lib/rom_media.romstage.o
        CC         arch/x86/lib/romstage_console.romstage.o
        CC         console/die.romstage.o
        CC         console/post.romstage.o
        CC         console/vtxprintf.romstage.o
        CC         device/device_romstage.romstage.o
        CC         lib/cbfs.romstage.o
        CC         lib/compute_ip_checksum.romstage.o
        CC         lib/gcc.romstage.o
        CC         lib/lzma.romstage.o
        CC         lib/memchr.romstage.o
        CC         lib/memcmp.romstage.o
        CC         lib/memmove.romstage.o
        CC         lib/ramtest.romstage.o
        CC         lib/uart8250.romstage.o
        CC         southbridge/amd/cs5536/smbus.romstage.o
        ROMCC      generated/bootblock.inc
        GEN        generated/bootblock.ld
    make: *** No rule to make target `nvramtool', needed by `coreboot-builds/pcengines_alix1c/coreboot.pre1'.  Stop.
    make: *** Waiting for unfinished jobs....
        OPTION     cmos_layout.bin

[1] http://review.coreboot.org/#/c/3229/
[2] http://www.coreboot.org/pipermail/coreboot/2013-May/075864.html
[3] http://qa.coreboot.org/job/coreboot-gerrit/6251/testReport/junit/(root)/board/i386_pcengines_alix1c/

Change-Id: I4764d90c39ccdb4dc7e7a9aef7525c306614e1a8
Signed-off-by: Peter Stuge <peter@stuge.se>
Reviewed-on: http://review.coreboot.org/3245
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-05-12 20:42:20 +02:00
Peter Stuge 08d0baa77a Revert "Asus M4A785T-M: Add CMOS defaults."
Revert commit b8b3e8bff3 [1] as
it was merged without its dependencies and therefore the source
tree currently does not build [2][3].

        OPTION     option_table.h
        SCONFIG    mainboard/asus/m4a785t-m/devicetree.cb
    make: *** No rule to make target `nvramtool', needed by `coreboot-builds/asus_m4a785t-m/coreboot.pre1'.  Stop.
    make: *** Waiting for unfinished jobs....
        OPTION     cmos_layout.bin

[1] http://review.coreboot.org/3224
[2] http://www.coreboot.org/pipermail/coreboot/2013-May/075864.html
[3] http://qa.coreboot.org/job/coreboot-gerrit/6251/testReport/junit/(root)/board/i386_asus_m4a785t_m/

Change-Id: I8bf33b62b56627f0eea9440ff5e5136e4122ef01
Signed-off-by: Peter Stuge <peter@stuge.se>
Reviewed-on: http://review.coreboot.org/3244
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-05-12 20:41:39 +02:00
Duncan Laurie d289852741 Remove the wtm1 mainboard
This was an early bring-up reference board for ULT but it is no
longer being worked on and was never complete enough to be useful
and I no longer have a board so it is already stale and untested.

All ULT bring-up work has moved to the wtm2 mainboard instead.

Change-Id: If64d61bf7a3fc8c9e16096ffc28fa4128aa99477
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/48897
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/3231
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-05-11 20:21:05 +02:00
Denis 'GNUtoo' Carikli f90071faee PC Engines ALIX.1C: Add CMOS defaults.
After removing power and the CMOS Battery, putting it back
  and booting coreboot we have:
    # ./nvramtool -a
    boot_option = Fallback
    last_boot = Fallback
    ECC_memory = Disable
    baud_rate = 115200
    power_on_after_fail = Disable
    debug_level = Spew
    boot_first = HDD
    boot_second = Fallback_Floppy
    boot_third = Fallback_Network
    boot_index = 0xf
    boot_countdown = 0x7f
    nvramtool: Warning: Coreboot CMOS checksum is bad.

Change-Id: Iba2701d4611cd2c2e5a2d76d41ffc23ed65574e8
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/3229
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-11 05:20:22 +02:00
Martin Roth 33cde9a0ba Make early x86 POST codes written to IO port optional
This continues the work done in patch 6b908d08ab
http://review.coreboot.org/#/c/1685/
and makes the early x86 post codes follow the same options.

Change-Id: Idf0c17b27b3516e79a9a53048bc203245f7c18ff
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/3237
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-11 05:19:31 +02:00
Duncan Laurie c1ef740d88 haswell: Fix VGA option rom INT15 handler
The format of this function changed but was not updated in
all mainboards.  This fixes BaskingRidge and WTM2.

The int15 handler no longer takes a regs structure as an
argument and instead uses global variables.  The yabel interface
is now similar enough that we can drop the duplicate handler.

Change-Id: Ia717ae14f99cee6d83ccdb1e26b9d7defe1638c4
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/48896
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/3230
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-11 00:15:30 +02:00
Stefan Reinauer ec664bcfa4 romcc: support attribute((packed))
right now this is just a fake option to get rid of ifdefs in
coreboot's code.

Change-Id: I59233f3c1d266b4e716a5921e9db298c7f96751d
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/3225
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2013-05-10 19:33:00 +02:00
Ronald G. Minnich 711a6fde0d Get rid of MAXIMUM_CONSOLE_LOGLEVEL; compile all messages into the coreboot binary
This option has never had much if any use. It solved a problem over 10
years ago that resulted from an argument over the value or lack thereof
of including all the debug strings in a coreboot image. The answer is
in: it's a good idea to maintain the capability to print all messages,
for many reasons.

This option is  also misleading people, as in a recent discussion, to
believe that log messges are controlled at build time in a way they are
not. For the record, from this day forward, we can print messages at all
log levels and the default log level is set at boot time, as directed by
DEFAULT_CONSOLE_LOGLEVEL. You can set the default to 0 at build time and
if you are having trouble override it in CMOS and get more messages.

Besides, a quick glance shows it's always set to max (9 in this case) in
the very few cases (1) in which it is set.

Change-Id: I60c4cdaf4dcd318b841a6d6c70546417c5626f21
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/3188
Tested-by: build bot (Jenkins)
2013-05-10 17:33:49 +02:00
Stefan Reinauer c5e036a043 Get rid of a number of __GNUC__ checks
In the process of streamlining coreboot code and getting
rid of unneeded ifdefs, drop a number of unneeded checks
for the GNU C compiler. This also cleans up x86emu/types.h
significantly by dropping all the duplicate types in there.

Change-Id: I0bf289e149ed02e5170751c101adc335b849a410
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/3226
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2013-05-10 17:31:31 +02:00
Denis 'GNUtoo' Carikli b8b3e8bff3 Asus M4A785T-M: Add CMOS defaults.
After removing power and the CMOS Battery, putting it back
  and booting coreboot we have:
    # ./nvramtool -a
    boot_option = Fallback
    last_boot = Fallback
    ECC_memory = Enable
    baud_rate = 115200
    hw_scrubber = Enable
    interleave_chip_selects = Enable
    max_mem_clock = 400Mhz
    multi_core = Enable
    power_on_after_fail = Disable
    debug_level = Spew
    boot_first = HDD
    boot_second = Fallback_Floppy
    boot_third = Fallback_Network
    boot_index = 0xf
    boot_countdown = 0xc
    slow_cpu = off
    nmi = Enable
    iommu = Enable
    nvramtool: Can not read coreboot parameter user_data because layout info specifies CMOS area that is too wide.
    nvramtool: Warning: Coreboot CMOS checksum is bad.

Change-Id: Ifa09c7a468e3e0713b426763266ae633e67d8397
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/3224
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-10 17:27:05 +02:00
Siyuan Wang e04dc7529f AMD Thatcher: remove unused macros in PlatformGnbPcieComplex.h
The macros GNB_GPP_PORTx_PORT_PRESENT, GNB_GPP_PORTx_SPEED_MODE,
GNB_GPP_PORTx_LINK_ASPM and GNB_GPP_PORTx_CHANNEL_TYPE are not used.

Change-Id: I5c7b7d45880367dba452ebcd4f01fbd0c15aac22
Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/3087
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2013-05-10 09:57:03 +02:00
Paul Menzel bed88d65b2 northbridge/intel/i5000/udelay.c: Remove unused header `console.h`
Nothing from the header `console.h` is needed in `udelay.c`, so do
not include it.

This header was included since commit
»Add Intel i5000 Memory Controller Hub« (17670866) [1].

[1] http://review.coreboot.org/491

Change-Id: Ie136a1b862b55c9471f9293ed616ce27a1d01a50
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3218
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-10 00:36:22 +02:00
Stefan Reinauer 3f5f6d8368 Drop prototype guarding for romcc
Commit "romcc: Don't fail on function prototypes" (11a7db3b) [1]
made romcc not choke on function prototypes anymore. This
allows us to get rid of a lot of ifdefs guarding __ROMCC__ .

[1] http://review.coreboot.org/2424

Change-Id: Ib1be3b294e5b49f5101f2e02ee1473809109c8ac
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/3216
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-10 00:06:46 +02:00
Paul Menzel d654f42e27 AMD: Reduce stack size from 64 KB to the default of 4 KB
Apply the following commit to all AMD boards.

    commit 935850e082
    Author: Stefan Reinauer <reinauer@chromium.org>
    Date:   Mon May 6 16:16:03 2013 -0700

        asrock/e350m1: reduce default stack size

        The stack used on the ASRock E350M1 is significantly less than
        what we currently set (64k per core). In fact, we use about half
        of the default stack size (4k) on core 0 and even less on non
        BSP cores [1]:

        $ grep stack coreboot_without_patch_but_monotonic_timer.log
        CPU1: stack_base 002a0000, stack_end 002afff8
        CPU1: stack: 002a0000 - 002b0000, lowest used address 002afda8, stack used: 600 bytes
        CPU0: stack: 002b0000 - 002c0000, lowest used address 002bf75c, stack used: 2212 bytes

        […]

        Reviewed-on: http://review.coreboot.org/3209

Please note that AGESA seems to define bigger stack sizes. But
these seem to be too much too.

    $ git grep STACK_SIZE src/vendorcode/amd
    […]
    src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14CacheDefaults.c:#define BSP_STACK_SIZE            16384
    src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14CacheDefaults.c:#define CORE0_STACK_SIZE          16384
    src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14CacheDefaults.c:#define CORE1_STACK_SIZE          4096
    src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14CacheDefaults.c:  BSP_STACK_SIZE,
    src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14CacheDefaults.c:  CORE0_STACK_SIZE,
    src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14CacheDefaults.c:  CORE1_STACK_SIZE,
    […]

The following command was used to create the patch.

    $ git grep -l STACK_SIZE src/mainboard/ | xargs sed -i '/STACK_SIZE/,+3d'

Change-Id: I36b95b7a6f190b64d0639fc036ce2fb0253f3fa1
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3217
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-05-09 20:19:24 +02:00