For AMD Inagua, the following two commits
commit 01f7ab9335
Author: Kerry Sheh <shekairui@gmail.com>
Date: Thu Jan 19 13:18:36 2012 +0800
Inagua: Synchronize AMD/inagua mainboard.
Reviewed-on: http://review.coreboot.org/542
and
commit d91c9b7e3c
Author: efdesign98 <efdesign98@gmail.com>
Date: Thu Sep 15 10:59:55 2011 -0600
AMD Inagua platform updates
Reviewed-on: http://review.coreboot.org/136
replaced the constant `iobase` is set to by the define `SMBUS0_BASE_ADDRESS` from `OEM.h`.
Do the same for AMD Persimmon, South Station, Union station and ASRock E350M1.
Change-Id: If095cd9d9b28b118b4072c7c9d345bf620b774c9
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2453
Tested-by: build bot (Jenkins)
Currently the size of the volatile storage for S3 reserved in the
image is hardcoded to 32768 bytes. Make that configurable by
introducing the Kconfig 'S3_DATA_SIZE'.
As the storage space is needed for storing non-volatile, volatile and
MTRR data, add a check if the size is big enough.
Change-Id: I9152797cf0045c8da48109a9d760e417717686db
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/2383
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
If CONFIG_CONSOLE_SERIAL is set, and we can call the standard function
and get a non-zero uart address, then we create an lb table entry.
The code was mostly right, just needed a tweak.
Change-Id: I5b36c7b4e580a23319b7ba92cc8ad61592b1757a
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/2466
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
For whatever reason tabs got inserted in the license header text.
Remove one occurrence of that with the following command [1].
$ git grep -l 'MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.'$'\t' | xargs sed -i 's,MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.[ ]*,MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.\ \ ,'
[1] http://sed.sourceforge.net/grabbag/tutorials/sedfaq.txt
Change-Id: Iaf4ed32c32600c3b23c08f8754815b959b304882
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2460
Tested-by: build bot (Jenkins)
Reviewed-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Reviewed-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
The following commit was too eager replacing spaces with tabs.
commit 36abff1dc8
Author: Marc Jones <marcj303@gmail.com>
Date: Mon Nov 7 23:26:14 2011 -0700
Cleanup Persimmon mainboard whitespace.
Reviewed-on: http://review.coreboot.org/427
Fix that with the following command.
$ git grep -l 'Floor, Boston, MA'$'\t''02110-1301 USA' | xargs sed -i 's/Boston, MA[ ]*02110-1301 USA/Boston, MA 02110-1301 USA/'
Change-Id: Ia118a8c19d94ce1f1048280a0f1d49d447cfa2a7
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2461
Tested-by: build bot (Jenkins)
Reviewed-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Reviewed-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
The SDRAM base is fixed in hardware. It makes no sense to make it configurable.
The TEXT start is a magic number that should also be fixed, not settable.
Change-Id: Ie44cc5c8da1dc38fc00eb602c4a295b045ca5364
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/2465
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Payloads, by design, can return. There's lots of mechanism in the payload code
to support it, and the chooser payload relies on it. Hence, we should not mark
the function call in exit_stage as noreturn.
Not all ARM have unified caches, and it's not always easy to tell what
to do. So we are very paranoid. Before we call between stages, we
should carefully flush the dcache to memory and invalidate the icache.
This may be more than is necessary on all architectures but it
doesn't really hurt for the most part.
So compile cache management code into all stages, and call the
flush dcache/invalidate icache from all stages.
Change-Id: Ib9cc625c4dfd2d7d4b3c69a74686cc655a9d6484
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/2462
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Not only were these files checked in with the Chromium OS Authors
copyright, but in addition they were wrongly licensed as GPL.
Switch to 3-clause BSD (and, since we're changing it, fix copyright,
too)
Change-Id: I3656c1f4304d53e343d89bb7c909fd4b929249f4
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2456
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Fix warning:
mptable.c:52, GNU Compiler 4 (gcc), Priority: Normal
passing argument 3 of 'mptable_write_buses' from incompatible pointer type [enabled by default]
mptable_write_buses is expecting a pointer to an int, so I changed the
U8 isa_bus to an int to match. A U8 doesn't make sense if the value could
be greater than 255 - certainly unlikely, but possible since the value
of isa_bus gets set to the maximum PCI bus number + 1.
Change-Id: I7ea416f48285922d6cf341382109993fd3f6405c
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/2450
Tested-by: build bot (Jenkins)
Reviewed-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
Fix Warning:
sb700_cfg.c:129, GNU Compiler 4 (gcc), Priority: Normal
large integer implicitly truncated to unsigned type [-Woverflow]
The issue here was that an 8 bit value was being placed into a 2-bit
bitfield.
$ more src/vendorcode/amd/cimx/sb700/SBTYPE.h
[…]
UINT32 AzaliaSdin0 :2; //6
UINT32 AzaliaSdin1 :2; //8
UINT32 AzaliaSdin2 :2; //10
UINT32 AzaliaSdin3 :2; //12
$ more src/mainboard/tyan/s8226/sb700_cfg.h
[…]
* SDIN0 is define at BIT0 & BIT1
* 00 - GPIO PIN
* 01 - Reserved
* 10 - As a Azalia SDIN pin
* SDIN1 is define at BIT2 & BIT3
* SDIN2 is define at BIT4 & BIT5
* SDIN3 is define at BIT6 & BIT7
*/
#ifndef AZALIA_SDIN_PIN
#define AZALIA_SDIN_PIN 0x2A
#endif
[…]
$ more src/mainboard/tyan/s8226/sb700_cfg.c
[…]
sb_config->AzaliaSdin0 = AZALIA_SDIN_PIN;
[…]
The 8 bit value 0x2A (binary 00 10 10 10), was being used incorrectly
– I believe the original intent of this value was to enable the SDIN
pins 0, 1, & 2. Because it was getting truncated as it was put into
AzaliaSdin0, this wasn't happening and only SDIN0 was being enabled.
I am leaving only SDIN0 enabled at this point to as not change the
actual behavior on the platform.
Change-Id: Icaeb956926309dbfb5af25a36ccb842877e17a34
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/2452
Tested-by: build bot (Jenkins)
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Fix 84 warnings all like this one:
agesawrapper.c:289, GNU Compiler 4 (gcc), Priority: Normal
format '%lu' expects argument of type 'long unsigned int', but argument 3 has type 'UINT32' [-Wformat]
Fixed by getting rid of the l length specifier and casting to unsigned int.
Change-Id: Ic143c1034f760fa5efb2220aa33861e399ddd708
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/2451
Tested-by: build bot (Jenkins)
Reviewed-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Looking at AssertSlotReset, the comments and all other case's it's
obvious this is a simple copy & paste error where someone just forgot
to change one occurrance of the GPIO nr. Also the AMD Inagua
schematics show that GPIO02 is what they really meant.
Also forward the fix to boards copied from Inagua (AMD South
Station, Union Station, Asrock E350M1).
Change-Id: I6b9a3d473245fa27604b2f148a730290277a88ed
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Reviewed-on: http://review.coreboot.org/2445
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
get_cbfs_header expects CBFS_HEADER_INVALID_ADDRESS (0xffffffff)
instead of NULL when something is wrong.
Also, fix typo.
Change-Id: Ibe56c9eab3b9fdfc6d0b14bc848ca75f3a4fc2f1
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/2455
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
This moves uartmem_getbaseaddr() from an 8250-specific header to the
generic uart header. This is to accomodate non-8250 memory-mapped
UARTs.
Change-Id: Id25e7dab12b33bdd928f2aa4611d720aa79f3dee
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2422
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This adds necessary device operations to add CPU and RAM resources.
Change-Id: Ief8f66627ef37f4fa786bfc3f7899529d3e5b037
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2419
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This patch will cause the resource allocator to actually set aside
the memory resources using methods in the previous patch. The coreboot
table output will include "RAM" entries (there were none before):
coreboot memory table:
0. 0000000040400000-00000000bff001ff: RAM
1. 00000000bff00200-00000000bff00fff: CONFIGURATION TABLES
2. 00000000bff01000-00000000bfffffff: RAM
Change-Id: I5cd76e93fc232fdae1754253efb4e9269b3a20c0
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2420
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Instead, ignore them. One is as non-standard as the other
and ignoring is more convenient since we don't need to
guard prototypes with #ifndef __ROMCC_ all the time.
Change-Id: I7be93a2ed0966ba1a86f0294132a204e6c8bf24f
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/2424
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
REQUIRES_BLOB assumes that all blob files come from the 3rdparty directory,
builds failed when all files were configured to point to other sources.
This change modifies the blob mechanism so that cbfs-files can be tagged as
"required" with some specification what is missing.
If the configured files can't be found (wrong path, missing file), the build
system returns a list of descriptions, then aborts.
Change-Id: Icc128e3afcee8acf49bff9409b93af7769db3517
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/2418
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marcj303@gmail.com>
S3_DATA_POS defines address where the whole S3 data is stored.
Change-Id: I4155a0821e74a3653caaead890e5fec5677637aa
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/2438
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
This adds a simple loop which initializes the stack to 0xdeadbeef
which is used by checkstack().
Change-Id: I8aecf7bfb1067de68c4080c1fcb7eefa28fd04a7
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2421
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Inagua can use GPIOs 178,179 to switch VMEM to 1.5, 1.35 or 1.25 V,
which it does according to data read from the SO-DIMM's SPD EEPROM.
On Persimmon (according to DB-FT1 rev. D schematics) both GPIOs are
unconnected, there is no way to change the 1.5 V DDR3 voltage (save
unsoldering a resistor). The whole code copied over from Inagua is
useless.
Removed the code, instead a comment hints at Inagua, for people who do designs
based on Persimmon but do have a way to change VMEM.
The line ...->DDR3Voltage = VOLT1_5; is supposed to make the AGESA DDR3 code
select the RAM timings for the actually supplied voltage instead of the
hoped-for but unavailable lower voltage. I have no idea how to test this, but
in any case it can't hurt.
Change-Id: Id098e09418b665645814a6ee2d41a3bff72238ba
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Reviewed-on: http://review.coreboot.org/2448
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
According to DB-FT1 rev. D schematics the APU PCIe lane 3 is unconnected.
Reflect this fact in the mainboard code.
Change-Id: Ic98f4a63ef971628df7fbf97f56b80ebe7cb8517
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Reviewed-on: http://review.coreboot.org/2447
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
Comparing Persimmon and Inagua schematics and Coreboot code show the PCIe reset
code has been blindly copied even though it doesn't suit the Persimmon at all.
The Inagua can employ GPIOs 21, 25, 02 to manually reset devices on APU PCIe
lanes 0/1, 2, 3 respectively. (Appearently the motivation for this is to revive
buggy PCIe gen1 devices which got confused by PCIe gen2 signal training.)
However the Persimmon not only doesn't support this, it even needs these 3 pins
for the PCI interface! Instead it uses GPIO50 to reset devices on lanes 0-2 all
at once. Lane 3 is unconnected anyway.
This patch adapts the Persimmon mainboard code according to the DB-FT1 rev. D
schematics.
Change-Id: I05a657d9bf8cc59acc4f5174eb20375165c860c7
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Reviewed-on: http://review.coreboot.org/2446
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
At least not in menuconfig. Move it after the endchoice.
Change-Id: I87d2f70e7c1fbe539cd78cb602a39335b2886d8d
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Reviewed-on: http://review.coreboot.org/2443
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
The "offset" in cbfs-mkpayload should be printed as type %lu
instead of %d as `gcc` rightfully warns about.
gcc -g -Wall -D_7ZIP_ST -c -o /srv/filme/src/coreboot/util/cbfstool/cbfs-mkpayload.o cbfs-mkpayload.c
cbfs-mkpayload.c: In function ‘parse_fv_to_payload’:
cbfs-mkpayload.c:284:3: warning: format ‘%d’ expects argument of type ‘int’, but argument 3 has type ‘long unsigned int’ [-Wformat]
cbfs-mkpayload.c:296:3: warning: format ‘%d’ expects argument of type ‘int’, but argument 3 has type ‘long unsigned int’ [-Wformat]
This warning was introduced in the following commit.
commit 4610247ef1
Author: Patrick Georgi <patrick@georgi-clan.de>
Date: Sat Feb 9 13:26:19 2013 +0100
cbfstool: Handle alignment in UEFI payloads
Reviewed-on: http://review.coreboot.org/2334
Change-Id: I50c26a314723d45fcc6ff9ae2f08266cb7969a12
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2440
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
According to spi.c in src/southbridge/amd/agesa/hudson
readwrite = (bytesin + readoffby1) << 4 | bytesout;
We can see that Hudson limits the SPI programming data
packet size as 15.
We used to write data to SPI in dword mode. It didn't
take full advantage of the data packet size. We need to
leverage that to speed up programming time.
Change-Id: I615e3c8e754e58702247bc26cfffbedaf5827ea8
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/2306
Tested-by: build bot (Jenkins)
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Add needed prototypes to .h files.
Remove unused variables and fix types in printk statements.
Add #IFNDEFs around #DEFINEs to keep them from being defined twice.
Fix a whole bunch of casts.
Fix undefined pre-increment behaviour in a couple of macros. These now
match the macros in the F14 tree.
Change a value of 0xFF that was getting truncated when being assigned
to a 4-bit bitfield to a value of 0x0f.
This was tested with the torpedo build.
This fixes roughly 132 of the 561 warnings in the coreboot build
so I'm not going to list them all.
Here is a sample of the warnings fixed:
In file included from src/cpu/amd/agesa/family12/model_12_init.c:35:0:
src/include/cpu/amd/amdfam12.h:52:5: warning: redundant redeclaration of 'get_initial_apicid' [-Wredundant-decls]
In file included from src/cpu/amd/agesa/family12/model_12_init.c:34:0:
src/include/cpu/amd/multicore.h:48:5: note: previous declaration of 'get_initial_apicid' was here
src/northbridge/amd/agesa/family12/northbridge.c:50:10: warning: no previous prototype for 'get_node_pci' [-Wmissing-prototypes]
src/northbridge/amd/agesa/family12/northbridge.c: In function 'get_hw_mem_hole_info':
src/northbridge/amd/agesa/family12/northbridge.c:302:13: warning: unused variable 'i' [-Wunused-variable]
src/northbridge/amd/agesa/family12/northbridge.c: In function 'domain_set_resources':
src/northbridge/amd/agesa/family12/northbridge.c:587:5: warning: format '%lx' expects argument of type 'long unsigned int', but argument 3 has type 'device_t' [-Wformat]
src/northbridge/amd/agesa/family12/northbridge.c:587:5: warning: format '%lx' expects argument of type 'long unsigned int', but argument 3 has type 'device_t' [-Wformat]
src/northbridge/amd/agesa/family12/northbridge.c:716:1: warning: format '%x' expects argument of type 'unsigned int', but argument 3 has type 'long unsigned int' [-Wformat]
In file included from src/mainboard/amd/torpedo/agesawrapper.h:31:0,
from src/northbridge/amd/agesa/family12/northbridge.c:38:
src/vendorcode/amd/agesa/f12/AGESA.h:1282:0: warning: "TOP_MEM" redefined [enabled by default]
In file included from src/northbridge/amd/agesa/family12/northbridge.c:34:0:
src/include/cpu/amd/mtrr.h:31:0: note: this is the location of the previous definition
In file included from src/mainboard/amd/torpedo/agesawrapper.h:31:0,
from src/northbridge/amd/agesa/family12/northbridge.c:38:
src/vendorcode/amd/agesa/f12/AGESA.h:1283:0: warning: "TOP_MEM2" redefined [enabled by default]
src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c: In function 'PcieInputParserGetNumberOfComplexes':
src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c:99:19: warning: operation on 'ComplexList' may be undefined [-Wsequence-point]
src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c: In function 'PcieInputParserGetLengthOfPcieEnginesList':
src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c:126:20: warning: operation on 'PciePortList' may be undefined [-Wsequence-point]
src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c: In function 'PcieInputParserGetLengthOfDdiEnginesList':
src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c:153:19: warning: operation on 'DdiLinkList' may be undefined [-Wsequence-point]
src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c: In function 'PcieInputParserGetComplexDescriptorOfSocket':
src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c:225:17: warning: operation on 'ComplexList' may be undefined [-Wsequence-point]
src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PciePhyServices.c:246:1: warning: no previous prototype for 'PcieFmForceDccRecalibrationCallback' [-Wmissing-prototypes]
In file included from src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieComplexConfig.c:58:0:
src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/LlanoComplexData.h:120:5: warning: large integer implicitly truncated to unsigned type [-Woverflow]
And fixed a boatload of these types of warning:
src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c: In function 'HeapGetBaseAddress':
src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c:687:17: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c:694:19: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c:701:23: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c:702:23: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c:705:23: warning: assignment makes integer from pointer without a cast [enabled by default]
src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c:709:21: warning: assignment makes integer from pointer without a cast [enabled by default]
Change-Id: I97fa0b8edb453eb582e4402c66482ae9f0a8f764
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/2348
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
Create a new serial console variable, X86_SERIAL_CONSOLE
which is only enabled when SERIAL_CONSOLE and ARCH_X86 are defined.
Builds for x86 and ARM.
Change-Id: I607253c418de015975a839e3c33577842885ec0c
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/2412
Tested-by: build bot (Jenkins)
Reviewed-by: Gabe Black <gabeblack@chromium.org>
This cleans out some obsolete Kconfig variables pertaining to IRAM
usage.
Change-Id: Ie53f5f7204eadc3a3dddc739d2b4b6237242b198
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2417
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
This patch fixes up the usage of stack pointer and regions.
The current approach only works by coincidence, so this fixes a few
things at once to get it into a working state and allow us to use
checkstack() again:
- Add a STACK_SIZE Kconfig variable. Earlier on it was evaluated to 0.
- Assign _stack and _estack using CPU-specific Kconfig variables since
it may reside elsewhere in memory (not necessarily DRAM).
- Make the existing IRAM stack variables more useful in this context.
Change-Id: I4ca5b5680c9ea7e26b1b2b6b3890e028188b51c2
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2416
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
Just a mechanical cleanup.
Change-Id: I0815625e629ab0b7ae6c948144085f1bd8cabfb5
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2408
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
The compiler gets mad when the types are equivalent size but not necessarily
interchangeable because of strict aliasing checks. Since uint32_t is likely to
be used when trying to read 32 bit data, it makes sense for them to be the
compatible.
Signed-off-by: Gabe Black <gabeblack@google.com>
Change-Id: If73d794866055dc026fc06d6268e692adac0f835
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/2411
Tested-by: build bot (Jenkins)
Reviewed-by: Gabe Black <gabeblack@chromium.org>
lpgcc was unconditionally setting -m32.
Most of the flags it sets in the common case are right, however: no need
to duplicate them everywhere, and we only want to change the common ones
in one place, so it would be a shame to duplicate _CFLAGS all over the place.
So add another variable, _ARCHEXTRA, which can be used to add
special flags to _CFLAGS. We onlu use it at present for the x86; this may
change.
This allows us to get through compiling on arm and x86.
Change-Id: I12f1620982c4ee10f76b3953e4225f13db31531e
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/2399
Tested-by: build bot (Jenkins)
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Get rid of the nest of includes, and make separate sections
for each architecture. Also gets rid of the "there's X86 and there's
everything else" structure of this file.
Change-Id: I4232f50f048fa05e911e5de3aa9ec1530931b461
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/2397
Tested-by: build bot (Jenkins)
Reviewed-by: Gabe Black <gabeblack@chromium.org>
The default_ functions in memory.c are only used to initialize a weak
variable. They should not be used outside memory.c. Make them
invisible.
Remove the declaration from libpayload.h. For real this time.
Change-Id: Id54c1fd172c78748f01a958ce4065dd0eb53bbc3
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/2394
Tested-by: build bot (Jenkins)
Reviewed-by: Gabe Black <gabeblack@chromium.org>
These live at the bottom of memory on x86, but that's IO mapped on the exynos.
The particular range used will likely need to be configurable, but this will
make it work in one more case than it used to.
Change-Id: I4d4963b9732cf538d00f8effb4398f30cbbde6aa
Signed-off-by: Gabe Black <gabeblack@google.com>
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/2410
Tested-by: build bot (Jenkins)
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
We don't need three different implementations.
Change-Id: Ie7b5fa90794676ea38838454a33e8e9188428eb7
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2406
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
s5p-common mostly contained duplicate files, drop the whole directory
and merge the few pieces that we are using into exynos5-common.
Change-Id: I5f18e8a6d2379d719ab6bbbf817fe15bda70d17f
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2405
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
They're unused. Also drop some unused defines in system.h
Change-Id: Ia5afc3a676a4a94787041430f05d08f333033c73
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2404
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: build bot (Jenkins)
We don't have asm/
Change-Id: I7f80f47e9d7f457b7a5a64603c59b14d3b536a8c
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2403
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
I think this needs to be its own ldscript. I'm pretty sure this one
is going to need some work however. Is libpayload PIC? That would be
best if so.
Change-Id: I44578d70dfa72de527af8901a86583c2a60130ec
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/2398
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: build bot (Jenkins)
Jens Rottmann