Commit Graph

6613 Commits

Author SHA1 Message Date
Nico Huber 0d120f8ee2 libpayload: Add interrupt-queue underrun recovery to EHCI
If the queue of an interrupt transfer runs out, we have to reset
the queue head. This also introduces the use of a spare transfer
descriptor (TD) in interrupt queues, which assures, that a processed
TD  won't be reused until the host controller has written it back
from his overlay.

Change-Id: Id0eeb2808b77f1c187f164eb34bd66f8f399938b
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1123
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2012-06-21 11:53:17 +02:00
Nico Huber cef86927e8 libpayload: Adjust timeout in EHCI driver
Tested with a bunch of usb flash sticks. The slowest non-TUR (test
unit ready) turn around took about 1.3s, so this commit increases the
timeout to 2s.

Change-Id: Iec64b5cc48d51912b2bdeeebb5885399a71311b2
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1120
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-06-21 11:52:33 +02:00
Sven Schnelle dab6bfe97d i3100: Enable second IOAPIC for PCI-X
i3100/i5000 have a second IOAPIC which handles IRQs for PCI-X.
Add code to enable it.

Change-Id: Ib447628f501b152c8adc9c7c89bd09b5615b9e5a
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1118
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-06-21 08:47:42 +02:00
Anton Kochkov 2e33a65a8c libpayload: reg_base reading for USB EHCI driver
Added reading registers base address for USB EHCI driver
in ehci_init() function.

Change-Id: I59443ca9823588d70822b4f14486caf217a5ac26
Signed-off-by: Anton Kochkov <anton.kochkov@gmail.com>
Reviewed-on: http://review.coreboot.org/1106
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-06-21 08:42:06 +02:00
Nico Huber 904a0ec9d0 Don't use 64-bit constant 0x100000000 in linker scripts
The constant value 0x100000000 is used in linker scripts to calculate
offsets from the end of 32-bit-addressed memory. There is nothing
wrong with it, but 32-bit versions of ld do the calculation wrong.

Change-Id: I4e27c6fd0c864b4d98f686588bf78c7aa48bcba8
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1129
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2012-06-21 08:05:31 +02:00
Sven Schnelle 1454685327 i5000: fix another typo
As Mathias Krause pointed out, using movw/outw on %al is clearly invalid.
Let's do another typo fix...

Change-Id: Ib95832a11097f599a236ab30c64c26ef429a1699
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1119
Tested-by: build bot (Jenkins)
Reviewed-by: Mathias Krause <minipli@googlemail.com>
2012-06-20 20:24:29 +02:00
Nico Huber 43b9f32d20 libpayload: Better error detection in USB mass storage
This implements status transport (CSW) more closely to the standard
(usbmassbulk_10).

Change-Id: Ife516316e054d4e87ebe698dc487eeb9ebcfd38d
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1072
Reviewed-by: Peter Stuge <peter@stuge.se>
Tested-by: build bot (Jenkins)
2012-06-20 19:47:07 +02:00
Anton Kochkov 421303a25a libpayload: Fix detach_contoller in the USB driver
Fixed usb controllers linked list walking in
detach_controller() function

Change-Id: Ia97c7ec814f75d2b1bfe185f160fb4cd32aa6fdb
Signed-off-by: Anton Kochkov <anton.kochkov@gmail.com>
Reviewed-on: http://review.coreboot.org/1105
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.huber@secunet.com>
2012-06-20 17:45:10 +02:00
Sven Schnelle 39b47d2b03 i5000: fix typos
Peter and Ron pointed out two typos. They have no side effects, but
it's still worth to fix them.

Change-Id: I9aecccdbc72beb2623fbe558a06e4f1b050f6e74
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1117
Tested-by: build bot (Jenkins)
2012-06-20 16:37:18 +02:00
Sven Schnelle 69eab16ce6 mptable: realign comments with code
Change-Id: I4bc90334c7220512607cd5e777ce1f8cc595e2f0
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1115
Tested-by: build bot (Jenkins)
2012-06-20 12:46:55 +02:00
Sven Schnelle 2f8c4f829e mptable: initialize apic/bus arrays with ARRAY_SIZE
and increase the busses size to 32, as 16 isn't enough one some
systems (i5000 for example)

Change-Id: Ie09f451dd82ac25b0de85fd47807136e01da737b
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1114
Tested-by: build bot (Jenkins)
2012-06-20 12:46:39 +02:00
Sven Schnelle 2fcc166fb8 mptable: pretty print PCI INT entries
make it more readable by adding INT defines and a left shift.

Change-Id: I7db4d8c71ab4d705833019aa4cc2f11cef7d4fee
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1113
Tested-by: build bot (Jenkins)
2012-06-20 12:46:28 +02:00
Sven Schnelle 4fbcaecf9a mptable: Fix BUS type determination
Change-Id: I7268b35671f6629601fa3b2a589054b8c5da5d78
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1112
Tested-by: build bot (Jenkins)
2012-06-20 11:07:51 +02:00
Sven Schnelle b00c9a2257 mptable: reindent code to comply with coreboot coding style
Change-Id: Iee27c535f56ebedaceea542c2919cde68006827c
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1111
Tested-by: build bot (Jenkins)
2012-06-20 10:36:33 +02:00
Sven Schnelle 09a180230a mptable: Fix 'mptable.c:1019:12: warning: ‘c’ may be used uninitialized in this function'
Change-Id: Icf6968f5bcbbe28c3a2a1d6ee7c1fd0be583f182
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1110
Tested-by: build bot (Jenkins)
2012-06-20 10:20:48 +02:00
Sven Schnelle 57f524fd62 mptable: remove unused variable
Change-Id: I1ff7e040b5aafcdb05a3669158ae94551981e747
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1109
Tested-by: build bot (Jenkins)
2012-06-20 09:44:18 +02:00
Sven Schnelle 9b860165ba mptable: print ioapic entries
Print IOAPIC entry based on actual data, instead of giving the user
the feeling that the generated ioapic entry has any relation to reality.
If the IOAPIC entry in the MPTABLE is incorrect, the user will notice
it anyways. But adding a static entry (which might be also incorrect)
is even worse.

Change-Id: I6d0012324a9e6c7d22436ada36cbd3a4f7166f5c
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1108
Tested-by: build bot (Jenkins)
2012-06-20 09:43:43 +02:00
Sven Schnelle 0b879f838f mptable: rename LAPIC_ADDR to LOCAL_APIC_ADDR
It was renamed in coreboot, so have mptable generate correct code.

Change-Id: I9579209f9f47b756d8ccab63b6f942d22d53d79d
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1107
Tested-by: build bot (Jenkins)
2012-06-20 09:38:01 +02:00
Sven Schnelle edac28ce65 Enable Intel PECI on Model 6fx CPUs
Those CPUs support the PECI (Platform Environment Control
Interface), so enable it. This interface is commonly used
for tasks like fan control.

Change-Id: Id2dadc4821de8cc0b579e77235aa36892e57fd02
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1104
Reviewed-by: Peter Stuge <peter@stuge.se>
Tested-by: build bot (Jenkins)
2012-06-19 18:31:58 +02:00
Sven Schnelle 1a7a7e610e i5000: enforce hard reset
Not doing a hard reset leaves the BOFL0 register cleared, which
prevents the BSP selection from working. To make sure we start
with known values, use the SPAD0 register for soft reset detection.
If there's a value other than 0, do a hard reset.

Change-Id: I390e3208084cfd32d73cce439ddf2bc9d4436a62
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1103
Tested-by: build bot (Jenkins)
2012-06-18 09:03:35 +02:00
Denis 'GNUtoo' Carikli ec6f043c25 llshell: fix build without romcc
Without that fix we have:
      LINK       cbfs/fallback/romstage_null.debug
  build/generated/crt0.romstage.o: In function `ramtest':
  romstage.c:(.rom.text+0x53f): undefined reference to `.Lhlt'
  collect2: ld returned 1 exit status
  make: *** [build/cbfs/"fallback"/romstage_null.debug] Error 1
On the M4A785T-M which doesn't have CONFIG_ROMCC.

Change-Id: I49eded1d18e996afe9441b85dae04ae30c760dd6
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/1101
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2012-06-14 21:21:06 +02:00
Martin Roth 9aa43892e6 Update SB800 CIMX FADT
- Add #define to allow the FADT PM Profile to be overridden.
 - Change the location of the PMA_CNT_BLOCK_ADDRESS to match
   current documentation.
 - cst_cnt should be 0 if smi_cmd == 0
 - add a couple of default access sizes.
 - Add a couple of #define values for unsupported C2 & C3 entries.
 - Add PM Profile override value into amd/persimmon platform.
   This does not use the #defines in acpi.h so that the files that
   include this don't all need to start including acpi.h.

Change-Id: Ib11ef8f9346d42fcf653fae6e2752d62a40a3094
Signed-off-by: Martin L Roth <martin@se-eng.com>
Reviewed-on: http://review.coreboot.org/1055
Tested-by: build bot (Jenkins)
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-06-12 23:35:16 +02:00
Sven Schnelle 0860e723cb udelay: add missing bus frequency
commit 5b6404e419 ("Fix timer frequency
detection on Sandybridge") reworked the udelay code, but didn't add
the 333MHz FSB entry used on Model 15 Xeons.

Change-Id: Ie34f9ae3703b64672625e7bf1b943654a7a5eaa6
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1099
Tested-by: build bot (Jenkins)
2012-06-12 10:01:16 +02:00
Nico Huber bb1c42b920 libpayload: Add timeouts in the UHCI USB driver
We should always have some timeout when we wait for the hardware. This adds
missing timeouts to the UHCI driver.

Change-Id: Ic37b95ce12ff3ff5efe3e7ca346090946f6ee7de
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1073
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-06-09 13:13:08 +02:00
Nico Huber c43e736c0c libpayload: Fix an integer overflow in USB mass storage
Change-Id: I3d618497016478ea727c520e866d27dbc3ebf9af
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1070
Reviewed-by: Mathias Krause <minipli@googlemail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-06-09 13:11:36 +02:00
Nico Huber 0421dc84df libpayload: Add timeouts in the EHCI USB driver
We should always have some timeout when we wait for the hardware. This adds
missing timeouts to the EHCI driver.

Change-Id: I13ba532a6daf47510b16b8fdbe572a21f1d8b09c
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1077
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-06-08 00:01:25 +02:00
Nico Huber afe86c0b74 libpayload: Add timeouts in the OHCI USB driver
We should always have some timeout when we wait for the hardware. This adds
missing timeouts and a more standard compliant port reset to the OHCI driver.

Change-Id: I2cfcb1039fd12f291e88dcb8b74d41cb5bb2315e
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1076
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-06-07 23:49:02 +02:00
Nico Huber 5e3428ea20 libpayload: Remove orphaned delay from OHCI USB driver
This removes a synthetic delay of 5ms from every OHCI USB command.  A delay
here seems to be of no use and first tests have shown no glitches.

Change-Id: Ie72b2d49e6734345708f04f3f7b86bacc7926108
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1075
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-06-07 23:19:30 +02:00
Nico Huber 62eb5b3837 libpayload: Add support for interrupt transfers in EHCI
This adds support for usb interrupt transfers in the EHCI driver. Split
transactions are supported, so this enables support for HID keyboards
devices over hubs in high-speed mode.

Change-Id: I9eb08f12b12c67ece10814952cb8651278b02f9d
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1083
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-06-07 23:16:35 +02:00
Nico Huber 4842dfe6f7 libpayload: Free intr queue structure in usb_hid_destroy
The call to destroy_intr_queue was missing in usb_hid_destroy.

Change-Id: I51ccc6a79bc005819317263be24a56c51acd5f55
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1082
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-06-07 23:15:28 +02:00
Nico Huber 1ab6075320 libpayload: Add support for split transactions in EHCI
With split transactions, the EHCI host controller can handle full- and
low-speed devices on hubs in high-speed mode. This adds support for split
transactions for control and bulk transfers.

Change-Id: I30fa1ce25757f33b1e6ed34207949c9255f05d49
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1081
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-06-07 23:14:18 +02:00
Nico Huber d5d024f3e5 libpayload: Bring USB hub driver to a working state
This adds proper device attachment and detachment detection and port enable-
ment to the USB hub driver. Support for split transactions is still missing,
so this works only with USB2.0 devices on hubs in USB2.0 mode and USB1.1
devices on hubs in USB1.1 mode.

Change-Id: I80bf03f3117116a60382b87a4f84366370649915
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1080
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-06-07 23:12:44 +02:00
Raymond Danks c95da25ac6 Improve parsing of --cpu parameter in abuild script.
* -c "" need never be tested if getopt params are handled; fail abuild script when getopt parsing fails
* use expr to resolve numeric test fails with -c max
* cpus variable may be being passed in the environment.  Don't overwrite MAKEFLAGS if it is not.

Change-Id: I96236ef719a1a9f942b8e15bfcf015d60068e58a
Signed-off-by: Raymond Danks <ray.danks@se-eng.com>
Reviewed-on: http://review.coreboot.org/1068
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-06-04 16:19:45 +02:00
Nico Huber bdca15337b libpayload: Remove orphaned delay from USB mass storage
This removes a synthetic delay of 10ms from every mass storage command.
A delay here seems to be of no use and first tests have only shown a
huge speed increase.

Change-Id: Ida7423229373ec521d4326c5467a3f518b76149c
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1071
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-06-01 12:26:31 +02:00
Nico Huber 7250f0365d Enable CONFIG_GFXUMA for roda/rk886ex
Without GFXUMA beeing set, MTRR initialization runs out of variable MTRRs.

Change-Id: I5d1aa0d5fa2d72f17a0d88cae3fad880b489828c
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1086
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-06-01 12:25:16 +02:00
Nico Huber 14f61424d0 libpayload: Disable some buggy debugging code
This disables some debugging code in the OHCI USB driver which causes
reboots under rare circumstances.

Change-Id: Ic274c162846137ee00638ffbc59ccf1d8130586f
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1074
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-06-01 12:24:17 +02:00
Mathias Krause e28a61550c libpayload: fix OHCI IN commands
Due to operator precedence incomming USB commands were missing some
flags.

Change-Id: I87ef51590c9db7a6cbc7304e1ccac29895f8a51e
Signed-off-by: Mathias Krause <mathias.krause@secunet.com>
Reviewed-on: http://review.coreboot.org/1084
Reviewed-by: Mathias Krause <minipli@googlemail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-06-01 12:23:04 +02:00
Mathias Krause 7b7b5666f0 libpayload: fix UHCI timeout
UHCI commands should have a timeout of 30ms, not 30s!

Change-Id: Iebcf338317164eb1e683e1de850ffab5022ca3a1
Signed-off-by: Mathias Krause <mathias.krause@secunet.com>
Reviewed-on: http://review.coreboot.org/1085
Reviewed-by: Mathias Krause <minipli@googlemail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-06-01 12:22:38 +02:00
Nico Huber 5c4e7aa9e5 libpayload: Correct port power settings for EHCI root hub
Enable power on EHCI root hub ports only if the controller supports it.
Wait 20ms for the power to become stable.

Change-Id: I8897756ed2bfcb88408fe5e9f9e3f8af5dd900ac
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1078
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-06-01 12:22:08 +02:00
Nico Huber 5f595cb6eb libpayload: Add clear_feature() function to USB framework
This function will be used by the USB hub driver.

Change-Id: I4d1d2e94f4442cbb636ae989e8ffd543181c4357
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1079
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-06-01 12:21:14 +02:00
Nico Huber cefec0ea8c libpayload: Fix b0b4a52b70
The removal of bitfields came with some glitches in the UHCI driver. This
fixes it.

Change-Id: Iba8ea3b56b03c526eca7b6388c019568e00be6f5
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1069
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-05-31 18:43:29 +02:00
zbao ee8a9f6c55 Initializer of a static member in union.
It is just me or does anybody have the same build error without
this patch?
------
src/arch/x86/boot/acpigen.c: In function 'acpigen_write_empty_PTC':
src/arch/x86/boot/acpigen.c:347:3: error: unknown field 'resv'
specified in initializer
src/arch/x86/boot/acpigen.c:347:3: warning: missing braces around
 initializer
src/arch/x86/boot/acpigen.c:347:3⚠️ (near initialization
 for 'addr.<anonymous>')
-------

Anyway, I believe at least this will cause warnings.
"resv" is a member of a union, not of acpi_addr_t. So it should be
wrapped by a brace in the initializer.

Change-Id: I72624386816c987d5bb2d3a3a64c7c58eb9af389
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1056
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-05-30 23:01:23 +02:00
Patrick Georgi 2dbfcb750f sconfig: Some fixes
clang complained about a missing include and wrong fprintf use.

Change-Id: Idc023b653e694147c624d5f8f9ed3b797c462e9f
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1067
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-05-30 19:43:01 +02:00
Denis 'GNUtoo' Carikli 7c2d058d61 Fix the location of "Setting variable MTRR" printk.
Without that fix the debugging is harder because the person debugging
  coreboot will see the following twice(note the repeated MTRR number):
    Setting variable MTRR 0, base:    0MB, range: 4096MB, type WB
    [...]
    Setting variable MTRR 1, base: 4096MB, range:  512MB, type WB
    Setting variable MTRR 1, base: 4608MB, range:  256MB, type WB
    Setting variable MTRR 1, base: 3072MB, range: 1024MB, type UC
  instead of the following twice:
    Setting variable MTRR 0, base:    0MB, range: 4096MB, type WB
    [...]
    Setting variable MTRR 1, base: 3072MB, range: 1024MB, type UC

Thanks to kmalkki on #coreboot's Freenode IRC channel for the idea:
  May 25 23:57:17 <kmalkki>	I would add (move) that "Setting variable MTRR..." debug at the end of set_var_mtrrs()

Change-Id: I9f4b7110ba34d017a58d8cc5fb06a7b1c3d0c8aa
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/1058
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2012-05-30 08:32:38 +02:00
Vadim Bendebury 3b3a1a1ee6 Provide functions to access arbitrary GPIO pins and vectors
This change adds utility functions which allow to read any GPIO pin,
as well as a vector of GPIO pin values.

As presented, these functions will be available to Sandy Bridge and
Ivy Bridge systems only.

There is no error checking: trying to read GPIO pin number which
exceeds actual number of pins will return zero, trying to read GPIO
which is not actually configured as such will return unpredictable
value.

When reading a GPIO pin vector, the pin numbers are passed in an
array, terminated by -1. For instance, to read GPIO pins 4, 2, 15 as a
three bit number GPIO4 * 4 + GPIO2 * 2 + GPIO15 * 1, one should pass
pointer to array of {4, 2, 15, -1}.

Change-Id: I042c12dbcb3c46d14ed864a48fc37d54355ced7d
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/1049
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-05-30 00:53:19 +02:00
Stefan Reinauer 691c9f0dab Add support for Panther Point to SPI driver
Change-Id: I98b05d9e639eda880b6e8dc6398413d1f4f5e9c3
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1048
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-05-30 00:53:11 +02:00
Patrick Georgi 68b5da0e68 Use ld manually when compiling with clang
clang does its own linking, incompatible to our
binutils-centric linker magic.

Change-Id: I243597adcb6bc3f7343c3431d7473610c327353d
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/785
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-05-29 22:54:13 +02:00
Stefan Reinauer bb31f3a24a Drop config variable CPU_MODEL_INDEX
It's only used in the ACPI generator for Sandybridge/Ivybridge CPUs
and the code can easily be changed to not rely on any Kconfig magic.

Change-Id: Ie2f92edfe8908f7eb2fda3088f77ad22f491ddcf
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1047
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-05-29 19:55:42 +02:00
Stefan Reinauer 14b23a6ca6 Fix compilation with CONFIG_DEBUG_SPI_FLASH enabled
Right now coreboot compilation fails when SPI flash debugging is
enabled. Fix it by using the right set of memory functions.

Change-Id: I5e372c4a5df53b4d46aaed9e251e5205ff68cb5b
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1044
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-05-29 11:29:54 +02:00
Vadim Bendebury 71695d8a28 Fix full reset for Ivy Bridge platforms
Experiments have shown that writing plain value of 6 at byte io
address of 0xcf9 causes the systems to reset and reboot reliably.

Change-Id: Ie900e4b4014cded868647372b027918b7ff72578
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/1050
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-05-29 11:29:24 +02:00