Commit graph

7 commits

Author SHA1 Message Date
Patrick Georgi
a73b93157f tree: drop last paragraph of GPL copyright header
It encourages users from writing to the FSF without giving an address.
Linux also prefers to drop that and their checkpatch.pl (that we
imported) looks out for that.

This is the result of util/scripts/no-fsf-addresses.sh with no further
editing.

Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/11888
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-31 21:37:39 +01:00
Lee Leahy
94b856ef9a FSP 1.1: Move common FSP code
Move the FSP common code from the src/soc/intel/common directory into
the src/drivers/intel/fsp1_1 directory.  Rename the Kconfig values
associated with this common code.

BRANCH=none
BUG=None
TEST=Build and run on kunimitsu

Change-Id: If1ca613b5010424c797e047c2258760ac3724a5a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e8228cb2a12df1cc06646071fafe10e50bf01440
Original-Change-Id: I4ea84ea4e3e96ae0cfdbbaeb1316caee83359293
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/306350
Original-Commit-Ready: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12156
Tested-by: build bot (Jenkins)
Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
2015-10-27 15:19:03 +01:00
Aaron Durbin
789f2b6c43 fsp1_1: provide binding to UEFI version
FSP has some unique attributes which makes integration
cumbersome:

1. FSP header files do not include the types they need. Like
   EDKII development it's expected types are provided by the
   build system. Therefore, one needs to include the proper
   files to avoid compilation issues.
2. An implementation of FSP for a chipset may use different
   versions of the UEFI PI spec implementation. EDKII is a
   proxy for all of UEFI specifications. In order to provide
   flexibility one needs to binding a set of types and
   structures from an UEFI PI implementation.
3. Each chipset FSP 1.1 implementation has a FspUpdVpd.h
   file which defines it's own types. Commonality between
   FSP chipset implementations are only named typedef
   structs. The fields within are not consistent. And
   because of FSP's insistence on typedefs it makes it
   near impossible to forward declare structs.

The above 3 means one needs to include the correct UEFI
type bindings when working with FSP. The current
implementation had the SoC picking include paths in the
edk2 directory and using a bare <uefi_types.h> include.
Also, with the prior fsp_util.h implementation the SoC's
FSP FspUpdVpd.h header file was required since for providing
all the types at once (Generic FSP 1.1 and SoC types).

The binding has been changed in the following manner:
1. CONFIG_UEFI_2_4_BINDING option added which FSP 1.1
   selects. No other bindings are currently available,
   but this provides the policy.
2. Based on CONFIG_UEFI_2_4_BINDING the proper include
   paths are added to the CPPFLAGS_common.
3. SoC Makefile.inc does not bind UEFI types nor does
   it adjust CPPFLAGS_common in any way.
4. Provide a include/fsp directory under fsp1_1 and
   expose src/drivers/intel/fsp1_1/include in the
   include path. This split can allow a version 2,
   for example, FSP to provide its own include files.
   Yes, that means there needs to be consistency in
   APIs, however that's not this patch.
5. Provide a way for code to differentiate the FSP spec
   types (fsp/api.h) from the chipset FSP types
   (fsp/soc_binding.h). This allows for code re-use that
   doesn't need the chipset types to be defined such as
   the FSP relocation code.

BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built and booted on glados.

Signed-off-by: Aaron Durbin <adubin@chromium.org>

Change-Id: I894165942cfe36936e186af5221efa810be8bb29
Reviewed-on: http://review.coreboot.org/11606
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Tested-by: build bot (Jenkins)
2015-09-10 17:52:28 +00:00
Aaron Durbin
bbbfbf2e0f intel fsp: remove CHIPSET_RESERVED_MEM_BYTES
FSP 1.1 platforms should be conforming to the spec. In order
to ensure following specification remove the crutch that allows
FSP to no conform.

BUG=chrome-os-partner:41961
BRANCH=None
TEST=Built.

Change-Id: I28b876773a3b6f07223d60a5133129d8f2c75bf6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c3fe08c5af41867782e422f27b0aed1b762ff34a
Original-Change-Id: Ib97027a35cdb914aca1eec0eeb225a55f51a4b4b
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/285187
Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/10993
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-07-21 20:09:31 +02:00
Lee Leahy
32471729d9 Braswell: Add Braswell SOC support
Add the files to support the Braswell SOC.

BRANCH=none
BUG=None
TEST=Build for a Braswell platform

Change-Id: I968da68733e57647d0a08e4040ff0378b4d59004
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10051
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-06-25 21:50:48 +02:00
Patrick Georgi
25509ee245 Remove address from GPLv2 headers
Follow up for commit b890a12, some contributions brought
back a number of FSF addresses, so get rid of them again.

Change-Id: I0ac0c957738ce512deb0ed82b2219ef90d96d46b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10322
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-05-28 04:21:52 +02:00
Lee Leahy
77ff0b1a01 Braswell: Use Baytrail as Comparison Base
Add baytrail source for comparison with Braswell.

BRANCH=none
BUG=None
TEST=None

Change-Id: I5170addf41676d95a3daf070a32bcee085f8156d
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10117
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-23 01:40:57 +02:00