Commit Graph

29 Commits

Author SHA1 Message Date
Lee Leahy a4d8180913 Documentation: x86 MTRR setup, TempRamExit and MTRR loading
Document how to test TempRamExit and verify the MTRR setup and loading.

TEST=None

Change-Id: I57a604fa139edac4b05453547d3caf185db491e0
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14113
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-21 20:12:35 +01:00
Lee Leahy b953d05e60 Documentation/Intel: Add more Galileo Gen2 links
Add datasheet links for the components supporting GPIO.  This includes
I2C I/O ports, I2C PWMs, bus buffers and multiplexers.

TEST=None

Change-Id: I0a1d222d6f9bdbd824b78edf2338cd797e83ebba
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14114
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-21 19:47:35 +01:00
Lee Leahy e9a6d1a813 Documentation: x86 shadow ROM disable
Add documentation on disabling the SPI flash which is mapped (shadowed)
into the x86 address space at 0x000e0000 - 0x000fffff.

TEST=None

Change-Id: I1d94d84c6cade97886a3274a7e7403f7b3275c5a
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14112
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-21 19:47:06 +01:00
Lee Leahy fcfa94d6e8 Documentation/Intel: Add EDK-II links
Add a link to the "Driver Writer's Guide" and a link to the "EDK II
firmware for Intel Quark SoC X1000" document.

TEST=None

Change-Id: I8d629d06accfe24a0b8971b5b5868849587c3db7
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13893
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2016-03-07 04:17:34 +01:00
Lee Leahy 7b209ddea7 Documentation/Intel: Making a bootable SD card
Add a link to "Making a bootable SD card"

TEST=None

Change-Id: I5682fdd51a4ba37f97ad35475e11d9843f1498fb
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13892
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-07 04:16:55 +01:00
Lee Leahy 4ee073d476 Documentation/Intel: More CorebootPayloadPkg documentation
Add more documentation on the features that the EDK-II
CorebootPayloadPkg is using.  Add 8254 and 8259 documentation
links.  Add EDK-II documentation links.

TEST=Boot CorebootPayloadPkg to shell prompt

Change-Id: I66df1be0ba908b51b5ddb44a8671b2d7bdb46493
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13851
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-29 04:59:26 +01:00
Lee Leahy ca20b5fa6f Documentation/Intel: Add ACPI link and more FADT documentation
Add a link to the ACPI specification.
Update the FADT table to better describe the use and ACPI specification
reference for the various fields.

TEST=None

Change-Id: I77cd925800d71398be6d677de48874099ea26479
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13765
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-29 04:56:23 +01:00
Lee Leahy bf08da27d5 Documentation/Intel: Add minimal APCI and TempRamExit documentation
Update the documentation to add the minimal ACPI support.  Also add
TempRamExit entry to the FSP features table.

TEST=None

Change-Id: I7a4576d58005a0b6834188dfeca97f1683d03cb0
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13757
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-24 15:55:42 +01:00
Lee Leahy c7a943397d Documentation/Intel: Update EDK2 CorebootPayloadPkg build instructions
Update the build instructions for CorebootPayloadPkg to target the
Galileo Gen2 platform.

TEST=Build and run on the Galileo Gen2 platform.

Change-Id: I9ca8a67811eff988f81f04d4c01c77115356c050
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13756
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-22 07:06:54 +01:00
Lee Leahy de8c7e39bc Documentation: x86 device tree processing and memory map
Add documentation on:
*  FSP Silicon Init
*  How to start the x86 device tree processing for ramstage
*  Disabling the PCI devices
*  Generic PCI device drivers
*  Memory map support

TEST=None

Change-Id: If8f729a0ea1d48db4d5ec1d4ae3ad693e9fe44f0
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13718
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-19 20:24:02 +01:00
Lee Leahy db7410e0a4 Documentation: x86 add EDK2 CorebootPayloadPkg and documentation links
Add EDK2 CorebootPayloadPkg build instructions, EDK2 documentation links
and EDK2 BIOS build instructions.

TEST=None

Change-Id: I236405914c5fa8e33a7826cc4fa60f6dbf0e7724
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13717
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-19 20:23:41 +01:00
Lee Leahy 1c85fea945 Documentation: Add Quark EDK2 build instructions for Linux
Document the Linux build instructions for EDK2.

TEST=Build EDK2 for Quark on Ubuntu 14.04

Change-Id: I5f87eb2c5879f2fd4dd18880908756089a0c7a51
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13644
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-09 19:22:06 +01:00
Lee Leahy fcf776fd02 Documentation: x86 add sleep state and minimal memory setup
Document how to add the sleep state and minimal memory setup.

TEST=None

Change-Id: Ibebeef34269dbf2366f1bea6d734f6bade4e4028
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13446
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-05 22:57:25 +01:00
Lee Leahy 66decf1644 Documentation: x86 Enable Serial Output
Document the steps necessary to enable serial output

TEST=None

Change-Id: Ifc0e700d7ef54fb1e28ca9bca34b94cccd3633ac
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13444
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-05 22:57:03 +01:00
Lee Leahy 7e0078b990 Documentation: Add the x86 FSP Binary
Document how to add the FSP binary to the SPI flash image.

TEST=None

Change-Id: I51b16600ea69853240282ac2eb0d84935b8e2a71
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13442
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-05 22:53:11 +01:00
Lee Leahy a1e4de47c6 Documentation: Add Galileo Gen 1 Documentation
TEST=None

Change-Id: Ic5a732dc27e772c4708a090ecd0c0af17dc5b056
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13606
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-05 22:52:54 +01:00
Lee Leahy e8424cf10f Documentation: Fix links to Intel/documentation.html
Fix links to the documenation.html page which was renamed from
x86Documenation.html.

TEST=Verified documentation links and searched for x86Documenation.html

Change-Id: Icee79bab4c05ac9b8010dc7acdde8dd5e2ab2909
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13592
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-05 22:52:46 +01:00
Lee Leahy 380e167680 Documentation: Add x86 bootblock support
Document what is involved with adding the bootblock support.

TEST=None

Change-Id: I6c8cc38e1b9346b4962588b33ca5e4ab8eac24c3
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13441
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-04 19:30:40 +01:00
Lee Leahy 05c0215ff3 Documenation: x86 Quark/Galileo remove i586 warning
Leverage patch 13552 by adding USE_MARCH_586 to soc/intel/quark/Kconfig.

TEST=None

Change-Id: Ifac947db53e967b98b9494db3f6c3f8ee039ac73
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13561
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
2016-02-02 19:00:13 +01:00
Lee Leahy c1e4f89953 Documentation: Add x86 documentation for required files
Document the required files to perform a minimal coreboot/FSP build for
x86.

TEST=None

Change-Id: I65b2947114634fce982ce82fb7c577fd5f47ed10
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13438
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-02 15:54:43 +01:00
Martin Roth 331c722dd7 Documentation: Add information about patches from other git repos
This is more tribal knowledge that I don't think I've seen written down
anywhere else.  It's not a huge issue, but when looking through the git
log, it helps to be able to differentiate the information from the old
gerrit with the information from the new one.

Change-Id: I7993bda1e9aab79dc26940aaba9ddc52382ed0df
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12804
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-06 17:41:13 +01:00
Martin Roth 6f1e074c3d Documentation: coreboot Gerrit Etiquette and Guidelines
As the community has grown, so has the need to formalize some of the
guidelines that the community lives by.  When the community was small,
it was easy to communicate these things just from one person to another.

Now, with more people joining the community every day, it seems that
it's time to write some of these things down, allowing people to
understand our policies immediately instead of making them learn our
practices as they make mistakes.

As it says in the document:
The following rules are the requirements for behavior in the coreboot
codebase in gerrit.  These have mainly been unwritten rules up to this
point, and should be familiar to most users who have been active in
coreboot for a period of time.  Following these rules will help reduce
friction in the community.

Change-Id: If80e933fcfb04b86fd5efe6423cda448118d7a3c
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/12256
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-11-24 03:52:04 +01:00
Zheng Bao dea0a7f9ae documentation: Update the document about building coreboot
The previous LinuxBIOS-AMD64.tex was still working with subversion.

We need a document to give the preliminary steps to build coreboot
for a new guys.

Change-Id: I64240c8344456e724f0823680e0534cf1db4c4a8
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/4510
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-19 16:05:41 +01:00
Patrick Georgi a73b93157f tree: drop last paragraph of GPL copyright header
It encourages users from writing to the FSF without giving an address.
Linux also prefers to drop that and their checkpatch.pl (that we
imported) looks out for that.

This is the result of util/scripts/no-fsf-addresses.sh with no further
editing.

Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/11888
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-31 21:37:39 +01:00
Furquan Shaikh 567a68e948 documentation: Add documentation for timestamp library
[pg: removed discussion of timestamp internals that isn't current anymore in
favor of some notes for users: when to run which function, what _not_ to do.
Also moved to markdown-ish layout. Will do further style cleanups later.]

BUG=chrome-os-partner:32973
BRANCH=None
TEST=None

Change-Id: I6ea7237f2fa749ce3a493f378f9937e642f3b678
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 97e2a3ebd9552c2a91d9ea62be515059428631cb
Original-Change-Id: I4b184ffad6fcd93d63343a9bca34ad013e9d4263
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/229861
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/10741
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-07 18:00:07 +02:00
Elyes HAOUAS 52648623e0 Remove empty lines at end of file
Used command line to remove empty lines at end of file:
find . -type f -exec sed -i -e :a -e '/^\n*$/{$d;N;};/\n$/ba' {} \;

Change-Id: I816ac9666b6dbb7c7e47843672f0d5cc499766a3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: http://review.coreboot.org/10446
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-08 00:55:07 +02:00
Patrick Georgi b890a1228d Remove address from GPLv2 headers
As per discussion with lawyers[tm], it's not a good idea to
shorten the license header too much - not for legal reasons
but because there are tools that look for them, and giving
them a standard pattern simplifies things.

However, we got confirmation that we don't have to update
every file ever added to coreboot whenever the FSF gets a
new lease, but can drop the address instead.

util/kconfig is excluded because that's imported code that
we may want to synchronize every now and then.

$ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} +
$ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} +
$ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} +
$ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} +
$ find * -type f
	-a \! -name \*.patch \
	-a \! -name \*_shipped \
	-a \! -name LICENSE_GPL \
	-a \! -name LGPL.txt \
	-a \! -name COPYING \
	-a \! -name DISCLAIMER \
	-exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} +

Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/9233
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2015-05-21 20:50:25 +02:00
Vladimir Serbinenko 4679c41db2 Move smi trap sample to documentation, don't keep it in every mobo.
Sample code belongs to documentation, not copied 100x over prodcution code.

Change-Id: I6bb318d76057d02bd6ac5641d12d56ab6d60b745
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10229
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-19 16:22:56 +02:00
Stefan Reinauer 4d8b843d37 Rename documentation -> Documentation
In order to be closer to the Linux kernel source tree
structure, rename documentation to Documentation.

Change-Id: I8690f666638ef352d201bd3c3dc1923b0d24cb12
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10110
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-06 19:09:47 +02:00