These resolved to <device/oprom/include/io.h> which
included <arch/io.h> that we really wanted.
Change-Id: I9aa0bdf34cd1d53e20b4494c7986f0878f4fd840
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31693
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable the support for providing a MAC address for a dock to use based on
the VPD values set in the platform.
BUG=b:123925776
TEST=tested on sarien by setting VPD values and observing the string
returned by the AMAC() method:
> vpd -i RO_VPD -s "ethernet_mac0"="AA:AA:AA:AA:AA:AA"
> vpd -i RO_VPD -s "dock_mac"="BB:BB:BB:BB:BB:BB"
1) Test with no policy set, returns "dock_mac"
ACPI Debug: "VPD region RW did not verify"
ACPI Debug: "Found VPD KEY dock_mac = BB:BB:BB:BB:BB:BB"
ACPI Debug: "MAC address returned from VPD: BB:BB:BB:BB:BB:BB"
ACPI Debug: "AMAC = _AUXMAC_#BBBBBBBBBBBB#"
2) Test with policy set to "builtin", returns nothing
> vpd -i RW_VPD -s "dock_passthru"="builtin"
ACPI Debug: "Found VPD KEY dock_passthru = builtin" [AMAC returns Zero]
3) Test with policy set to "ethernet_mac0"
> vpd -i RW_VPD -s "dock_passthru"="ethernet_mac0"
ACPI Debug: "Found VPD KEY dock_passthru = ethernet_mac0"
ACPI Debug: "Found VPD KEY ethernet_mac0 = AA:AA:AA:AA:AA:AA"
ACPI Debug: "MAC address returned from VPD: AA:AA:AA:AA:AA:AA"
ACPI Debug: "AMAC = _AUXMAC_#AAAAAAAAAAAA#"
4) Test with policy set to "dock_mac"
> vpd -i RW_VPD -s "dock_passthru"="dock_mac"
ACPI Debug: "Found VPD KEY dock_passthru = dock_mac"
ACPI Debug: "Found VPD KEY dock_mac = BB:BB:BB:BB:BB:BB"
ACPI Debug: "MAC address returned from VPD: BB:BB:BB:BB:BB:BB"
ACPI Debug: "AMAC = _AUXMAC_#BBBBBBBBBBBB#"
Change-Id: I90474e264cc433c0fd1a4b0dbaf98e5f74180d54
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
This change adds support for providing a MAC address that can be used
by the OS network drivers to change the MAC address that a NIC uses.
The Realtek r8152 driver in the Linux kernel supports a MAC address
passthru feature which can result in the dock ethernet port using the
same MAC address that is assigned to the internal NIC. This is done
by calling an ACPI method at \_SB.AMAC() which returns a formatted
string containing the MAC address for the dock to use.
The Linux kernel implementation can be found at
drivers/net/usb/r8152.c:vendor_mac_passthru_addr_read()
This is implemented specifically for Chrome OS as it relies on VPD
to determine the MAC address to supply.
The policy which controls where the dock MAC address comes from is
written into RW_VPD property "dock_passthru":
"dock_mac" or empty: Use MAC address from RO_VPD value "dock_mac"
"ethernet_mac0": Use MAC address from RO_VPD value "ethernet_mac0"
"builtin": existing dock MAC address (return nothing)
The MAC address in VPD is the standard format AA:BB:CC:DD:EE:FF and
it must be converted into the string format expected by the OS which
involves some string manipulation which ACPI is not great at handling.
BUG=b:123925776
TEST=this was tested on a sarien board by setting the VPD keys to
their expected values and observing if the AMAC() method returns the
expected string.
Change-Id: I3335e5d924155431e299844e2aaace62168294e0
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31669
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
This ACPI device presents an interface that allows other ACPI devices
or methods to read VPD strings. The VPDF() method is provided the
VPD partition to look in, and the name of the VPD key to find and it
will return the VPD string if it exists.
For example: VPD.VPDF ("RO", "serial_number")
BUG=b:123925776
TEST=this was tested on a sarien platform by adding ACPI code that
searches for a VPD key and returns the value it finds, and then setting
that VPD string from the OS with the Chrome OS 'vpd' utility to ensure
the ACPI method returns the correct value.
Change-Id: I4668f66d7f7f364ac8c3b064d406b24135abb0f6
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31668
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Store the memory address of VPD region start and length for the memory
mapped RO_VPD and RW_VPD into GNVS so they can be used by ACPI code.
BUG=b:123925776
TEST=boot on sarien and verify VPD start/length in GNVS
Change-Id: I39073a9d78f5ff60bfe088860c087a5167f05fdf
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31667
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Move common definitions for PCH H and LP to a common header.
Change-Id: If47692ecb05134db1ee6c0fb10125d6a1b67f127
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/31621
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Create the ISH ACPI device so we can hang fields off of a _DSD table.
Since this is also a PCI device that has run time probing, we can always
emit the ACPI device and let the device tree turn the device on or off.
BRANCH=none
BUG=b:122722008
TEST=verify that _DSD table gets publish under ISH device in kernel ACPI
tables. Also verified that device is still turned off if device tree for
ISH is off.
Change-Id: Ic0231f1ac637fea0e251eb3ac84f0fd8d64c12b2
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31681
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The following remarks show up during cannonlake based platform coreboot
build:
dsdt.asl 55: Offset (0x00),
Remark 2158 - ^ Unnecessary/redundant use of Offset operator
dsdt.asl 136: Offset (0xa8),
Remark 2158 - ^ Unnecessary/redundant use of Offset operator
Address those two remarks in coreboot.
BUG=N/A
TEST=Build coreboot and check build log to see no more remark.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: Iad660347b32d90ac1176654820375e30a21b5ffe
Reviewed-on: https://review.coreboot.org/c/31666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Using ACPICA version 20180927 or greater, IASL detects Unnecessary/redundant
uses of the Offset() operator within a Field Unit list.
It then sends a remark "^ Unnecessary/redundant use of Offset".
Offsets refer to the current offset are unnecessary.
example:
OperationRegion (OPR1, SystemMemory, 0x100, 0x100)
Field (OPR1)
{
Offset (0), // Never needed
FLD1, 32,
Offset (4), // Redundant, offset is already 4 (bytes)
FLD2, 8,
Offset (64), // OK use of Offset.
FLD3, 16,
}
We will have those remarks:
dsdt.asl 14: Offset (0),
Remark 2158 - ^ Unnecessary/redundant use of Offset
operator
dsdt.asl 16: Offset (4),
Remark 2158 - ^ Unnecessary/redundant use of Offset
operator
Change-Id: If53072c6a91dd794c70d1fab8697b1713d400fe8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
IASL version 20180927 and greater, detects Unnecessary/redundant uses of
the Offset() operator within a Field Unit list.
It then sends a remark "^ Unnecessary/redundant use of Offset"
example:
OperationRegion (OPR1, SystemMemory, 0x100, 0x100)
Field (OPR1)
{
Offset (0), // Never needed
FLD1, 32,
Offset (4), // Redundant, offset is already 4 (bytes)
FLD2, 8,
Offset (64), // OK use of Offset.
FLD3, 16,
}
We will have those remarks:
dsdt.asl 14: Offset (0),
Remark 2158 - ^ Unnecessary/redundant use of Offset
operator
dsdt.asl 16: Offset (4),
Remark 2158 - ^ Unnecessary/redundant use of Offset
operator
Change-Id: Ie1f2a2ace335af7984209c9e286b9f85e5342a7e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31671
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When updating firmware, we may need to preserve some sections like VPD,
calibration data, ... etc. The logic can be hard-coded in updater as a
list of known names, but a better solution is to have that directly
declared inside FMAP area flags.
To do that, the first step is to apply the changes in flash map
(http://crosreview.com/1493767). A new FMAP_AREA_PRESERVE is now
defined and will be set in future with new syntax in FMD parser.
BUG=chromium:936768
TEST=make; boots an x86 image.
Change-Id: Idba5c8d4a4c5d272f22be85d2054c6c0ce020b1b
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Local APIC was not configured.
Add setup_lapic() to configure the APIC.
BUG=N/A
TEST= Ubuntu 4.15.0 reports correct local APIC information
on Intel CherryHill CRB
Change-Id: Ic1da5b1bf235f34b957142e86c70a9dbfa3ded1d
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29290
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
HDA support did not configure the codecs correclty.
Use Intel common block support to configure the codecs.
To use common Intel HDA support file hda.c file has been
removed and Braswell HDA device ID is added to list of
supported PCI devices in intel/common/block/hda/hda.c.
CONFIG_SOC_INTEL_COMMON_BLOCK and
CONFIG_SOC_INTEL_COMMON_BLOCK_HDA are enabled
to include hda.c in build.
When codec table is available at board level
SOC_INTEL_COMMON_BLOCK_HDA_VERB must be enabled
and a codec table must be supplied.
BUG=N/A
TEST=Facebook FBG-1701 ALC298 configuration
Change-Id: I5c23ec311e5b5a6dfd6f031aa19617407fe8ed63
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29394
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Since ACPI v2.c, this field is access_size.
Currently, coreboot is using ACPI v3,so we can drop '.resv' field.
Change-Id: I7b3b930861669bb05cdc8e81f6502476a0568fe0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Use a single group for all CONFIG_PCI=y sources.
Change-Id: I426f4398c01dfbf03b9dd2db8c7a964512c86d5e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31680
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
A default is a build-time static value, fallback. Return
value does not depend of input parameter.
Change-Id: I43ae28f465fb46391519ec97a2a50891d458c46d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31679
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Drop the bus parameter, we do not use it.
It would still be possible to do per-bus selection
by evaluating the bus number, but currently we do
not have need for that either.
Change-Id: I09e928b4677d9db2eee12730ba7b3fdd8837805c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31678
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Having different signatures for the PCI config accessors
prevents them from having the same name in different
stages.
For now, work around this using __SIMPLE_DEVICE__.
Change-Id: I20f56cfe3ac7dc4421e62a99ca91f39a857c0ccf
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31677
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This patch makes the way to protect flash regions selectable. If you
don't want to use ifdtool for modification of flash descriptor, enable
the new option. Otherwise, the previous config settings for all
mainboards will be retained.
Change-Id: I46ec6339008edcc78fe76682eed5714f85354937
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/31639
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
As we are running ACPI v3.0, references to older
than v3.0 are removed.
Change-Id: I0cce0035ed2b952d59cc1a4a9e6017dae67ef6db
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31689
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Applying microcode updates a second time seems to be only necessary
on newer platforms (Nehalem+) for "uncore" updates.
Change-Id: Ia2ee9c70677190ffd1a08df1101d39a14fc2c384
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/31665
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Masanori Ogino <masanori.ogino@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
We load it once for the BSP in advance and let the MP init handle it for
the APs. The BSP load could also be done earlier, e.g. before CAR setup,
to align with other platforms.
TEST=Booted ThinkPad X200s and checked log: Microcode is loaded
correctly on the BSP before SMM setup, and reported to be up
to date on all cores after.
Change-Id: I85adb22a608ca3e7355bd486ebba52ec8fdd396c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/31664
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Some ITEs have more than 3 independent FAN controller outputs. As the
initial implementation assumed only 3 outputs some registers are not
consequently numbered. This change adds macros for accessing those
registers.
Additionally some chips have SmartGuardian always enabled, without the
option for turning it off. For these chips bits that were responsible
for ON/OFF control are either reserved or have different meaning.
Another Kconfig option is added to disable ON/OFF functionality on
platforms that do not support it.
Change-Id: Icd60a16b6b5583a3b981bdc220aac472c2a8f40f
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/31616
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
There was CONFIG_ prefix missing in SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG
option, this patch fixes it.
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Change-Id: I52919671569175141560cb73e42344aa1725c112
Reviewed-on: https://review.coreboot.org/c/31674
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In order to prevent keyboard keys pressed at boot from causing issues
in the payload remove the PS2 keyboard driver so it does not get
initialized until it is needed in libpayload.
This was enabled initially because the keyboard controller on this
platform does not come up in translated mode, so unless coreboot
called keyboard_init() the keyboard would never work properly in the
kernel because it would come up as an "AT Raw" device instead of an
"AT Translated" device.
Instead of initializing the keyboard in coreboot a workaround is
added to the payload to put the keyboard into translated mode.
BUG=b:126633269
TEST=boot on sarien while pressing keys and ensure libpayload and/or
the kernel does not have any issues initializing the keyboard.
Change-Id: I765e808f0d2589cf23c0349798a07e2706a2a7a4
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31659
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
We had two ways to configure the serial IRQ mode. One time in the
devicetree for FSP and one time through Kconfig for coreboot. We'll
use `enum serirq_mode` from soc/intel/common/ as a devicetree option
instead. As the default is `quiet mode` here and that is the most
common mode, this saves us a lot of lines.
In four cases kblrvp8, 11 and librem 13v2, 15v3, we had conflicting
settings in devicetree and Kconfig. We'll maintain the `continuous`
selection, although it might be that coreboot overrode this earlier
on the kblrvps.
Note: A lot of Google boards have serial IRQ enabled, while the pin
seems to be unconnected?
Change-Id: I79f0cd302e335d8dcf8bf6bc32f3d40ca6713e5c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/31596
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
INT_MODEL defined in ACPI 1.0 and renamed to reserved since V 2.0.
The value for this field is zero but 1 is allowed to maintain
compatibility with ACPI 1.0.
So set this value to zero as we are using greater version than ACPI 1.0.
Change-Id: I910ead4e5618c958a7989f4c309a3a4bb938e31a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29986
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: David Guckian
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds few more required EFI return status into FSP2.0
drivers so that coreboot code can make use of those.
Change-Id: I9f040e7b9232b05dfc34971afa190cc3cbd7192a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/31647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
This mainboard has a TPM located on the LPC bus. Enable the driver for
it so that it is initialized and the ACPI table entry is generated.
Change-Id: I2eae63932658c2a9f752d28d7c08c27f48531360
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/31663
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
On Sarien, change pin config of 0x19 (headset mic) and
0x21(headset headphone) to change jack location so that naming does
not use "Front" in the name."Front Headphone" --> "Headphone" so it
matches naming on Arcada.
BUG=b:126334749
TEST= verify with 'evtest' command that jack name is
"HDA Intel PCH Headphone" not "HDA Intel PCH Front Headphone"
Change-Id: I36ccf0c0a3952ab363fe6ee313fac8f0cce4dd61
Signed-off-by: Joyce Toh <joyce.toh@intel.com>
Reviewed-on: https://review.coreboot.org/c/31624
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The fdt in the maskrom cannot be used to start linux. The correct fdt
is dumped by replacing the bbl of the original firmware and used in
coreboot.
Correct the mac address in fdt by reading otp
Change-Id: Ic29f0e590311360b85fafd12ebc36cd189fbbc38
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/c/31047
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Philipp Hug <philipp@hug.cx>
Calculation of memory reserved by FSP is incorrect.
Use CBMEM_ID_FSP_RESERVED_MEMORY to determine the memory area
BUG=N/A
TEST=Intel CherryHill CRB
Change-Id: If68bda39ba2b1f3be4ed4bc872710be7bbd4948b
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Preliminary dptf change for Atlas
- Throttle charger using all temp sensors (not just ambient)
- Throttle charger with higher priority than CPU
- Update throttle temperature using data from surface thermistor
in thermal chamber test
BUG=b:113101335
BRANCH=None
TEST=based on preliminary data from thermal chamber test
Change-Id: Ic1ab72f569e8a4f7bffc5560518fb703d32f4b21
Signed-off-by: Puthikorn Voravootivat <puthik@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Caveh Jalali <caveh@google.com>
The level/edge mode of PIRQ is not configured and i8259 PIC not initialized.
Add calls to:
- i8259_configure_irq_trigger()
- setup_i8259()
- write_pci_config_irqs()
to correct the configuration of interrupts.
BUG=N/A
TEST=Intel CherryHill CRB
Change-Id: I128cb35dd0e348a9cd9fb162651e0aa2b7e4a3ef
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29419
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
IRQ10 and 11 are not available as _PRS in all LNKx ResourceTemplates.
These interrupt numbers are added to all LNKx.
BUG=N/A
TEST=Intel CherryHill CRB
Change-Id: Ie7a263d7d50f7f85e6195777c1429dcc27a15604
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29287
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Static scan does not know the contents of the fixed MTRR descriptor, so
it has no way to eval the result for variable num_ranges. If num_ranges
is less or equal to 0, the for loop will not be entered, and the values
of fixed_msrs will not be set. Asserting that num_ranges is greater than
0 ensures the loop enters at least once.
BUG=b:112253891
TEST=build grunt
Change-Id: Ieec0ac432c745bde4b1700539c266625da6cfd77
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/c/31527
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
These marketing names are much easier to distinguish. My
mnemonic: Socket M => up to Merom, Socket P => up to Penryn.
Change-Id: I3c2a59596cf7f3cd763bd79962ad326ab080677b
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/31645
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These came for the Socket 479 which is not supported anymore.
Change-Id: I0cf7ece028baa6750b79f54d615e93e452aff2e1
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/31644
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These sneaked in and were never supported by this socket (nor expected
in the notebooks that have it).
Change-Id: Iaeaf1d3bba213da56c7841cf6182e013626b8ca2
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/31643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The name was wrong. mFCPGA478 is actually a pseudonym for mPGA478MN,
the successor of the socket that was meant.
The official name of this socket is mPGA478MT. But "Socket M" is much
easier to distinguish.
Change-Id: I4efeaca69acddfcdc5e957b0b521544314d46eeb
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/31642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Doesn't look like it could be used.
Change-Id: I8074df12d062bd15f2388b367b3698c9d3b7b5b6
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/31641
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
coreboot did not program all GPIOs from C0 to C7 correctly which are
SMBUS GPIO. Some of the GPIOs are left in default mode which is
native function but we need to configure as GPIO mode and provide proper
configuration as per schematic.
After fixing GPIO, CSME power gating issue also gets fixed since SMBUS was not
getting idle due to GPIO configuration and CSME was not getting power
gated due to SMBUS.
BUG=b:123702553
BRANCH=none
TEST=Check on hatch board. CSME was not getting power gated for s0ix.
After applying this patch CSME is power gated now
Change-Id: I5c6b9310dcc7bade0023abd5524781ce71df28be
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/31640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Kyösti Mälkki