These are not used anywhere and are not present on Broadwell.
Change-Id: I2d1359286ac719cb5daefc955d5c6085e2949c1f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46788
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There's no need to perform manual shifting and masking when ACPI allows
one to painlessly describe bitfields of a register. The now-unused DVEN
definition will be dropped in a follow-up, alongside other definitions.
Change-Id: Iab6972c78c1114c8e3dfee28320ae233421ff154
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46787
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Rename it to `hostbridge.asl`, which is what Haswell uses.
Change-Id: I6f97fc5c9459fe6b66dcfcf51900c751beda0ebe
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46786
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These Function Disable definitions have been copied from Cougar Point,
are not used by any mainboard, and may be incorrect. So, remove them.
Change-Id: I36f732bce22ec33aab42beababe54c4d88e0205b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46784
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There's no need to dynamically differentiate between traditional and Low
Power platforms at runtime, and doing so makes code reuse more complex.
Change-Id: Id40f2f5f41db00487af9115eabee8874c2399030
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46785
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Commit 576b7c7 (broadwell: gpio.asl: Make GWAK method serialized) made
GWAK serialized for Broadwell. This commit follows suit on Lynx Point.
The reason to serialize this method is because it creates named objects
which depend on input parameters, and thus cannot be created elsewhere.
Change-Id: I892700df3bba079e3280008f619017e3954d5a06
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46783
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tested with BUILD_TIMELESS=1, Google Wolf does not change.
Change-Id: I0ce8f1e4aaa86d2f7607fec9214dc64d1f530c88
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46782
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
LynxPoint-LP handles GPIOs differently, and LynxPoint-H has the same
GPIO kind as previous-generation PCHs, such as Cougar Point. Remove some
unneeded logic from `_CRS` and declare the GPIOBASE resource statically.
The preprocessor allows later ACPI deduplication to remain reproducible.
Change-Id: If771d5b6c3a1623da7d015ed50199877615409b2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46781
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In order for ACPI deduplication to be reproducible, the `ISLP` method
needs to disappear. Replace the _PRW methods with a name and a macro.
Change-Id: Id0a46965b66f1a70e8f8868af01a535207c9f5c7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46780
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is merely to ease diffing Lynx Point and Broadwell ASL code.
Tested with BUILD_TIMELESS=1, Google Buddy does not change.
Change-Id: I9f6ab98388d2a2915a48377ebe9e724cfee4b95f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46779
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use ASL 2.0 syntax where possible and uniformize code style to match the
IASL disassembly. Some `Store` in gpio.asl change the binary if touched.
Tested with BUILD_TIMELESS=1, Google Buddy does not change.
Change-Id: Ic13c081fd7ee2212d851cc14263c1e2fd8970072
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46778
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use ASL 2.0 syntax where possible and uniformize code style to match the
IASL disassembly. Some `Store` in gpio.asl change the binary if touched.
Also remove outdated comment and remove `LynxPoint` from `serialio.asl`.
Tested with BUILD_TIMELESS=1, Google Panther does not change.
Change-Id: Ie0994fa546ff54ebb533afcc6205efb36da99a67
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46777
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4,
the interrupt line used by the device is required to be level triggered.
Hence, this change updates the configuration of the HID over I2C devices
to be level triggered.
References:
[1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx
BUG=b:172846122
TEST=./util/abuild/abuild
Change-Id: Ifc6dd5f6549e7501f350afe8456a9a8096edcc25
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47425
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4,
the interrupt line used by the device is required to be level triggered.
Hence, this change updates the configuration of the HID over I2C devices
to be level triggered.
References:
[1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx
BUG=b:172846122
TEST=./util/abuild/abuild
Change-Id: Ida1b1d05b39e67a9eba3bfaecca37f38821a438b
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47423
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4,
the interrupt line used by the device is required to be level triggered.
Hence, this change updates the configuration of the HID over I2C devices
to be level triggered.
References:
[1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx
BUG=b:172846122
TEST=./util/abuild/abuild
Change-Id: Ib2f203b5f5eea5c25cfd4543f5ed9f15101b1735
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47422
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4,
the interrupt line used by the device is required to be level triggered.
Hence, this change updates the configuration of the HID over I2C devices
to be level triggered.
References:
[1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx
BUG=b:172846122
TEST=./util/abuild/abuild
Change-Id: Ic334816712370da63471135da8dd598ab02d54ef
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47421
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4,
the interrupt line used by the device is required to be level triggered.
Hence, this change updates the configuration of the HID over I2C devices
to be level triggered.
References:
[1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx
BUG=b:172846122
TEST=./util/abuild/abuild
Change-Id: I75a92616f11054993ff5a5bfefce5c3f4638c07c
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4,
the interrupt line used by the device is required to be level triggered.
Hence, this change updates the configuration of the HID over I2C devices
to be level triggered.
References:
[1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx
BUG=b:172846122
TEST=./util/abuild/abuild
Change-Id: Iff00667377eecedcf0b83bcfc0bf50bd4c3411eb
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47419
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4,
the interrupt line used by the device is required to be level triggered.
Hence, this change updates the configuration of the HID over I2C devices
to be level triggered.
References:
[1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx
BUG=b:172846122
TEST=./util/abuild/abuild
Change-Id: I1773973f64bcc5ef6bd1856c5d8eb998bb6a4888
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47418
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4,
the interrupt line used by the device is required to be level triggered.
Hence, this change updates the configuration of the HID over I2C devices
to be level triggered.
References:
[1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx
BUG=b:172846122
TEST=./util/abuild/abuild
Change-Id: I320198d56131cf54e0f73227479f69968719b2a7
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47417
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4,
the interrupt line used by the device is required to be level triggered.
Hence, this change updates the configuration of the HID over I2C devices
to be level triggered.
References:
[1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx
BUG=b:172846122
TEST=./util/abuild/abuild
Change-Id: Ie7b82ea07ef97b2096d75229c445bd3a65cb3be0
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47416
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4,
the interrupt line used by the device is required to be level triggered.
Hence, this change updates the configuration of the HID over I2C devices
to be level triggered.
References:
[1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx
BUG=b:172846122
TEST=emerge-dedede coreboot
Change-Id: I9d8fa57ae0f554896a4a0722e3e89567676382d4
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47415
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add a helper function to print out debug info and add the MADT entry.
Change-Id: I1a00f87c6edef530c5352929ee9279782be4b112
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47299
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
The existing help text wasn't updated for Mandolin after it was copied
from an older reference board and contained some information that
doesn't apply to Mandolin.
Change-Id: Ib34abb2ee8b289df5f7085957042fe00ad506ca9
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47481
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The defines for RX6110SA_SLAVE_ADR and RX6110SA_I2C_CONTROLLER are not
used anymore and can be deleted.
Change-Id: I3cddf7a9e2f757a22c729ae0f0ff767d55909b9c
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47236
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tested-by: siemens-bot
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
This patch adds basic ACPI support for the RTC so that the OS is able to
use this RTC via the ACPI interface.
If the Linux kernel is able to find the RTC in ACPI scope, you should
see the following lines in dmesg, where [n] is an enumerated number:
rx6110 i2c-RX6110SA:00: rtc core: registered RX6110SA:00 as rtc[n]
rtc rtc[n]: Update timer was detected
Change-Id: I9b319e3088e6511592075b055f8fa3e2aedaa209
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47235
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
It’s common to annotate the closing endif, so do it for these four
files.
Change-Id: Ia5d071e1f544c9dea5af9c6bc3c605d9a0c5c0f5
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
List of changes:
1. Add new PCH ID 0x5181 into device/pci_ids.h
2. Update new PCH ID into common lpc.c
3. Add new PCH ID description into report_platform.c
TEST=Able to build and boot ADLRVP with new PCH ID.
Change-Id: I4343b7343876eb40c2955f6f4dd99d6446852dc0
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47474
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Work on this SoC was abandoned and never finished. It's not really
usable in its current state, so let's get rid of it.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I23453e3e47ac336ab61687004470e5e79172cafe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47428
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Work on this mainboard was abandoned and never finished. It's not really
usable in its current state, so let's get rid of it.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I4cd2e2cd0ee69d9846472653a942fa074e2b924d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Selecting USE_CAR_NEM_ENHANCED_V1 as of now. This selection in Kconfig
programs IA32_L3_MASK_1 (0xc91) & IA32_L3_MASK_2 (0xc92). These will
select ways for eviction & non-eviction. TGL will have to switch back
to USE_CAR_NEM_ENHANCED_V2 once the IA32_L3_SF_MASK_1 (0x1891) &
IA32_L3_SF_MASK_2 (0x1892) programming requirements are understood.
Bug=b:171601324
BRANCH=volteer
Test=Build coreboot for volteer. Boot on SKU that has 4MB L3 cache.
Change-Id: Ifc77856e26ab26f9fbb2693f70c751f43337421b
Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47258
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This change switches the selection of CAR mode so that
INTEL_CAR_NEM_ENHANCED_V2 is the default unless mainboard
selects INTEL_CAR_NEM. INTEL_CAR_NEM is selected only by
mainboards using older silicon (ES1 or ES2) that did not
support NEM enhanced mode.
This enables NEM Enhanced Mode for TGL-U/Y RVPs.
Bug=b:171601324
BRANCH=volteer
Test=Build coreboot for volteer. Boot on SKU that has 4MB L3 cache.
Change-Id: Ib6e041261cb8ca9c6e602935da4962aac0d9ece5
Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47259
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Introduce the `sir_unset_and_set_mask` helper and update the one PCI
read-modify-write operation that is somehow not reproducible.
Change-Id: I30ad6ef8ad97ee0a8dc2297fba5bbbfe24f00f1c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47030
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
The other two modes are not used by any mainboard, and the code seems to
be copied from older southbridges. As the code looks incorrect, drop it.
Change-Id: I374546279a85cead1aea13e0952bbfd6f643a75b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47022
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
The Asus F2A85-M, F2A85-M LE and F2A85-M PRO all have a Super I/O, and
therefore have legacy devices like a serial console.
Selecting `HUDSON_LEGACY_FREE` currently disable the serial console
during bootup in romstage, which is undesired.
So, deselect the symbol by default.
TEST=Boot Asus F2A85-M PRO and verify serial console is *not* disabled
during romstage.
Change-Id: Ia6588c0d4b2c24c7cb9da04805d13274c8ae295e
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47363
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Mike Banon <mikebdp2@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add support to check for the Power Management (PM) Status bit for
various internal devices like USB, CNVi etc. and log them into the event
log for debugging purposes.
BUG=b:172279037
BRANCH=volteer
Change-Id: Ib3d0bf33d780444f8240f749a3319212c985950d
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47227
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add support to check for the Power Management (PM) Status bit for
various internal devices like USB, CNVi etc. and log them into the event
log for debugging purposes.
BUG=b:172279037
TEST=Build and boot to OS in Drawlat. Ensure that the wake up event is
logged into the event log for one of the internal devices eg. USB
bluetooth.
8 | 2020-11-05 15:04:16 | S0ix Enter
9 | 2020-11-05 15:04:29 | S0ix Exit
10 | 2020-11-05 15:04:29 | Wake Source | PME - XHCI (USB 2.0 port) | 8
11 | 2020-11-05 15:04:29 | Wake Source | GPE # | 109
12 | 2020-11-05 15:05:08 | S0ix Enter
13 | 2020-11-05 15:05:14 | S0ix Exit
14 | 2020-11-05 15:05:14 | Wake Source | PME - XHCI (USB 2.0 port) | 8
15 | 2020-11-05 15:05:14 | Wake Source | GPE # | 109
Change-Id: I9f43675b698bf310f6b98b5e775d1259607abbcd
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47226
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It is too easy to confuse those with IA32_SMRR_PHYS_x registers.
Change-Id: Ice02ab6c0315a2be14ef110ede506262e3c0a4d5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46896
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Actual support CBnT will be added later on.
Change-Id: Icc35c5e6c74d002efee43cc05ecc8023e00631e0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46456
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Create the shuboz variant of the zork reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.2.0).
BUG=b:172021093
BRANCH=none
TEST=emerge-zork coreboot
Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: I3f62625f8cbde1c9adf8ab335edeb9e811e32679
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47152
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The code is based on autoport, with necessary modifications.
This laptop uses SMSC MEC1322 embedded controller, but the EC
interface is the same as the EliteBook laptops of previous generations
that use KBC1126 EC. So it still uses ec/hp/kbc1126, but does not need
EC firmware inserted into CBFS. We also need to leave the end of the
OEM flash content untouched, so the default ROM size is set to 12MiB
instead of 16MiB, and we need to modify the IFD when flashing.
Thanks to persmule for providing the laptop and pointing out how to
program the system flash chip of it.
Change-Id: I2328c43cbb1f488aa1d0ddd9116814d971e5d8ae
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45578
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
CB:46865 ("mb, soc/intel: Reorganize CNVi device entries in
devicetree") reorganized the devicetree entries to make the
representation of CNVi device consistent with other internal PCI
devices. Since a dummy generic device is added for the CNVi device,
`emit_sar_acpi_structures()` needs to first check if the device is PCI
before checking the vendor ID. This ensures that SAR table generation
is skipped only for PCIe devices with non-Intel vendor IDs and not for
the dummy generic device.
BUG=b:165105210
Change-Id: I3c8d18538b94ed1072cfcc108552f3a1ac320395
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47364
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Adds ACPI properties for WDT8762A device.
Per spec v0.8
HID name WDHT2002
T14=100ms
BUG=b:163561649
BRANCH=puff
TEST=emerge-puff coreboot and check system dmesg and evtest can get device.
Change-Id: I178e9d5aa1e1501d33b3cd4092f3f522bb6f1a74
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47280
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
