Commit Graph

31306 Commits

Author SHA1 Message Date
Wim Vervoorn a1c259beef security/vboot: Add rw_region_only support to vboot
In some case where the flash space is limited or when a large payload such as LinuxBoot
is used, the RO region may not be large enough to contain all components that would
normally be added.

This patch adds the possibility to add specific components to the RW regions only in
the same way as the RO_ONLY_SUPPORT does for the RO region.

Please note: this applies only to the items that would normally be added to all regions.
If the payload is directed to the RW region only, a recovery payload needs to be added
to the RO region manually.

BUG=N/A
TEST=build

Change-Id: Ie0df9b5dfc6df4f24efc5582a1aec9ecfb48c44d
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36544
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-11 10:38:34 +00:00
Arthur Heymans 02a4a0d471 soc/intel/tigerlake: Fix cbmem_top
EBDA support was dropped.

Change-Id: I83d838b79e2653d4e3764cfc7deaca9bb241deab
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36718
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-11 10:37:42 +00:00
Werner Zeh 9caadfe708 mb/siemens/mc_apl6: Add TPM to devicetree
The TPM chip needs to be added to the devicetree so that the ACPI tables
will be generated for it. These ACPI table entry is used by the OS to get
the location of the TPM chip.

Change-Id: Ic40d1cf236dd849f04f088808d94b6dd81e3238a
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36677
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2019-11-11 10:35:17 +00:00
Werner Zeh a4b7befbd5 mb/siemens/mc_apl6: Enable SDHCI and disable eMMC controller
This mainboard variant uses SD-card and not eMMC. Therefore eMMC
controller is disabled while SDHCI is enabled.

Change-Id: I40b314905730b5d74c674d2251f8a4e5c807805f
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36676
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-11 10:35:06 +00:00
Werner Zeh 4f7fe494a0 mb/siemens/mc_apl6: Adjust clock lines used on PCIe-2-PCI bridge
On this mainboard variant the PCIe-2-PCI bridge is used a bit different.
Adjust the switched off clock lines to match the mainboard
configuration.

Change-Id: I16f3b6eed0948c8201baecdfbb8052c6c1c335c8
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2019-11-11 10:34:55 +00:00
Werner Zeh 7c276c0dd7 mb/siemens/mc_apl6: Enable VBOOT per default
mc_apl6 uses VBOOT scheme so enable it as default.

Change-Id: I341180f3815ff9f3b2db801d9d989119a2585b03
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36669
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2019-11-11 10:34:36 +00:00
Werner Zeh 0dc87ef90d mb/siemens/mc_apl6: Add new mainboard based on mc_apl3
This patch adds a new mainboard variant called mc_apl6 which is based
on mc_apl3. So far only the names have been adjusted with no further
changes. Following commits will introduce the needed changes for this
mainboard variant.

Change-Id: Ic935f6cc1f037947b2c167696d40da8309e4d4f0
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36668
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2019-11-11 10:34:09 +00:00
Michael Niewöhner 6754dcda74 soc/intel/quark: make use of common cbmem_top_chipset
This replaces quark's own implementation of cbmem_top_chipset and
selects the common code one.

Change-Id: I445c471b654abfa922b20215e52a2794529be120
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36621
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-11 10:33:51 +00:00
Michael Niewöhner 97012bd019 soc/intel/apollolake: make use of common cbmem_top_chipset
This replaces apollolake's own implementation of cbmem_top_chipset and
selects the common code one.

Change-Id: I11d12a6c8414a98d38be8b0dbf6dc57cd2efc5d6
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36618
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-11 10:33:11 +00:00
Kyösti Mälkki 45ddb4344f console,boot_state: Exclude printk() from reported times
Use monotonic timer to accumulate the time spent in
console code.

For bootblock and romstage, only stage total is reported.
For ramstage each boot_state is reported individually.

Change-Id: Id3998bab553ff803a93257a3f2c7bfea44c31729
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36574
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-11 10:31:29 +00:00
Kyösti Mälkki 19825e8e37 Documentation: Add some significant 4.11 release notes
Change-Id: I0f9a5afe85068e6ef2a0b0d088557b0dd1e5bd91
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36697
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-11 10:31:14 +00:00
Elyes HAOUAS ca7f93d567 fsp{rangeley,baytrail,broadwell_de}: Fix dead assignment
Change-Id: I0f02a4508b78cdb0706df6f288138a9db54e229e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36703
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-11 10:30:24 +00:00
Elyes HAOUAS aabc215962 src/mb: Remove redundant message befor 'system_reset()'
Change-Id: Id5a6b7c731b65aafbb88a7c52a1f434dbab41f4a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36694
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-11 10:30:13 +00:00
Elyes HAOUAS 10cfd4d7cf mb/{x4x}: Remove unused 'include <northbridge/intel/x4x/iomap.h>'
Change-Id: I82f1d4325ea87585137fa81567aa82b80454c704
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36693
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-11 10:29:24 +00:00
Julius Werner e396c662c0 rockchip/rk3288: Bump verstage size a little more
RK3288 is running out of space again. I believe reducing the CBFS cache
size this much should be safe. I don't really care to test it either
though. We should probably just deprecate that SoC at some point, it's
just causing too much pain.

Change-Id: Id8f971606a7a183d3e9af8bbb1b353e518ec24c8
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36692
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Joel Kitching <kitching@google.com>
2019-11-11 10:29:04 +00:00
Shelley Chen 5c7b74a22b Helios: Set the reset delay for Goodix touchscreen to 120ms
With the 0.71586+ Goodix FW, we can reduce the reset delay from 500ms
to 120ms.  We should do the change in coreboot device tree after we
ensure Helios DVT build is flashed with 0.71586+ Goodix FW.

BUG=b:142316026
BRANCH=None
TEST=./util/abuild/abuild -p none -t google/hatch -x -a

Change-Id: I000ee4ea84c598b437992f1000f6e5b561cae605
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36655
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philip Chen <philipchen@google.com>
2019-11-11 10:28:32 +00:00
Aaron Durbin 56aeae0400 region: publicize region_end() and add region_device_end()
Provide region_device_end() and make region_end() publically available
for use to match a pattern of open coding the offset + size calculation
for both struct region and struct region_device. Apply the use of the
helpers where the usage matches in the code.

Change-Id: Iaef5d007eef9a77f7f33b0e89298abef0197352d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36689
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-11 10:28:09 +00:00
Aaron Durbin b1ea53d846 region: add rdev_chain_full()
Instead of open coding an offset of 0 and querying the size of a
region device provide a rdev_chain_full() helper function that
does that for the caller. For the existing users that match this pattern
convert them to using rdev_chain_full().

Change-Id: Ie316790a8a5b16a7f7e22f86f58bd2e633c19450
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36683
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-11 10:27:47 +00:00
Michael Niewöhner f0564a9c44 include: introduce update* for mmio operations
Introduce update* as equivalent of pci_update* for mmio operations.

Change-Id: I9f188d586c09ee9f1e17290563f68970603204fb
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36596
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-11 10:26:55 +00:00
Michael Niewöhner e919390f47 soc/intel/icelake: add soc implementation for ETR address API
Add soc implementation for the new ETR address API.

Change-Id: I8383a60c2c4988948ab8b3e9a54330269d217868
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36568
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-11 10:26:14 +00:00
Michael Niewöhner 93d215cb05 soc/intel/cannonlake: add soc implementation for ETR address API
Add soc implementation for the new ETR address API.

Change-Id: Ifc128099185a2c40ec3e7c5f84fcc42227c93f28
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36567
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-11 10:26:11 +00:00
Michael Niewöhner b4d960b65a soc/intel/apollolake: add soc implementation for ETR address API
Add soc implementation for the new ETR address API.

Change-Id: I1832f5f14055fc3dbb502289035130ca7a5d6d33
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-11-11 10:26:03 +00:00
Michael Niewöhner 28552095d8 soc/intel/common: pmclib: add API to get ETR register address
Add a new API to get the ETR register address.

Change-Id: I706f3e220d639a6133625e3cb7267f7009006af2
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36565
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-11 10:25:55 +00:00
Michael Niewöhner 8f22136c05 include/device: add pci mmio cfg address helpers
Add helpers for getting the pci mmio cfg address for a register.

Change-Id: Ie6fe22cacc7241a51d47cbe9fc64f30fa49d5a80
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36686
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-11 10:25:40 +00:00
Changqi Hu bc2f9a30f3 libpayload: usbmsc: update return value of CSW transfer
When the first CSW transfer failed, get_csw function will retry
CSW transfer again, but the return value is not updated.

Change-Id: I289916baa08d0a189d659164a0002347f6f435db
Signed-off-by: Changqi Hu <changqi.hu@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36678
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-11-11 10:25:24 +00:00
Patrick Rudolph 1b95501fad Documentation: Add some significant 4.11 release notes
Change-Id: Ia881cfa9382d0b2fa2652696b912030af942b68a
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36625
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-11-11 10:24:50 +00:00
Arthur Heymans 12440ce63e drivers/intel/fsp1_1: Fake microcode update to make FSP happy
The FSP loops through microcode updates and at the end checks if
the microcode revision is not zero. Since we update the microcode
before loading FSP, this is the case and a fake microcode can be
passed to the FSP.

The advantage is that the Kconfig symbols to specify the location and
the size of the microcode blob can be dropped.

Change-Id: I63cfb7b19e9795da85566733fb4c1ff989e85d03
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36255
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-10 22:57:55 +00:00
Arthur Heymans 8256ca0e14 soc/intel/braswell: Update microcode before FSP
The google FSP Braswell version has broken microcode update code and
FSP checks at some point if the installed microcode version is non
zero, so coreboot has to update it before calling FSP-T.

This is fixed with newer FSP releases by Intel, but doing updates in
coreboot won't hurt.

Tested with both Intel FSP and google FSP.

Change-Id: I3e81329854e823dc66fec191adbed617bb37d649
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36198
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-10 22:57:29 +00:00
Arthur Heymans 3c1e986119 soc/intel/broadwell: Use common sb code for SPI lockdown configuration
Change-Id: I5a8239f4e9e1f9728074ff5452c95d3138965d82
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36005
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-10 22:41:43 +00:00
Arthur Heymans 5efee3a2c2 soc/intel/broadwell: Don't reinitialize SPI after lockdown
With the common southbridge SPI code reinitialization after lockdown
is not necessary, hence the SMM finalize call becomes a no-op.

Change-Id: I4d7c6ba91dc9f0e0ce4e3228fdf859d5f3d5abf4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36004
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-10 22:41:33 +00:00
Arthur Heymans 95755dd65d soc/intel/broadwell: Use common INTEL_SB SPI code
Change-Id: Id906733ac3719c8d6835aad52ca87beb81b5771d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33203
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-10 22:41:19 +00:00
Arthur Heymans 2abbe46765 soc/intel/broadwell: Use common SB RTC code
Change-Id: Iedb9a8962ac1b4107e9192b0be610fb92d2cfdc6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33202
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-10 22:40:59 +00:00
Arthur Heymans 1d4bdda47f sb/intel/common: Remove the SOUTHBRIDGE_INTEL_COMMON Kconfig symbol
All code in southbridge/intel/common is now properly guarded by a
Kconfig symbol, making SOUTHBRIDGE_INTEL_COMMON obsolete.

Change-Id: Ifeccfaa9534f903e3f3543e1f9f3d5f3345b461e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36438
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-10 22:40:49 +00:00
Arthur Heymans 23a6c79126 sb/intel/common: Make COMMON_RESET optional
Change-Id: Id706919835100903dd4ebac2bbd2f3a44c2b6b60
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36003
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-11-10 22:40:38 +00:00
Arthur Heymans 074730c14c sb/intel/common: Make linking rtc.c conditional
Change-Id: I7321da453c0d9bb4a142c3c93103d8dc0ff416b7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33201
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-10 22:39:46 +00:00
Arthur Heymans 1c54bc4849 lib/cbmem: Remove the cbmem_top_init() hook
This hook is unused and with the need for initializing storage to
share cbmem_top over other stages gone, there is likely no future
need for this.

Change-Id: I4ba9daea61b6d7b8949bbd2c4fb71d0a0fa20d93
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36369
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-11-10 15:39:00 +00:00
Arthur Heymans 8b7cd43d5d arch/x86: Remove EARLY_EBDA_INIT support
This is unused now.

Change-Id: Ie8bc1d6761d66c5e1dda40c34c940cdba90646d2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36363
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-11-10 15:38:45 +00:00
Arthur Heymans 005e25de0f soc/intel/common/ebda: Drop code
There is no need to use EBDA to pass cbmem_top from romstage to
later stages.

Change-Id: I46e2459ff3c785f530cabc5930004ef920ffc89a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36362
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-10 15:38:25 +00:00
Arthur Heymans cf5af24a94 soc/intel/common/sa: Remove EBDA dependency
Saving cbmem_top across stages is not needed anymore so EBDA should
not be used. The guard to cbmem_top_chipset implementation was
inappropriate.

Change-Id: Ibbb3534b88de4f7b6fc39675a77461265605e56e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36614
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
2019-11-10 15:38:17 +00:00
Arthur Heymans c4c5d85c22 lib/Kconfig: Remove RAMSTAGE_CBMEM_TOP_ARG
All targets now have the _cbmem_top_ptr symbol populated via calling
arguments or in the nvidia/tegra210 case worked around by populating
it with cbmem_top_chipset explicitly at the start of ramstage, so the
Kconfig guarding this behavior can be removed.

Change-Id: Ie7467629e58700e4d29f6e735840c22ed687f880
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36422
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-10 11:46:29 +00:00
Arthur Heymans 55069d15d8 arch/riscv: Pass cbmem_top to ramstage via calling argument
Tested on the Qemu-Virt target both 32 and 64 bit.

Change-Id: I5c74cd5d3ee292931c5bbd2e4075f88381429f72
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36558
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-10 11:46:10 +00:00
Arthur Heymans 7f22933e98 Kconfig: Remove untrue comment
In the vast majority of cases the bootdevice is the bottleneck and
compression increases bootspeed.

Change-Id: Id0c11cf6d9a605d24e3148abb8d11a65d48a4529
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-09 22:36:00 +00:00
Kyösti Mälkki 21d6a27ac0 arch/x86: Replace some __SMM__ guards
We generally do not guard source in attempts to reduce
the final object sizes, but rely on garbage collection.

Most of the __unused attributes inserted here will be
removed when remaining __SIMPLE_DEVICE__ guards can
be removed.

Change-Id: I2440931fab4f41d7e8249c082e6c9b5a9cd0ef13
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36641
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-09 11:03:03 +00:00
Kyösti Mälkki be5317f6d0 ELOG: Avoid some preprocessor use
Change-Id: I8daf8868af2e8c2b07b0dda0eeaf863f2f550c59
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36648
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-09 10:50:12 +00:00
Kyösti Mälkki 9dd1a12f9c ELOG: Introduce elog_gsmi variants
This avoids a lot of if (CONFIG(ELOG_GSMI)) boilerplate.

Change-Id: I87d25c820daedeb33b3b474a6632a89ea80b0867
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36647
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-09 10:49:47 +00:00
Arthur Heymans 7e4bfe4b91 mb/asus/p5ql-em: Add mainboard
Tested, working:
- First dimm slot of each channel
- USB, SATA
- CPU FSB at 800, 1067 and 1333MHz
- Libgfxinit on DVI and VGA slot
- PCI slot
- Realtek NIC (configure MAC address in Kconfig)
- PEG slot
- PS2 keyboard

Tested, not working:
- second dimm slot for each channel. Those are hooked up to the second
  rank of the channel, instead of rank 3 and 4. The raminit does not
  support such setups.

Untested:
- PCIe x1 slot, likely works fine
- HDMI

Tested using SeaBIOS 1.12, Linux 4.19.

Change-Id: I88fe9c66dae079cd7eedcc9736c5922defbc0e5a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31323
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-11-09 05:37:09 +00:00
Subrata Banik b8df689a6a soc/intel/tigerlake/acpi: Copy acpi directory from icelake
Clone entirely from Icelake

List of changes on top off initial icelake clone
1. Removed Descriptor Name for Memory mapped SPI flash and
local APIC in northbridge.asl
2. Rearranged code in gpio.asl to move RBUF object under _CRS
and made the file use ASL2.0 syntax.
3. Make use of absolute path for scs.asl
4. Remove unused smbus.asl
5. Rearranged code in nothbridge.asl to move MCRS object under _CRS,
use absolute variable path and added TODO for further clean up.
6. Refer absolute variable path in scs.asl

Change-Id: If967cb5904f543ce21eb6e89421df0e5673d2238
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36553
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-11-09 03:26:54 +00:00
Subrata Banik 91e89c5393 soc/intel/tigerlake: Do initial SoC commit till ramstage
Clone entirely from Icelake

List of changes on top off initial icelake clone
1. Replace "Icelake" with "Tigerlake"
2. Replace "icl" with "tgl"
3. Replace "icp" with "tgp"
4. Rename structure based on Icelake with Tigerlake
5. Remove and clean below files
   5.a Clean up upd override in fsp_params.c,
	will be added once FSP available.
   5.b Remove __weak functions from fsp_params.c
   5.c Remove dGPU over PCIE enable Kconfig option
6. Add CPU/PCH/SA EDS document number and chapter number
7. Remove unnecessary headers from .c files based on review

Tiger Lake specific changes will follow in subsequent patches.
1. Include GPIO controller delta over ICL
2. FSP-S related UPD overrides as applicable

Change-Id: Id95e2fa9b7a7c6b3b9233d2c438b25a6c4904bbb
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36087
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-09 03:26:34 +00:00
Subrata Banik baf6d6e203 soc/intel/tigerlake/romstage: Do initial SoC commit till romstage
Clone entirely from Icelake

List of changes on top off initial icelake clone
1. Replace "Icelake" with "Tigerlake"
2. Replace "icl" with "tgl"
3. Replace "icp" with "tgp"
4. Rename structure based on Icelake with Tigerlake
5. Remove and clean below files
   5.a Clean up upd override in fsp_params.c,
	will be added once FSP available.
   5.b Remove __weak functions from fsp_params.c
6. Add CPU/PCH/SA EDS document number and chapter number
7. Add required headers into include/soc/ from ICL directory

Change-Id: I24980c196efb2c5569996ca4fb315c256cf9de87
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36552
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-09 03:26:23 +00:00
Subrata Banik 930c31c63a soc/intel/tigerlake/bootblock: Do initial SoC commit till bootblock
Clone entirely from Icelake

List of changes on top off initial icelake clone
1. Replace "Icelake" with "Tigerlake"
2. Replace "icl" with "tgl"
3. Replace "icp" with "tgp"
4. Rename structure based on Icelake with Tigerlake
5. Add CPU/PCH/SA EDS document number and chapter number
6. Add required headers into include/soc/ from ICL directory

Tiger Lake specific changes will follow in subsequent patches.
1. Add Tigerlake specific device IDs (CPU/PCH/SA)

Change-Id: Id7a05f4b183028550d805f02a8078ab69862a62e
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36550
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2019-11-09 03:26:10 +00:00