This change moves all ACPI table support in coreboot currently living
under arch/x86 into common code to make it architecture
independent. ACPI table generation is not really tied to any
architecture and hence it makes sense to move this to its own
directory.
In order to make it easier to review, this change is being split into
multiple CLs. This is change 3/5 which basically is generated by
running the following command:
$ git grep -iIl "arch/acpi" | xargs sed -i 's/arch\/acpi/acpi\/acpi/g'
BUG=b:155428745
Change-Id: I16b1c45d954d6440fb9db1d3710063a47b582eae
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40938
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Let's gather some documentation ideas for the season of docs. I reused
the project ideas style (thanks Patrick). Feel free to add yourself as a
mentor here. Also if you have more ideas, please add them to the
document.
Change-Id: I72221cbd53b99cdc946109753cf72af9c865a1e5
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40662
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update all occurrences of vboot and spell it lowercase.
Change-Id: I432b0db8a3dda43b71844e557a3d89180f25f1c3
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Marcello Sylvester Bauer <sylv@sylv.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Remove entries for old utilities and add entries for new ones.
Generated using util/util_readme, with some tweaks to preserve the
markdown.
Change-Id: I3a4d8a6bf15a677aa07aa72b8809328110fb72da
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40504
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Later EliteBooks use different EC chips and have different EC firmware
interfaces, so rename the document elitebook_series.md to a more
precise name and also do some rewriting.
A link to the code review page for 8760w is also added because the
port for this laptop is not merged yet.
Change-Id: I2f9b8c4e52ed760c16977d16838cca9e490cda05
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40315
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Some features are made mandatory, meaning that some platforms have
been dropped from master. This also explains that further development
on these popular platforms can happen on the 4.11 branch.
TODO is this really the right place or is it too technical for release
notes?
Change-Id: I95e01c301e7db6f81ef88a89d709ebab35c9ccfb
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37064
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Set IgdDvmt50PreAlloc to zero if InternalGfx is disabled. It's 'correct'
to do it like this, otherwise the FSP would always allocate memory for
the IGD even if it is disabled. In addition the FSP enables the graphics
panel power even if no IGD is present which leads to a crashing FSP.
Thus, if no IGD is present we switch off the panel via UPDs.
Refer to this issue on IntelFSP for details:
https://github.com/IntelFsp/FSP/issues/49
Tested on:
* CFL platform with IGD
* CFL platform without IGD
Change-Id: I6f9e0f9855224614471d8ed23bf2a9786386ddca
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39454
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
We can make our lifes much easier by removing its dependency on
`ADD_FSP_BINARIES`. Instead, we imply the latter if the repository
is to be used. We can also hide a lot of unnecessary prompts in
this case.
Also, remove default overrides and selects for the two that are
now unnecessary.
Change-Id: I8538f2e966adc9da0fbea2250c954d86e42dfeb3
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39882
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update the Lenovo Ivy Bridge documentation that no issues could be
observed on W530.
Tested on Lenovo W530 with stripped ME and found no issues:
commit 93b0c7cfc6
* USB
* Bluetooth
* Wifi
* Wifi-kill switch
* libgfxinit
* SATA
* mSATA
* Audio
* SD-card
* Ethernet
* Keyboard
* Fn-Keys
* Display brightness
* ACPI S3 resume
* CPU temperature reporting
* Stress test stable (intel_pstate no_turbo due to W530 overheating bug)
* Youtube videos
* stress -c 8 -m 1 -t 3600
Change-Id: I46d23d41cc6ade5e641a6ddb3f357a6036002edc
Signed-off-by: Marcello Sylvester Bauer <sylv@sylv.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39603
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fix "WARNING: document isn't included in any toctree" by adding
the lemp9 to mainboard/index.md.
Change-Id: Id6d8f9e2aab6dc7ad4baf1b37d88e531acb757f4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39800
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The ACPI Spec 2.0 states, that Processor declarations should be made
within the ACPI namespace \_SB and not \_PR anymore. \_PR is deprecated
and is removed here for Intel CPUs only.
Tested on:
* X11SSH (Kabylake)
* CFL Platform
* Asus P8Z77-V LX2 and Windows 10
FWTS does not return FAIL anymore on ACPI tests
Tested-by: Angel Pons <th3fanbus@gmail.com>
Change-Id: Ib101ed718f90f9056d2ecbc31b13b749ed1fc438
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Add a script generated list of vboot enabled devices to the
documentation. Add a entry to the release checklist.
Change-Id: Ibb57d26c5f0cb8efd27ca9a97fd762c25b566f93
Signed-off-by: Marcello Sylvester Bauer <sylv@sylv.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39200
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The 51nb X210 is a replacement motherboard for Thinkpad X200/X201 systems,
based on a modern Kabylake CPU. It also ships with no firmware protection,
(IFD is fully unlocked, no protected regions are set, no Bootguard),
making it an ideal coreboot target. This port is based on the support for
the Skylake-based Purism Librem 13v3, with the following significant
changes:
* EC firmware is contained within the system SPI flash, and so a blob of
EC firmware must be injected to a defined location during image build.
* GPIO layout is different - this is currently just a raw import of the
GPIO configuration from the vendor firmware
* The system has two DIMMs, so an additional SPD address has been added
* The USB port layout is different
* The EC must be enabled at boot time through SuperIO-style logical device
configuration
* EC register layout is different, necessitating changes in the ACPI tables
* The HDA pins are different
* The genx_dec config is different
All hardware appears to work as expected, although the SD reader is
untested.
Signed-off-by: Matthew Garrett <mjg59@google.com>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Change-Id: If74621e76d703f629b54f1feb1acfc95cc72d183
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32531
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The code in coreboot is actually for the Arrandale processors, which
are a MCM (Multi-Chip Module) with two different dies:
- Hillel: 32nm Westmere dual-core CPU
- Ironlake: 45nm northbridge with integrated graphics
This has nothing to do with the older, single-die Nehalem processors.
Therefore, replace the references to Nehalem with the correct names.
Change-Id: I8c10a2618c519d2411211b9b8f66d24f0018f908
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38942
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There seems to be no board using this, but some currently under review.
Remove the DSDT, which doesn't work together with the SSDT ACPI
code generation. Also update the documentation pointing to the SSDT
generator.
Change-Id: I8b7daeadaaac93d74ee2fc9eb18f0eff5ef50eb3
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38864
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
austin-3 was a devel board, retracting
t60 comes in variants with discrete gpu and only intel gpu one
Change-Id: Ic1f7397b8676bdcc15f63d59d87518d35bba5b4d
Signed-off-by: Sebastian "Swift Geek" Grzywna <swiftgeek@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34352
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Changes allow to use the integrated panel logic (power sequen-
cing and backlight control) for more connectors. The Kconfigs
GFX_GMA_PANEL_1_PORT and GFX_GMA_PANEL_2_PORT can now be set
to any port, e.g.
config GFX_GMA_PANEL_1_PORT
default "DP3"
Now that the panel logic is not tied to the `Internal` port
choice anymore, we can properly split it into `LVDS` and `eDP`.
This also adds Comet Lake PCI IDs which should still work the
same as Kaby and Coffee Lake.
Change-Id: I78b1b458ca00714dcbe7753a7beb4fb05d69986b
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38921
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
- Add a common page about Montevina ThinkPads.
- Describe how to disable ME and remove its firmware on these models.
- Describe vendor flash layouts.
Thanks to swiftgeek for his help when writing this, especially the last
paragraph and flash layouts.
Change-Id: I85917821efe63fff4b933b6226e99c17b63eb1b9
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38926
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This is a port of https://review.coreboot.org/c/coreboot/+/22337 to the
Haswell northbridge. This code is necessary to support the dGPU of the
t440p. Code was cut and pasted from Sandy Bridge with vendor IDs updated
to the correct Haswell values. Tested on t440p with dGPU on Ubuntu
18.04.4 with 5.3.0-28 kernel. Without patches dmesg reports Nouveau is
unable to read the VBIOS of the dGPU as it has an invalid checksum (I
checked that the ROM in CBFS is correct). With this patch DRM works
correctly with both the Nouveau driver and the Nvidia proprietary
driver. Windows 10 1909 also tested but generates bluescreen once GPU
driver is loaded.
Change-Id: Ie5f089fb6fd774e6c61f4f9281e2945bd44edf27
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38743
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
It somehow creeps into `make clean`, but is not used at all. Since no
VIA platform remains in coreboot, drop the utility as well.
Change-Id: Ia7e11379a6db650b5190a056226a9101c2be7dec
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38853
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Add new helper function in the acpigen library, that use the underlying
soc routines.
Change-Id: I8d65699d3c806007a50adcb51c5d84567ce451b7
Signed-off-by: Rajat Jain <rajatja@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39145
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
Add a small description about Heads.
Change-Id: I2e768a640751fee1b1b5df4401205e24cde0607c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Add a tutorial how to use ME cleaner, and give some basic steps to
strip the ME. Update the Lenovo Sandy Bridge documentation that no
issues could be observed on X220 and give an example flash layout.
Tested on Lenovo X220 with stripped ME and found no issues:
commit: cbc5b99ac9
* Displayport
* VGA
* USB
* Bluetooth
* Wifi
* Wifi-kill switch
* libgfxinit
* SATA
* Audio
* SD-card
* Ethernet
* Keyboard
* Fn-Keys
* Display brightness
* ACPI S3 resume
* Battery events
* CPU temperature reporting
* FAN managment
* Stress test stable
* Youtube videos over Wifi
* stress -c 2 -m 1 -d 1
* glxgears
Change-Id: I0b1d04f00b5dbb38cf04333f2b345749b740a375
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39129
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The coverity project is done, for the most part, so drop it. Expand
a bit on the scope of the toolchain binary project, and point out
that the Ghidra project already has code from GSoC 2019 but could be
developed further.
Change-Id: I7342cc3133494f69b175b11b1f8342a0f40840e7
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39086
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Currently, tables on this page are formatted as code blocks with
ASCII tables. Make it real beautiful tables.
Change-Id: I3c46477352b8151f3b0fb0616f909531a0a15c34
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38956
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Peter Lemenkov <lemenkov@gmail.com>
- Fix lists markup
- Some minor fixes in the text (e.g. lowercases)
Change-Id: I812bdbeed6609c31f3428a3020fa4b32ebbb3445
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38948
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Latest Sphinx supports up path traversal in markdown. Replace old
RST code that's no longer needed to prevent it being copy and pasted.
Change-Id: Ieec5cc1f8d91a7fbc003efae465f61e6b72b39dc
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38930
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Replace xx30 with Ivy_Bridge and xx20 with Sandy_Bridge.
Also add a note that the Ivy_Bridge tutorial doesn't covert T430s and T431s.
Change-Id: I0b65bca83195ec22cc139130e7cb6183c0972484
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38929
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Change-Id: Id12ec4d5f11f4285a1379cf32a5d0f6cd2ce9e70
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38519
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Add additional information on non-debian cli tools
* Improve spellings and descriptions to the best of my knowledge
Adding info about needed tools in other distribution's package
managers was requested at the coreboot beginner's workshop at 36C3.
Change-Id: Ifff3c8354b4bec9f195f075eb6b2f377195fc237
Signed-off-by: Patrik Tesarik <mail@patrik-tesarik.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38225
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The Picasso no longer intends to implement a hybrid romstage,
opting instead for a more traditional bootblock/romstage/ramstage.
Update the documentation to reflect this. Clarify additional
details that have come to light since the last revision.
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I6c98c007ddb8a4a05810f19e4215bde719de7bb8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38713
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This has been implemented last year.
Change-Id: I24e40a7a9a9d7238b8c9d34656d5b62a26b8252b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38533
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Both versions are correct, but especially for one liners indenting them
with four spaces instead of using ``` blocks helps readability of the
source file.
Change-Id: Ie2543c8c4cccefd74e966f784e651ed7dc3a9252
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38720
Reviewed-by: Peter Lemenkov <lemenkov@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update the security document to reflect the current state of the
coreboot implementation.
Add more detail and document the change to the public vboot API.
BUG=N/A
TEST=build
Change-Id: I228d0faae0efde70039680a981fea9a436d2384f
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38591
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update to reflect the beta status of the code.
BUG=N/A
TEST=build
Change-Id: I9d1c42d24578c9420569da7e294d5c723da3c772
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38607
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Add description of the procedure to create the flash components for this
system.
BUG=N/A
TEST=N/A
Change-Id: I2690dfbe715fa120f840d98c57fdc3fd7e8b45b1
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
The System76 Lemur Pro (lemp9) is an upcoming laptop computer. Support
in coreboot is developed by System76 and provided as the default
firmware option. Testing is done on a pre-production model expected to
be identical from a firmware perspective to the production model.
Working:
- Payload
- Tianocore
- CPU
- Intel i7-10510U
- Intel i5-10210U
- EC
- ITE IT5570E running https://github.com/system76/ec
- Backlit Keyboard, with standard PS/2 keycodes and SCI hotkeys
- Battery
- Charger, using AC adapter or USB-C PD
- Suspend/resume
- Touchpad
- GPU
- Intel UHD Graphics 620
- GOP driver is recommended, VBT is provided
- eDP 14-inch 1920x1080 LCD
- HDMI video
- USB-C DisplayPort video
- Memory
- Channel 0: 8-GB on-board DDR4 Samsung K4AAG165WA-BCTD
- Channel 1: 8-GB/16-GB/32-GB DDR4 SO-DIMM
- Networking
- M.2 PCIe/CNVi WiFi/Bluetooth
- Sound
- Realtek ALC293D
- Internal speaker
- Internal microphone
- Combined headphone/microphone 3.5-mm jack
- HDMI audio
- USB-C DisplayPort audio
- Storage
- M.2 PCIe/SATA SSD-1
- M.2 PCIe/SATA SSD-2
- RTS5227S MicroSD card reader
- USB
- 1280x720 CCD camera
- USB 3.1 Gen 2 Type-C (left)
- USB 3.1 Gen 2 Type-A (left)
- USB 3.1 Gen 1 Type-A (right)
Not working:
- TPM2 - SPI bus 0, chip select 2 is used. Chip selects other than 0
are not currently supported by the intel fast_spi driver.
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Change-Id: Ib0a32bbc6f89a662085ab4a254676bc1fad7dc60
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38463
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The new documentation describes typical ways that mainboards will
set up their GPIOs, as well as the distinction between "early"
and "normal" GPIOs. It also describes the typical properties
that GPIO configuration will cover.
Change-Id: I279eec4ed2bb0248a2bdb363fb73b40b8272267f
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37802
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Also update the known-good versions of the needed tools.
Change-Id: I0f63860beb0a8a00360752318236e302c7170977
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37952
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Add function to generate unique _UID using CRC32
* Add function to write the _UID based on a device's ACPI path
ACPI devices that have the same _HID must use different _UID.
Linux doesn't care about _UID if it's not used.
Windows 10 verifies the ACPI code on boot and BSODs if two devices
with the same _HID share the same _UID.
Fixes BSOD seen on Windows 10.
Change-Id: I47cd5396060d325f9ce338afced6af021e7ff2b4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37695
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
The BMC and tools interacting with it depend on metadata placed inside
the ROM in order the flash the BIOS.
Add a new tool smcbiosinfo, integrate it into the build system, and
generate a 128byte metadata file called smcbiosinfo.bin on build.
You need to provide the BoardID for every SMC mainboard through a new
Kconfig symbol: SUPERMICRO_BOARDID
Some fields are unknown, but it's sufficient to flash it using SMC
vendor tools.
Tested on Supermicro X11SSH:
* Flashing using the WebUI works
* Flashing using SMCIPMITool works
No further validation is done on the firmware.
Change-Id: Id608c2ce78614b45a2fd0b26d97d666f02223998
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Substitute `Part` with `Step` on this file's headings and use present
tense instead of gerund.
Change-Id: Ic130ed9865be43716e7de3121534761d9fc2ae8d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37933
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
Make sure all titles are capitalized, and add a missing period.
Change-Id: I48b8d6c85b915cc422bdfa3a89804f92f46800ba
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37932
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
Use periods on every element of a list, and make `IRC` uppercase.
Also, correct a grammar mistake that slipped through.
Change-Id: Id05865719c7c845265416e89bfd9b02b6d22ca6c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37709
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* Make use of introduced SSDT config mode access
* Make use of introduced SSDT mutex
* Provide ACPI functions to safely access SIO config space
* Implement method to query LDN enable state
* Implement method to set LDN enable state
* Use introduced functions to implement _DIS and _STA in the device
* Update documentation
Tested on Aspeed AST2500 and Linux 5.2.
Manually verified ACPI code that generates no errors in Linux.
Change-Id: I520b29de925f368cd71ff8f1f58d2d57d72eff8d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Make it part of the release process to note not only what config flags /
code properties etc will be deprecated, but to also spell out which
boards would be affected at the time of the release.
Change-Id: I0ef1404e75182ea4bacae31edb0a843e7a359545
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37702
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The table wasn't pretty enough so sphinx complained, while the second
paragraph had trailing whitespace, could be wrapped differently and
also came with a typo.
Change-Id: I6c16a3a1fcc306d0b12043ebec7d4e69e9339d7d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Disabling SSL verification is far from optimal, but depending on the
circumstances may be the most practical way, so describe how to do
that instead of leaving users confused.
It's also not _that_ bad because git's hashing scheme should uncover
most attempts to tamper with code, either when checking signed tags
or when people push (and see lots of modified commits).
State the command in a way that isn't conductive to careless
copy & paste.
Change-Id: Idbd52ba5d6e8b0f0e891fca16e4159ccef10771a
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37599
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
We are already in documentation so it should be obvious that other
links point to other documentation.
Change-Id: I7a021a09bdb88418ec85dbf433465f26445057d0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37241
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The board is booting Linux and has been briefly tested.
SeaBIOS, TianoCore payload and Linux as payload all seem to work fine.
BUG=N/A
TEST=tested on Facebook Monolith
Change-Id: I65a2e03334af65cfb3f825d43fa0daa6e6c75913
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37516
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
This documents the smmstore API.
Change-Id: I992c04c0cf9b3f03755cf3fede2c82c6471a5ef4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37243
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This patch does two things:
- The CLI and Git Cola sections contained some duplicated information
about pushing patches, which is now factored out into its own section.
- The draft workflow is now disabled, so that part has been reworded to
describe how to submit a private patch.
Signed-off-by: David Hendricks <david.hendricks@gmail.com>
Change-Id: I562c101ab2ee78d901be7e99165daba7473dc3c1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37256
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Having the release notes mostly ready one week before the release
allows for better review.
Some statistics, the actual release date and commit ID can only be
filled in on release day, but there's a tried & true technique for
that: placeholders.
It's also a nice touch to have the release notes of a release within
its source tarballs, so push them right before creating the release
(since changes in Documentation/releases won't break coreboot in
any way).
Change-Id: Iad7ba1ba4fc841bf437f2a997428b7f636e15422
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36957
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The MIPS architecture port has been added 5+ years ago in order to
support a Chrome OS project that ended up going nowhere. No other board
has used it since and nobody is still willing or has the expertise and
hardware to maintain it. We have decided that it has become too much of
a mainenance burden and the chance of anyone ever reviving it seems too
slim at this point. This patch eliminates all MIPS code and
MIPS-specific hacks.
Change-Id: I5e49451cd055bbab0a15dcae5f53e0172e6e2ebe
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34919
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
After removing urara no board still uses this SoC, and there are no
plans to add any in the future (I'm not sure if the chip really exists
tbh...).
Change-Id: Ic4628fdfacc9fb19b6210394d96431fdb5f8e8f1
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36491
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fill in some stats using our repo analysis scripts in
util/release/, thank the contributors, add some prose
about notable achievements since 4.10.
Also start a new doc for 4.12.
Change-Id: I10a39081762d6e01f4040f717d36662975e4c8e9
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36948
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The mainboard was accidently added due to bad rebase.
Change-Id: Ie7215e551651dbbc8d92316c48e455405923a30b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36077
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The microcode is available in 3rdparty microcode now.
This ucode can be used.
BUG=N/A
TEST=build
Change-Id: I52a04c7dc97608f868ee0b415bbbb328937f18f7
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Furquan Shaikh