coreboot-kgpe-d16

Commit Graph

Author	SHA1	Message	Date
Michael Niewöhner	a911216926	docs: intel fsp: add memory retraining bug on SPS systems FSP2.0 forces MRC retraining on cold boot on Intel SPS systems. Change-Id: I3ce812309b46bdb580557916a775043fda63667f Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36935 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>	2019-11-19 12:56:10 +00:00
Andrey Petrov	ee0b7ad683	mainboard/ocp/monolake: Hide IIO root ports before memory init It turned on some SKUs FSP hangs in Notify stage if IIO root ports are disabled after MemoryInit. To address that hide IIO root ports earlier in romstage. TEST=the patch was ran on affected HW and success was reported Change-Id: I6a2a405f729df14f46bcf34a24e66e8ba9415f9d Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35968 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>	2019-10-16 14:11:17 +00:00
Subrata Banik	fb6ea0af40	Documentation/soc/intel/fsp: Add link for external FSP2.1 spec Change-Id: I5d1abd6252bda2be09285cd878a483f055abcd7b Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35238 Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>	2019-09-04 10:56:22 +00:00
Patrick Rudolph	96d8e43178	Documentation: Add FSP bugs As Intel doesn't even document known bugs add a list of FSP bugs here. Change-Id: I07819b83fb0c9437fc237472dfe943f78738347a Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34239 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>	2019-07-15 07:14:57 +00:00
Subrata Banik	ebac8c772f	Documentation/soc/intel/fsp/ppi: Document new feature to dispatch external PPI Some new feature added into FSP specification to perform dispatching of external PPI service from boot firmware (coreboot) to FSP. Change-Id: Iaf6b54ccd27e21860539bb2a9966054fdb027108 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31839 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>	2019-03-12 04:23:58 +00:00
Subrata Banik	abc5130108	Documentation/soc/intel: Add documentation for Intel FSP This patch combines open source documentation for Intel FSP specification. Change-Id: I3a8bc0198a1e01ec019139b728834713978501ba Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31838 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>	2019-03-12 04:23:00 +00:00

6 Commits