Commit Graph

1754 Commits

Author SHA1 Message Date
Stefan Reinauer 0db924d74c cbmem: print timestamp names
The numbers alone are hard to parse, so add
some timestamp names to make it easier to read.

Change-Id: Ie32d3e7ca759bd15e7c160bdd829dec19943e6cb
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/65333
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: http://review.coreboot.org/4314
Tested-by: build bot (Jenkins)
2013-12-05 19:23:49 +01:00
Stefan Reinauer d8ef9e9e9b Fix timestamp output in cbmem utility on ARM
On ARM the timestamps are already in micro seconds, so
no need to convert them.

Signed-off-by: Stefan Reinauer <reinauer@google.com>

Change-Id: If7363b0703e144bde62d9dab4ba845e1ace5bd18
Reviewed-on: https://gerrit.chromium.org/gerrit/63991
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
Tested-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: http://review.coreboot.org/4313
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-05 19:23:40 +01:00
Patrick Georgi 274c6c2177 Add scripts to export board status data to wiki
It's a start...

Change-Id: Ibdb0b64ab0349df58bcad5ce553bf0dbec636925
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/4483
Tested-by: build bot (Jenkins)
2013-12-05 18:40:25 +01:00
Stefan Reinauer a9c8361c02 cbmem: fix userspace utility to work with dynamic CBMEM
This also adds an option -x/--hexdump to dump the whole
CBMEM area for debugging.

Change-Id: I244955394c6a2199acf7af78ae4b8b0a6f3bfe33
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/62287
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
Tested-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: http://review.coreboot.org/4312
Tested-by: build bot (Jenkins)
2013-12-04 22:21:13 +01:00
Stefan Reinauer 7f68150f1e cbmem: Implement ARM support
on ARM the CBMEM utility requires the procfs entry
/proc/device-tree/firmware/coreboot/coreboot-table
provided by the FDT (dynamically created by depthcharge
at the moment)

Signed-off-by: Stefan Reinauer <reinauer@google.com>

Change-Id: If5f961afb23791af6f32dd4fc9a837a1aa41b70e
Reviewed-on: https://gerrit.chromium.org/gerrit/59322
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Tested-by: Stefan Reinauer <reinauer@chromium.org>
Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: http://review.coreboot.org/4311
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-04 22:21:03 +01:00
Aaron Durbin 8a0cb8de65 cbfstool: check potential microcode update earlier
The update-fit command takes in a parameter for number of slots
in the FIT table. It then processes the microcobe blob in cbfs
adding those entries to the FIT table. However, the tracking of
the number of mircocode updates was incremented before validating
the update. Therefore, move the sanity checking before an increment
of the number of updates.

Change-Id: Ie8290f53316b251e500b88829fdcf9b5735c1b0e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/50319
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4161
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25 23:24:57 +01:00
Stefan Reinauer 8c5947709a cbmem utility: compatibility with older coreboot versions
Commit b8ad224 changed the memory address in lb_cbmem_ref coreboot
table entries from a pointer to a uint64_t. This change was introduced
to make the cbmem utility work on both 32bit and 64bit userland.
Unfortunately, this broke the cbmem utility running on older versions
of coreboot because they were still providing a 32bit only field for
the address while the cbmem utility would now take the following 4
bytes as upper 32bits of a pointer that can obviously not be
mmapped. This change checks if the size of the lb_cbmem_ref structure
provided by coreboot is smaller than expected, and if so, ignore the
upper 32bit of the address read.

Signed-off-by: Stefan Reinauer <reinauer@google.com>

Change-Id: If4c8e9b72b2a38c961c11d7071b728e61e5f1d18
Commit-Queue: Stefan Reinauer <reinauer@google.com>
Tested-by: Stefan Reinauer <reinauer@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4139
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25 23:02:07 +01:00
Patrick Georgi c37b05c413 nvramtool: write size field more obviously
The field wasn't initialized in RAM first and later overwritten in a somewhat
twisted way (that relied on the size field coming after the tag field in the
struct).

Change-Id: Ibe931b297df51e3c46ae163e059338781f5a27e2
Found-by: Coverity Scan
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/4087
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2013-11-19 00:59:55 +01:00
Ronald G. Minnich 72f15bd2be cbfstool: add a constant for the aarch64
Change-Id: Ide2c8b778447de66d95bd8c55b378aa2051ac2a0
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: http://review.coreboot.org/4091
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-11-18 16:58:58 +01:00
David Hendricks a4affe17f1 board_status.sh: trivial cosmetic changes toward the end
This moves an ugly comment closer to where it is applicable and also
adds a visual break between the commands which gather data and the
part of the script that finishes up. I'm usually not fan of banner
comments, but it seemed to help in my totally subjective opinion.

I was thinking about how to break the part that uploads results into
a separate function, but there are enough variables that are re-used
from earlier parts that the tradeoff probably isn't worth it.

Change-Id: If888329911c4de3b907cdf5973695c707bbb02fe
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/4051
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-17 10:32:22 +01:00
David Hendricks 406ce8a06e board_status.sh: pass filename as an arg to command wrappers
This allows the command wrappers to delete files if the command
fails. In particular, it delets empty or otherwise useless files
that are generated if a non-fatal command fails.

Change-Id: If26d7b4d7500f160edd1cc2a8b6218792fefae8b
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/4050
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-17 10:32:14 +01:00
David Hendricks f8b90e4622 board_status.sh: add support for non-fatal commands
This adds cmd_nonfatal() for commands which are considered
non-essential and can be expected to fail safely. This can be used,
for example, to gather data that is generated when using non-standard
utilities or coreboot config options.

Change-Id: Ie43944d2eb73f9aae1c30c3a204cfc413e11d286
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/4049
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-17 10:32:07 +01:00
David Hendricks 1fc65f76f4 board_status.sh: move show_help()
This is really only a cosmetic change, but is intended to make it
slightly easier to remember to update the help menu whenever
options change.

Change-Id: I58b5012309229d08da138a01c7cd1c5096423179
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/4048
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-17 10:31:37 +01:00
David Hendricks 16955fd665 board_status.sh: Make clobber option use 'C' instead of 'c'
Clobbering output is only really useful when debugging the script.
Since we're only using short options, let's save 'c' for something
more important.

Change-Id: If87a70fdc0cd006818d1736c40f9984dfec663a9
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/4047
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-17 10:31:30 +01:00
David Hendricks 1b6e7a6748 Updates to the board status script
This is the first major re-work for the board status script.
Summary:
- Added a command to the getrevision.sh script to retrieve tagged
  revision.

- Results are placed in a dynamically generated temporary location.
  This makes it easy to do multiple trial runs and avoids polluting
  the coreboot directory.

- Results are stored in a directory with the following form:
  <vendor>/<mainboard>/<tagged_revision>/<timestamp>/
  Vendor and mainboard are obtained from CONFIG_MAINBOARD_DIR so that
  hierarchy is consistent between coreboot and board-status.

- The results directory is used as the commit message.

- board-status repository is checked out automatically if results are
  to be uploaded.

TODO:
- Add ability to run commands which may fail. Currently we assume
  any failure should terminate the script, but some commands can be
  made optional.

Successfully uploaded first result to board-status repository. See
http://review.coreboot.org/gitweb?p=board-status.git;a=summary .

Change-Id: Icba41ccad4e6e6ee829b8092a2459c2d72a3365b
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/4039
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-17 10:31:17 +01:00
Patrick Georgi 0dde01cad1 romcc: Fix off-by-one
Arrays are indexed 0..(number_of_element-1).

Change-Id: I2157e74340568636d588113d1d2d8cae50082da2
Found-by: Coverity Scan
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/4089
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2013-11-16 09:49:35 +01:00
David Hendricks c5e947ef17 rename status-related stuff to board_status
This just moves stuff to be more clear about the purpose of
the script. Other suggestions are welcome.

Change-Id: Ic6095fd4eb347daa5a03eff21b5952d2d42a6bfd
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/4038
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-11-12 20:14:23 +01:00
Ronald G. Minnich 12785d9601 util/xcompile/xcompile: set up for aarch64
The tools for aarch64 on ubuntu are called
aarch64-linux-gnu-*
The type is
elf64-littleaarch64

This now finds the right files for building on aarch64

This has only been tested on ubuntu saucy; the aarch64 toolchain
is in a very ill-defined state on most distros.

Change-Id: Ic1bbd40f0d72384d6e80287b850686292a252918
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: http://review.coreboot.org/4035
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-11-10 04:41:30 +01:00
Zheng Bao 86655cf835 Trivial: Remove trailing whitespaces in status.sh
The whitespaces make "git commit" failed.

lint-stable-003-whitespace
Check for superfluous whitespace in the tree
========
test failed:
File util/status/status.sh has lines ending with whitespace.
========

Change-Id: I52fc5ae3e5aa81dac098b36d2479e4d10325a09b
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/4032
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2013-11-07 11:59:24 +01:00
David Hendricks 6583a8108c Another pass at board status script
This reports relevant bits of information about a machine which is
running coreboot. This also includes a script to get revision info
from git, which we may want to split out into another patch.

A remote target can be specified since it is likely that the machine
used to develop the code is not the same machine being developed for.
The remote host must be set up for non-interactive root login.

Example: sh util/status/status.sh -r gizmoboard -u

Change-Id: Ief0a85faca2ec9ce2d270e1e5b09e74836ab0c97
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/4021
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-04 17:11:35 +01:00
Paul Menzel 569ad760cc util/lint/lint-stable-003-whitespace: Ignore temporary files ending with a tilde
Some editors like gedit create auxiliary files ending with a
tilde '~'. As these are not checked into the Git repository, do
not check these for whitespace errors.

Change-Id: I2c4cf00f9d623be73ea3bbb7b2da4f1e1900c8e9
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3952
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
2013-10-22 04:17:30 +02:00
Andrew Wu cd9abf95e7 arch/x86/Makefile.inc: Pass $(AS) and $(CPP) to SeaBIOS
SeaBIOS’ Makefile requires cpp (C Preprocessor) to build. Modify
the xcompile script to search for cpp program path, and pass it to
SeaBIOS’ `Makefile.inc`. Also pass the program path for as (GNU assembler).

This is needed, so the crossgcc toolchain to build the SeaBIOS payload
under Mac OSX. OSX ships a cpp program, but it works differently
from GNU CPP, so we need to override it.

Change-Id: If996ffbb76ec4bd16079b54b41f3fac07bfe25be
Signed-off-by: Andrew Wu <arw@dmp.com.tw>
Reviewed-on: http://review.coreboot.org/3896
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
2013-10-17 01:59:50 +02:00
Nico Huber 1bfe37470e lint: Use temporary build directory
`util/lint/lint-stable-002-build-dir-handling` always overwrites your
current `config.h` and `auto.conf` when the pre-commit hook is run. It
can be very confusing when your configuration is suddenly broken. So fix
it by not using the default build directory.

Change-Id: If2bbc97ac2f12a8203a3769d813386a023f93dd6
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/3593
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-09-27 11:51:29 +02:00
Patrick Georgi c8883262cf buildgcc: Downgrade to gcc 4.7.3, handle armv7-a
gcc 4.8.x has issues with using ebp, which broke some builds,
so downgrade. The problem also manifested elsewhere, so it's
not necessarily our fault.

While at it, gcc complained about "armv7a" where it seems to
expect "armv7-a".

Change-Id: I6f0c35f49709cb41022475bb47116c12ab1c7ee3
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/3930
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-09-20 20:42:14 +02:00
Patrick Georgi 3af0aa2533 buildgcc: Use per-arch build directories
This simplifies debugging and also fixes an issue when build directories
are kept between buildgcc runs for different architectures.

Change-Id: I5badccd3368e3014680da3eedb607119fff8fa7f
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/3929
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-09-18 09:38:30 +02:00
Kyösti Mälkki ecd8424919 Fix whitespace leaked into tree
Clean whitespace errors that have gotten past lint-stable-003-whitespace
and gerrit review.

Change-Id: Id76fc68e9d32d1b2b672d519b75cdc80cc4f1ad9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3920
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-09-17 21:04:35 +02:00
Kyösti Mälkki 370ff4af11 lint whitespace: Fix rule to recurse into subdirectories
The rule "-perm +111 -prune" matched any searchable directory
and did not recursively find files in them. The use of "+mode"
for -perm is deprecated.

Change-Id: I1b43f89ee9ab37928e56104b0f07241ff84b84c0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3921
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-09-17 21:03:28 +02:00
Patrick Georgi 2f39eae41d Remove NRV2B compression support
It wasn't even hooked up to the build system anymore.

Change-Id: I4b962ffd945b39451e19da3ec2f7b8e0eecf2e53
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/3892
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2013-08-31 08:58:37 +02:00
Patrick Georgi de36d333c2 Add a (b)zImage parser to cbfstool
In the great tradition of LinuxBIOS this allows adding
a kernel as payload. add-payload is extended to also
allow adding an initial ramdisk (-I filename) and a
command line (-C console=ttyS0).

Change-Id: Iaca499a98b0adf0134e78d6bf020b6531a626aaa
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/3302
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-08-31 08:58:34 +02:00
Zheng Bao 3c4bd91a34 Locate the generated iasl in acpica-unix-20130626
acpica-unix-20130626 doesn't use bin32 and bin64 to save the objects
any more.

Change-Id: I419ecc987e2adcd860a8ad1bf2f6b5c4dd40fd8a
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/3885
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-08-27 19:55:55 +02:00
Paul Menzel 4159a8012e Correct spelling of shadow, setting and memory
Change-Id: Ic7d793754a8b59623b49b7a88c09b5c6b6ef2cf0
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3768
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-08-16 22:25:56 +02:00
Peter Stuge 3bfd5b8252 cbfstool: Add an add-int command that adds a raw 64-bit integer CBFS file
This simplifies storing SeaBIOS parameters in CBFS.

Change-Id: I301644ba0d7a9cb5917c37a3b4ceddfa59e34e77
Signed-off-by: Peter Stuge <peter@stuge.se>
Reviewed-on: http://review.coreboot.org/3733
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-08-15 20:46:09 +02:00
Damien Zammit dcea700762 inteltool: Print raw CPUID and make hexadecimal values unambiguous
The raw CPUID is useful for matching the directories under 'src/cpu/intel'
and is not easy to find out otherwise because it is most often decoded
already. The decoded values are not obviously hexadecimal so prepend
them with 0x to make sure they are unambiguous.

The output differences look like this:
-	CPU: Processor Type: 0, Family 6, Model 25, Stepping 2
+	CPU: ID 0x20652, Processor Type 0x0, Family 0x6, Model 0x25, Stepping 0x2

Change-Id: Id47f0b00f8db931f0000451c8f63ac1e966442c4
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3788
Reviewed-by: Stefan Tauner <stefan.tauner@gmx.at>
Tested-by: build bot (Jenkins)
2013-07-23 12:06:24 +02:00
Stefan Reinauer 0d2119da46 buildgcc: Update reference toolchain
* GCC 4.8.1
 * binutils 2.23.2
 * GDB 7.6
 * ACPICA 20130626
 * Python 3.3.2

... this adds support for Aarch64. For Ron.

Change-Id: Idec91bcd615bc35c83373bd23d4681f1c8eb015c
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/3758
Tested-by: build bot (Jenkins)
Reviewed-by: David Hubbard <david.c.hubbard+coreboot@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-22 20:49:15 +02:00
Benoît Legat f42b83e958 msrtool: Fix verbose ignored by cpuid().
This is a trivial patch moving cpuid() call after reading argv
so that verbose is set.

Change-Id: Ic621191ef650495614a041413c1a0f707d4469e6
Signed-off-by: Benoît Legat <benoit.legat@gmail.com>
Reviewed-on: http://review.coreboot.org/3627
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-08 19:39:00 +02:00
Stefan Tauner e978fc265d cbmem: Fix makefile
The .dependencies rule did not use the CPPFLAGS variable which led
to funny behavior: a spurious termination message the first time
(after checkout/make distclean) one executes make. Afterwards the
(wrongly) empty .dependencies file hides the problem and the binary
is created anyway.

$ make
cbmem.c:37:34: fatal error: boot/coreboot_tables.h: No such file or directory
compilation terminated.
cc -O2 -Wall -Werror -iquote ../../src/include -iquote ../../src/src/arch/x86  -c -o cbmem.o cbmem.c
cc   cbmem.o   -o cbmem

$ make
make: Nothing to be done for `all'.

$ make clean
rm -f cbmem *.o *~

$ make
cc -O2 -Wall -Werror -iquote ../../src/include -iquote ../../src/src/arch/x86  -c -o cbmem.o cbmem.c
cc   cbmem.o   -o cbmem

$ make distclean
rm -f cbmem *.o *~
rm -f .dependencies

$ make
cbmem.c:37:34: fatal error: boot/coreboot_tables.h: No such file or directory
compilation terminated.
cc -O2 -Wall -Werror -iquote ../../src/include -iquote ../../src/src/arch/x86  -c -o cbmem.o cbmem.c
cc   cbmem.o   -o cbmem

I fixed that by adding the CPPFLAGS variable to the .dependencies recipe, just
like Stefan Reinauer did in Chromium (Ia9d2e10a3ef122f30d681d16c2291eb108ead835),
hence the split sign-off for this tiny change. :)

Change-Id: Icd11b146ad762cbdf9774630b950f70e1253a072
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: http://review.coreboot.org/3548
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.huber@secunet.com>
2013-07-01 23:12:22 +02:00
Marc Jones 66a68a2af8 abuild: Add xgcc tools to the path
abuild checks the path for toolchains prior to building a
mainboard. It didn't check xgcc/, which would be picked up
by the coreboot make, and fail to build when it shouldn't.

Change-Id: If0ca4238e8c57a6b015fdad623ccdbf237ef1ba6
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/3350
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-25 00:36:31 +02:00
Nico Huber 413b0d9846 ifdfake - Create an IFD with just a section layout
This new tool called `ifdfake` just creates an empty Intel Firmware
Descriptor (IFD) and writes the IFD signature plus the section layout
given on the command line.

    usage: ifdfake [(-b|-m|-g|-p) <start>:<end>]... <output file>

       -b | --bios       <start>:<end>   BIOS region
       -m | --me         <start>:<end>   Intel ME region
       -g | --gbe        <start>:<end>   Gigabit Ethernet region
       -p | --platform   <start>:<end>   Platform Data region
       -h | --help                       print this help

    <start> and <end> bounds are given in Bytes, the <end> bound is inclusive.
    All regions must be multiples of 4K in size and 4K aligned.
    The descriptor region always resides in the first 4K.

    An IFD created with ifdfake won't work as a replacement for a real IFD.
    Never try to flash such an IFD to your board!

The output of ifdfake can be utilized to build an image with just the
later added sections (like coreboot itself) being valid. The resulting
image can then be partially written to a machines flash ROM to just
update coreboot (i.e. the BIOS section).

Change-Id: I925b47cab5c6d490a79d684bdd7a7a45ac442640
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3523
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-24 17:56:42 +02:00
Kyösti Mälkki 6aeb4a269c AMD: Drop empty root_complex
There are no files to build left under AMD nortbridge/x/root_complex
directories. For some cases, even the Kconfig file was no longer sourced.
Remove all such references and empty files.

For devicetree.cb treat component paths with "/root_complex" in them valid
even when the directory does not exists. This is because AMD boards us this
dummy chip component as the root node in their devicetree.cb.

The generated devicetree file static.c remains unchanged.

Change-Id: I9278ebb50a83cebbf149b06afb5669899a8e4d0b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3434
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-06-24 17:22:44 +02:00
Stefan Tauner dbc6fcd021 inteltool: add initial support for Nehalem
Also, add pretty printing of Westmere's DMI registers (tested on my t410s
by staring at non-zero output values :)

Apparently Nehalem does not have a MEMBAR? But there are some
documented memory controller control registers in PCI configuration
space... left out for now.

The PCIEXBAR is not documented publicly AFAICT, but there is
a similar register on a device on bus 0xFF. phcoder might know more...

Change-Id: I5faadb6e4f701728f5290276c02809b4993bd86d
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: http://review.coreboot.org/3505
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-23 23:36:03 +02:00
Stefan Tauner 088f569400 util/inteltool: Add support for other 5 chipsets
e4e8e090fa does add support for QM57,
but there are many more that should work with that code(?).

Does not explode on...
CPU: Processor Type: 0, Family 6, Model 25, Stepping 2
Northbridge: 8086:0044 (1st generation (Westmere family) Core Processor)
Southbridge: 8086:3b0f (QS57)

Change-Id: I85e15ba45678a5bd635415a7a8d69c05bff8f7ef
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: http://review.coreboot.org/3321
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2013-06-13 11:31:41 +02:00
Vladimir Serbinenko 083d35551c Add spkmodem receiver
This is spkmodem receiver counterpart.

Change-Id: Id27d32608502029fb6fcc8154f508811bf5ca77b
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/3411
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-12 05:18:24 +02:00
Patrick Georgi d2e0dd5bc1 buildgcc: Re-add some break statements
While some of the case .. break statement actually weren't needed,
too are, since otherwise the option parsing loop hangs.

Exit conditions for that endless loop: "--" or no more arguments,
in line with GNU command line parsing rules.

Change-Id: I0dbc35e530fb8c93a0f7de05ac47f325555ad4a4
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/3418
Tested-by: build bot (Jenkins)
Reviewed-by: David Hubbard <david.c.hubbard+coreboot@gmail.com>
2013-06-09 08:34:45 +02:00
Olivier Langlois ccc7d1f229 Intel Atom cpu support to msrtool
Added support for Intel Atom cpu to msrtool
Fixed a cut&paste error in nehalem msr bits definition

It has been tested with a N455 cpu and msrtool output can be review at:
http://www.trillion01.com/coreboot/msrtool_atom.txt

Change-Id: I0ecf455b559185e2d16fa1a655bf021efc2ef537
Signed-off-by: Olivier Langlois <olivier@olivierlanglois.net>
Reviewed-on: http://review.coreboot.org/3351
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-06 21:02:09 +02:00
Alexandru Gagniuc 67f556c296 viatool: Add utility to read various configuration bits on VIA systems
viatool is a utility for extracting useful for extracting certain configuration
bits on VIA chipsets and CPUs. It is a fork of inteltool.

viatool is currently focused on "quirks". Quirks are device configurations that
cannot be accessed directly. They are implemented as hierarchical configurations
in the PCI or memory address spaces (index/data register pairs). Such
configurations refer to hardware parameters that are board specific. Those
parameters would otherwise be difficult to extract from a system running the
vendor's firmware.

viatool also preserves inteltool's MSR dumps. VIA CPU and Intel CPU MSRs are
nearly identical.

Change-Id: Icbd39eaf7c7da5568732d77dbf2aed135f835754
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/1430
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04 22:36:26 +02:00
Nico Huber e25984b8c8 superiotool: Add dump facility for HWM of W83627DHG-P
Change-Id: I9355996a8cf1b7cb91cc415ec04f5108a1cc42a5
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3358
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-04 21:14:55 +02:00
Nico Huber 28a1324303 superiotool: Add dump facility for ITE IT8516 + I/O 0x20e/f
Change-Id: Iaea08b7eb5aac9ff1e0756f1400a82641bb45b14
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3359
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-04 21:14:44 +02:00
David Hubbard 5b0420a87b crossgcc/buildgcc: Remove unneeded 'break' statements
Bash case statements are terminated with ';;'.

Unlike C, bash case statements will not continue to the next case. No 'break' is needed.

Change-Id: I62e7e91f3223ac4052728a1ca12a4681af0dc036
Signed-off-by: David Hubbard <david.c.hubbard+coreboot@gmail.com>
Reviewed-on: http://review.coreboot.org/3330
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-04 01:15:20 +02:00
Nico Huber 8e4bb92898 util/cbmem: Fix format string in cbmem.c
Use PRIx64 to print a u64 instead of "llx". Fixes the following error:

cbmem.c: In function 'parse_cbtable':
cbmem.c:135:2: error: format '%llx' expects argument of type 'long long unsigned int', but argument 2 has type 'u64' [-Werror=format=]

Change-Id: Ibc2bf8597cb86db5b2e71fba77ec837a08c5e3d4
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3301
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-03 22:24:41 +02:00
Vladimir Serbinenko e4e8e090fa util/inteltool: Add support for mobile 5 chipset
Dump registers on mobile 5. Successfully tested on X201.

Change-Id: I606371801d3ae6c96d3d404c9775c254bd0ffbc9
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/2993
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-05-27 02:53:49 +02:00
Ronald G. Minnich b460a66aa9 Get buildgcc to behave reasonably with the -p choice.
buildgcc has many wrong choices, and two right ones,
but you would never guess that. It's even more
frustrating when it spends lots of time building a
full tool chain and you find out it's not the one you
wanted and, still worse, you've forgotten what it does want
and, even worse, it won't f-ing tell you what the two
right choices are!.

Have it tell you when you've done something wrong, and have it
make reasonable decisions when you say things like
-p arm
instead of
-p armv7a-eabi

This change lowers my blood pressure 10 points.

Change-Id: I44a59d7cb7a6260894d8bcb692a693ed25681ff8
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/3292
Tested-by: build bot (Jenkins)
2013-05-26 18:18:52 +02:00
Roman Zippel 330bb6acc8 kconfig: fix choice dependency check
Properly check the dependency of choices as a group.
Also fix that sym_check_deps() correctly terminates the dependency loop
error check (otherwise it would continue printing the dependency chain).

Signed-off-by: Roman Zippel <zippel@linux-m68k.org>
Signed-off-by: Sam Ravnborg <sam@ravnborg.org>

=======

Cherry-picked from the Linux kernel.

Change-Id: I0c98760dd0f55cf2ff70c53e0b014288b59574c8
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3290
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-26 11:50:11 +02:00
Roel Kluin 48757668a5 kconfig: reversed borderlines in inputbox
Fix reversal of dlg.border.atr and dlg.dialog.atr for draw_box()
Makes the inputbox look like expected

Signed-off-by: Roel Kluin <12o3l@tiscali.nl>
Signed-off-by: Sam Ravnborg <sam@ravnborg.org>

=======

Cherry-picked from the Linux kernel.

Change-Id: I596915aab0204ef0e392fefa56fad8e25204e207
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3289
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-26 11:49:30 +02:00
Roman Zippel 543aa7ba7b kconfig: add named choice group
As choice dependency are now fully checked, it's quite easy to add support
for named choices. This lifts the restriction that a choice value can only
appear once, although it still has to be within the same group,
but multiple choices can be joined by giving them a name.
While at it I cleaned up a little the choice type logic to simplify it a
bit.

Signed-off-by: Roman Zippel <zippel@linux-m68k.org>
Signed-off-by: Sam Ravnborg <sam@ravnborg.org>

=======

Cherry-picked from the Linux kernel.

Change-Id: If0f00d1783907d606220cda5307b8960d3bfc38d
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3291
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-26 11:49:12 +02:00
Stefan Reinauer ec664bcfa4 romcc: support attribute((packed))
right now this is just a fake option to get rid of ifdefs in
coreboot's code.

Change-Id: I59233f3c1d266b4e716a5921e9db298c7f96751d
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/3225
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2013-05-10 19:33:00 +02:00
Ronald G. Minnich 711a6fde0d Get rid of MAXIMUM_CONSOLE_LOGLEVEL; compile all messages into the coreboot binary
This option has never had much if any use. It solved a problem over 10
years ago that resulted from an argument over the value or lack thereof
of including all the debug strings in a coreboot image. The answer is
in: it's a good idea to maintain the capability to print all messages,
for many reasons.

This option is  also misleading people, as in a recent discussion, to
believe that log messges are controlled at build time in a way they are
not. For the record, from this day forward, we can print messages at all
log levels and the default log level is set at boot time, as directed by
DEFAULT_CONSOLE_LOGLEVEL. You can set the default to 0 at build time and
if you are having trouble override it in CMOS and get more messages.

Besides, a quick glance shows it's always set to max (9 in this case) in
the very few cases (1) in which it is set.

Change-Id: I60c4cdaf4dcd318b841a6d6c70546417c5626f21
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/3188
Tested-by: build bot (Jenkins)
2013-05-10 17:33:49 +02:00
Patrick Georgi a98d3061e9 nvramtool: Use CMOS_SIZE for cmos size
We write CMOS data to 128 byte files, which is a problem
when using them later-on (eg. as part of a coreboot image)
where nvramtool assumes them to be 256 byte, and so data
corruption occurs.

Change-Id: Ibc919c95f6d522866b21fd313ceb023e73d09fb9
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/3186
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-05-04 00:14:11 +02:00
Idwer Vollering 37714f33a6 crossgcc: update to gcc 4.7.3
Update crossgcc to use gcc 4.7.3
The resulting coreboot.rom is not runtime tested (any volunteers?).

Drop the texinfo patch, rename the armv7a patch.

Some Linux distributions have moved on to gcc 4.8,
under certain circumstances this version can't (cross-)compile gcc 4.7.2
Bug report: http://gcc.gnu.org/bugzilla/show_bug.cgi?id=56927

Change-Id: Id8ce5f86c34e1a0900d44dc6ae4e81cb9548ecc2
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: http://review.coreboot.org/3112
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-03 17:26:48 +02:00
Frank Rysanek c0c620e74a superiotool: add CR dump for W83627UHG = NCT6627UD
This commit adds "register dump capability" to
superiotool for a specific chip by Winbond/Nuvoton:
the W83627UHG   AKA   NCT6627UD  (same chip, different package).
In other words, it fills in the "CR map" definitions in winbond.c,
which so far have been void for this chip.
-
superiotool r4.0-3976-g190011e
Found Winbond W83627UHG = NCT6627UD (id=0xa2, rev=0x32) at 0x2e
Register dump:
idx 02 20 21 22 23 24 25 26  27 28 29 2a 2b 2c 2d 2e  2f
val ff a2 32 ff f0 44 00 00  ff 00 00 00 00 03 00 00  ff
def 00 a2 NA ff f0 MM 00 MM  RR 00 00 00 00 02 00 00  00
LDN 0x00 (Floppy)
idx 30 60 61 70 74 f0 f1 f2  f4 f5
val 00 00 00 00 02 8e 00 ff  00 00
def 01 03 f0 06 02 8e 00 ff  00 00
LDN 0x01 (Parallel port)
idx 30 60 61 70 74 f0
val 00 03 78 0c 04 3f
def 01 03 78 07 04 3f
LDN 0x02 (UART A)
idx 30 60 61 70 f0
val 01 03 f8 04 00
def 01 03 f8 04 00
LDN 0x03 (UART B)
idx 30 60 61 70 f0 f1
val 01 02 f8 03 00 44
def 01 02 f8 03 00 00
LDN 0x05 (Keyboard)
idx 30 60 61 62 63 70 72 f0
val 01 00 60 00 64 01 0c 82
def 01 00 60 00 64 01 0c 83
LDN 0x06 (UART C)
idx 30 60 61 70 f0
val 01 03 e8 05 80
def 01 03 e0 04 00
LDN 0x07 (GPIO 3, GPIO 4)
idx 30 e0 e1 e2 e3 e4 e5 e6  e7
val 04 ff ff ff ff ff ff ff  ff
def 00 ff 00 00 00 ff 00 00  00
LDN 0x08 (WDTO#, PLED, GPIO 5,6 & GPIO Base Address)
idx 30 60 61 e0 e1 e2 e3 e4  e5 e6 e7 f5 f6 f7
val 01 00 00 ff ff ff ff ff  ff ff ff 02 00 00
def 02 00 00 ff 00 00 00 ff  1f 00 00 00 00 00
LDN 0x09 (GPIO 1, GPIO 2 and SUSLED)
idx 30 e0 e1 e2 e3 e4 e5 e6  e7 f3
val 02 ff ff ff ff 00 ff 00  00 00
def 00 ff 00 00 00 ff 00 00  00 00
LDN 0x0a (ACPI)
idx 30 70 e0 e1 e2 e3 e4 e5  e6 e7 e8 e9 f2 f3 f4 f6  f7 fe
val 01 00 01 00 0a 00 00 00  0c 00 09 00 01 00 00 00  00 00
def 00 00 01 00 ff 08 00 00  1c 00 RR RR 3e 00 00 00  00 00
LDN 0x0b (Hardware monitor)
idx 30 60 61 70 f0 f1 f2
val 01 02 48 00 81 ff 81
def 00 00 00 00 RR RR 00
LDN 0x0c (PECI, SST)
idx e0 e1 e2 e3 e4 e5 e6 e7  e8 f1 f2 f3 fe ff
val 00 48 48 48 48 00 00 00  00 4c 50 10 23 5a
def 00 48 48 48 48 00 RR RR  00 48 50 10 23 5a
LDN 0x0d (UART D)
idx 30 60 61 70 f0
val 00 00 00 00 00
def 00 02 e0 03 00
LDN 0x0e (UART E)
idx 30 60 61 70 f0
val 00 00 00 00 80
def 00 03 e8 04 00
LDN 0x0f (UART F)
idx 30 60 61 70 f0
val 01 02 38 0a 00
def 00 02 e8 03 00

Change-Id: I834f8767b29f3148f353004edb22cfd7db5ddd56
Signed-off-by: Frank Rysanek <Frantisek.Rysanek@post.cz>
Reviewed-on: http://review.coreboot.org/3027
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2013-04-22 17:07:13 +02:00
Paul Menzel 8d9ffd93b5 cbmem: map_memory: Use length modifier `j` and cast for an `off_t` argument
cbmem currently fails to build due to `-Werror` and the following
warning.

    $ make
    cc -O2 -Wall -Werror -iquote ../../src/include -iquote ../../src/src/arch/x86  -c -o cbmem.o cbmem.c
    cbmem.c: In function ‘map_memory’:
    cbmem.c:87:2: error: format ‘%zx’ expects argument of type ‘size_t’, but argument 2 has type ‘off_t’ [-Werror=format]
    […]

Casting the argument of type `off_t` to `intmax_t` and using the
length modifier `j`

    $ man 3 printf
    […]
           j      A following integer conversion corresponds to an intmax_t or uintmax_t argument.
    […]

instead of `z` as suggested in [1] and confirmed by stefanct and
segher in #coreboot on <irc.freenode.net>, gets rid of this warning
and should work an 32-bit and 64-bit systems, as an `off_t` fits
into `intmax_t`.

[1] http://www.pixelbeat.org/programming/gcc/int_types/

Change-Id: I1360abbc47aa1662e1edfbe337cf7911695c532f
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3083
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-16 17:46:28 +02:00
Paul Menzel 17c05f23e2 inteltool: pcie.c: Use `0xffULL` instead of `0xff` to avoid shift overflow
When building inteltool with Clang, it warns about the following.

    $ clang --version
    Debian clang version 3.2-1~exp6 (tags/RELEASE_32/final) (based on LLVM 3.2)
    Target: i386-pc-linux-gnu
    Thread model: posix
    $ CC=clang make
    […]
    clang -O2 -g -Wall -W   -c -o pcie.o pcie.c
    pcie.c:297:40: warning: signed shift result (0xFF0000000) requires 37 bits to represent, but 'int' only has 32 bits [-Wshift-overflow]
                    pciexbar_phys = pciexbar_reg & (0xff << 28);
                                                    ~~~~ ^  ~~
    pcie.c:301:41: warning: signed shift result (0xFF8000000) requires 37 bits to represent, but 'int' only has 32 bits [-Wshift-overflow]
                    pciexbar_phys = pciexbar_reg & (0x1ff << 27);
                                                    ~~~~~ ^  ~~
    pcie.c:305:41: warning: signed shift result (0xFFC000000) requires 37 bits to represent, but 'int' only has 32 bits [-Wshift-overflow]
                    pciexbar_phys = pciexbar_reg & (0x3ff << 26);
                                                    ~~~~~ ^  ~~
    3 warnings generated.
    […]

Specifying the length by using the suffix `0xffULL` fixes these issues
as now enough bits are available.

These issues were introduced in commit 1162f25a [1].

    commit 1162f25a49
    Author: Stefan Reinauer <stepan@coresystems.de>
    Date:   Thu Dec 4 15:18:20 2008 +0000

        Patch to util/inteltool:
        * PMBASE dumping now knows the registers.
        * Add support for i965, i975, ICH8M
        * Add support for Darwin OS using DirectIO

[1] http://review.coreboot.org/gitweb?p=coreboot.git;a=commit;h=1162f25a49e8f39822123d664cda10fef466b351

Change-Id: I7b9a15b04ef3bcae64e06266667597d0f9f07b79
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3015
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.huber@secunet.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-15 19:03:19 +02:00
Paul Menzel c3fc1e05a6 cbmem: Makefile: Allow to override `CC` variable
Now users can use a different compiler from GCC like Clang by for example
doing `CC=clang make`.

Change-Id: I664a36df79f7496a56d89bdb61948b2eda33a6b4
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3082
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-15 07:00:23 +02:00
Paul Menzel 15a1fd1db9 inteltool: Use portable type `uint64_t` instead of `u64`
In [1] Idwer Vollering noted, that the type `u64` is not portable so
on his FreeBSD system, the following warning is shown.

    $ clang -O2 -Wall -W -I/usr/local/include   -c -o amb.o amb.c
    amb.c:441:22: error: use of undeclared identifier 'u64'
                    ambconfig_phys = ((u64)pci_read_long(dev16, 0x4c) << 32) |

The type `uint64_t` seems to be defined also on FreeBSD, so using this
fixes the warning.

Note, this warning is not reproducable with Debian Sid/unstable for
example. I have no idea why though.

[1] http://review.coreboot.org/#/c/3015/

Change-Id: Ic22f4371114b68ae8221d84a01fef6888d43f365
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3086
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-14 23:00:35 +02:00
Paul Menzel cb891de07f cbmem: parse_cbtable: Use length modifier `ll` `u64` argument
Currently on a 32-bit system cbmem fails to build due to `-Werror`
and the following warning.

    $ make
    cc -O2 -Wall -Werror -iquote ../../src/include -iquote ../../src/src/arch/x86  -c -o cbmem.o cbmem.c
    […]
    cbmem.c: In function ‘parse_cbtable’:
    cbmem.c:135:2: error: format ‘%lx’ expects argument of type ‘long unsigned int’, but argument 2 has type ‘u64’ [-Werror=format]
    cc1: all warnings being treated as errors
    […]

Using the length modifier `ll` instead of `l` gets rid of this
warning.

Change-Id: Ib2656e27594c7aaa687aa84bf07042933f840e46
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3084
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-14 02:06:21 +02:00
Paul Menzel 2c8f81b57b cbfstool: cbfs-mkstage.c: Free `buffer` on error path
Cppcheck warns about a memory leak, present since adding romtool,
which was renamed to cbfstool, in commit 5d01ec0f.

    $ cppcheck --version
    Cppcheck 1.59
    […]
    [cbfs-mkstage.c:170]: (error) Memory leak: buffer
    […]

Indeed the memory pointed to by `buffer` is not freed on the error path,
so add `free(buffer)` to fix this.

Change-Id: I6cbf82479027747c800c5fe847f20b779e261ef4
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3069
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-04-12 20:22:39 +02:00
Idwer Vollering e76d8d7ced acpica: update URL
The URL to acpica-unix-20121114 has changed, update the URL.

Change-Id: I1c8c228094f19455af3682f36f1990586fe3934c
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: http://review.coreboot.org/3070
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-04-12 20:15:51 +02:00
Vladimir Serbinenko f4a0d019fa util/cbmem: Don't output trailing garbage for cbmemc
Current code outputs the whole cbmemc buffer even if only part of
it is really used. Fix it to output only the used part and notify
the user if the buffer was too small for the required data.

Change-Id: I68c1970cf84d49b2d7d6007dae0679d7a7a0cb99
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/2991
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-09 23:52:36 +02:00
Stefan Reinauer 33e83caff5 cbfstool: completely initialize input and output streams
The LZMA glue code in cbfstool was recently rewritten from C++
to plain C code in:

        commit aa3f7ba36e
        Author: Stefan Reinauer <reinauer@chromium.org>
        Date:   Thu Mar 28 16:51:45 2013 -0700

            cbfstool: Replace C++ code with C code

            Reviewed-on: http://review.coreboot.org/3010

In the progress of doing so, the stream position for the
input stream and output stream was not reset properly. This
would cause LZMA producing corrupt data when running the
compression function multiple times.

Change-Id: I096e08f263aaa1931517885be4610bbd1de8331e
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/3040
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-08 21:36:37 +02:00
Stefan Tauner 0c8b7d1ac2 inteltool: remove unused file descriptor variable and ifdefs
Change-Id: I6a119b1f362f481914377e8d14c713159f895130
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: http://review.coreboot.org/3030
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-08 18:17:59 +02:00
Stefan Tauner 0dc775e894 inteltool: use inttypes for prints in memory.c
This fixes at least one warning on my machine where "llx" is replaced by PRIx64.

Change-Id: Iee3e5027d327d4d5f8e6d8b2d53d051f74bfc354
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: http://review.coreboot.org/3024
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-04-05 20:21:35 +02:00
Paul Menzel 5f3754e66d inteltool: cpu.c: Use conversion specifier `u` for unsigned integers
Cppcheck [1], a static code analysis tool, warns about the
following.

    $ cppcheck --version
    Cppcheck 1.59
    $ cppcheck --enable=all .
    […]
    Checking cpu.c...
    [cpu.c:951]: (warning) %d in format string (no. 1) requires a signed integer given in the argument list.
    [cpu.c:962]: (warning) %d in format string (no. 1) requires a signed integer given in the argument list.
    […]

And indeed, `core` is an unsigned integer and `man 3 printf` tells
the following about conversion specifiers.

       d, i   The int argument is converted to signed decimal notation. […]

       o, u, x, X
              The unsigned int argument is converted to unsigned octal (o), unsigned decimal (u), or  unsigned  hexadecimal  (x  and  X)
              notation.

So use `u` and Cppcheck does not complain anymore.

[1] http://cppcheck.sourceforge.net/

Change-Id: If8dd8d0efe75fcb4af2502ae5100e3f2062649e4
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3026
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-04-05 20:17:03 +02:00
Paul Menzel 72ef8881a3 libpayload, superiotool: README: Prepend `coreboot/` to path of change directory line
Nico Huber spotted [1], that commit (4d6ab4e2) [1] updating
superiotools’s `README` with the Git command line

    superiotool: Update README with Git repository URL and directory location

missed, that after `git clone` one sitll has to change into
the cloned directory.

So prepend the path with `coreboot/` to fix that. The same error
happened in the commit (e1ea5151) for libpayload [2]

    libpayload: Update README with Git repository URL and directory location

and is fixed in this patch too.

[1] http://review.coreboot.org/#/c/3019/
[2] http://review.coreboot.org/2228

Change-Id: Ib6e8b678af6276556a40ccfd52ae35ca7e674455
Reported-by: Nico Huber <nico.h@gmx.de>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3021
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.huber@secunet.com>
2013-04-04 17:22:15 +02:00
Paul Menzel 3402a7fa70 inteltool: Cast to `intptr_t` instead of `uint64_t`
When building inteltool under x86-32, the following warnings are
shown.

    $ gcc --version
    gcc-4.7.real (Debian 4.7.2-15) 4.7.2
    Copyright (C) 2012 Free Software Foundation, Inc.
    This is free software; see the source for copying conditions.  There is NO
    warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
    $ make
    […]
    amb.c: In function ‘amb_read_config32’:
    amb.c:31:23: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
    amb.c:31:10: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
    amb.c: In function ‘amb_read_config16’:
    amb.c:45:23: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
    amb.c:45:10: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
    amb.c: In function ‘amb_read_config8’:
    amb.c:60:22: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
    amb.c:60:10: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
    […]

Nico Huber commented the following [1].

    I don't see those warnings because I build for x86-64. I guess
    they could be fixed by casting to `ptrdiff_t` (from stddef.h)
    instead of `uint64_t`.

And indeed, using `ptrdiff_t` fixes the warning. But as Stefan
Reinauer commented in [2], `intptr_t` is more appropriate as this
is just a pointer and no pointer difference.

So `intptr_t` is taken, which fixes these issues warned about too.

These warnings were introduced in commit »inteltool: Add support for
dumping AMB registers« (4b7b320f) [3].

[1] http://review.coreboot.org/#/c/2996/1//COMMIT_MSG
[2] http://review.coreboot.org/#/c/3002/1/util/inteltool/amb.c
[3] http://review.coreboot.org/525

Change-Id: I2ea1a31dc1e3db129e767d6a9e0433fd75a77d0f
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3002
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.huber@secunet.com>
2013-04-04 14:24:25 +02:00
Paul Menzel 4d6ab4e2ae superiotool: Update README with Git repository URL and directory location
Change-Id: I36d980cea5ca9cc67262dba809441091757e1fb5
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3019
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-04-04 04:50:00 +02:00
Paul Menzel a8db717d4a inteltool: Use `ll` instead of `l` as the length modifier for `uint64_t`
When buidling inteltool with GCC, the following warning is printed.

    $ make
    […]
    gcc -O2 -g -Wall -W   -c -o memory.o memory.c
    memory.c: In function ‘print_mchbar’:
    memory.c:287:7: warning: format ‘%lx’ expects argument of type ‘long unsigned int’, but argument 3 has type ‘uint64_t’ [-Wformat]
    […]

This was introduced in commit »inteltool: Add support for H65 Express
chipset« (c7fc4422) [1].

Address this warning, by using `%llx` instead of `%lx`.

[1] http://review.coreboot.org/1258

Change-Id: I4f714edce7e8b405e1a7a417d02fa498322c88a8
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2994
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
Tested-by: build bot (Jenkins)
2013-04-03 11:13:29 +02:00
Stefan Reinauer aa3f7ba36e cbfstool: Replace C++ code with C code
cbfstool was using a C++ wrapper around the C written LZMA functions.
And a C wrapper around those C++ functions. Drop the mess and rewrite
the functions to be all C.

Change-Id: Ieb6645a42f19efcc857be323ed8bdfcd9f48ee7c
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/3010
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-03 02:35:28 +02:00
Stefan Reinauer 60a4a73fcd cbfstool: fix --machine
The help text says --machine, but the code
actually checked for --arch. Fix it!

Change-Id: Ib9bbf758b82ef070550348e897419513495f154b
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/3009
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-02 20:27:10 +02:00
Paul Menzel 9ebd8ea7cf inteltool: Allow to override Makefile variables
Allow to override the variables `CC`, `INSTALL`, `PREFIX`,
`CFLAGS` and `LDFLAGS`. Though append `-lpci -lz` to `LDFLAGS`.

This way for example a different compiler can easily be used.

    CC=clang make

As a side note, Clang in contrast to GCC does *not* issue the
following warnings.

    $ clang --version
    Debian clang version 3.2-1~exp6 (tags/RELEASE_32/final) (based on LLVM 3.2)
    Target: i386-pc-linux-gnu
    Thread model: posix
    $ gcc --version
    gcc-4.7.real (Debian 4.7.2-15) 4.7.2
    Copyright (C) 2012 Free Software Foundation, Inc.
    This is free software; see the source for copying conditions.  There is NO
    warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
    $ make
    […]
    amb.c: In function ‘amb_read_config32’:
    amb.c:31:23: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
    amb.c:31:10: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
    amb.c: In function ‘amb_read_config16’:
    amb.c:45:23: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
    amb.c:45:10: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
    amb.c: In function ‘amb_read_config8’:
    amb.c:60:22: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
    amb.c:60:10: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
    […]

These are only shown under 32-bit and not 64-bit

    $ uname -m
    i686

and are going to be fixed in a separate patch.

Change-Id: Id75dea081ecb35390f283520a7e5dce520f4c98d
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2996
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-04-01 22:40:45 +02:00
Nico Huber 42c5501c39 inteltool: Add Cougar/Panther Point GPIO defaults
This adds default values for the GPIO setup on Intel's Cougar Point and
Panther Point platform controller hubs (PCH). Values are taken from [1] and
[2], respectively. I've tested this with an H77 PCH. See below for the
output.

[1] Intel 6 Series Chipset and Intel C200 Series Chipset - Datasheet
    Document-Number: 324645-006

[2] Intel 7 Series / C216 Chipset Family Platform Controller Hub (PCH) -
    Datasheet
    Document-Number: 326776-003

$ ./inteltool -G
CPU: Processor Type: 0, Family 6, Model 3a, Stepping 9
Northbridge: 8086:0150 (unknown)
Southbridge: 8086:1e4a (H77)

========== GPIO DIFFS ===========

GPIOBASE = 0x0500 (IO)

gpiobase+0x0000: 0xb96ba1fb (GPIO_USE_SEL)
gpiobase+0x0000: 0xb96ba1ff (GPIO_USE_SEL) DEFAULT
gpiobase+0x0000: 0x00000004 (GPIO_USE_SEL) DIFF

gpiobase+0x0004: 0x06ff6efb (GP_IO_SEL)
gpiobase+0x0004: 0xeeff6eff (GP_IO_SEL) DEFAULT
gpiobase+0x0004: 0xe8000004 (GP_IO_SEL) DIFF

gpiobase+0x000c: 0xe1f17f7e (GP_LVL)
gpiobase+0x000c: 0x02fe0100 (GP_LVL) DEFAULT
gpiobase+0x000c: 0xe30f7e7e (GP_LVL) DIFF

gpiobase+0x002c: 0x00002000 (GPI_INV)
gpiobase+0x002c: 0x00000000 (GPI_INV) DEFAULT
gpiobase+0x002c: 0x00002000 (GPI_INV) DIFF

gpiobase+0x0030: 0x0aff70ff (GPIO_USE_SEL2)
gpiobase+0x0030: 0x020300ff (GPIO_USE_SEL2) DEFAULT
gpiobase+0x0030: 0x08fc7000 (GPIO_USE_SEL2) DIFF

gpiobase+0x0034: 0x15038ff2 (GP_IO_SEL2)
gpiobase+0x0034: 0x1f57fff4 (GP_IO_SEL2) DEFAULT
gpiobase+0x0034: 0x0a547006 (GP_IO_SEL2) DIFF

gpiobase+0x0038: 0xb65e7f4f (GP_LVL2)
gpiobase+0x0038: 0xa4aa0007 (GP_LVL2) DEFAULT
gpiobase+0x0038: 0x12f47f48 (GP_LVL2) DIFF

gpiobase+0x0040: 0x000001f3 (GPIO_USE_SEL3)
gpiobase+0x0040: 0x00000130 (GPIO_USE_SEL3) DEFAULT
gpiobase+0x0040: 0x000000c3 (GPIO_USE_SEL3) DIFF

gpiobase+0x0044: 0x00000ef3 (GPIO_SEL3)
gpiobase+0x0044: 0x00000ff0 (GPIO_SEL3) DEFAULT
gpiobase+0x0044: 0x00000103 (GPIO_SEL3) DIFF

gpiobase+0x0048: 0x00000dfc (GPIO_LVL3)
gpiobase+0x0048: 0x000000c0 (GPIO_LVL3) DEFAULT
gpiobase+0x0048: 0x00000d3c (GPIO_LVL3) DIFF

gpiobase+0x0060: 0x00000000 (GP_RST_SEL1)
gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DEFAULT
gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DIFF

$ ./inteltool -gG
CPU: Processor Type: 0, Family 6, Model 3a, Stepping 9
Northbridge: 8086:0150 (unknown)
Southbridge: 8086:1e4a (H77)

============= GPIOS =============

GPIOBASE = 0x0500 (IO)

gpiobase+0x0000: 0xb96ba1fb (GPIO_USE_SEL)
gpiobase+0x0000: 0xb96ba1ff (GPIO_USE_SEL) DEFAULT
gpiobase+0x0000: 0x00000004 (GPIO_USE_SEL) DIFF
gpiobase+0x0004: 0x06ff6efb (GP_IO_SEL)
gpiobase+0x0004: 0xeeff6eff (GP_IO_SEL) DEFAULT
gpiobase+0x0004: 0xe8000004 (GP_IO_SEL) DIFF
gpiobase+0x0008: 0x00000000 (RESERVED)
gpiobase+0x000c: 0xe1f17f7e (GP_LVL)
gpiobase+0x000c: 0x02fe0100 (GP_LVL) DEFAULT
gpiobase+0x000c: 0xe30f7e7e (GP_LVL) DIFF
gpiobase+0x0010: 0x00000000 (RESERVED)
gpiobase+0x0014: 0x00000000 (RESERVED)
gpiobase+0x0018: 0x00040000 (GPO_BLINK)
gpiobase+0x001c: 0x00000000 (GP_SER_BLINK)
gpiobase+0x0020: 0x00080000 (GP_SB_CMDSTS)
gpiobase+0x0024: 0x00000000 (GP_SB_DATA)
gpiobase+0x0028: 0x0000     (GPI_NMI_EN)
gpiobase+0x002a: 0x0000     (GPI_NMI_STS)
gpiobase+0x002c: 0x00002000 (GPI_INV)
gpiobase+0x002c: 0x00000000 (GPI_INV) DEFAULT
gpiobase+0x002c: 0x00002000 (GPI_INV) DIFF
gpiobase+0x0030: 0x0aff70ff (GPIO_USE_SEL2)
gpiobase+0x0030: 0x020300ff (GPIO_USE_SEL2) DEFAULT
gpiobase+0x0030: 0x08fc7000 (GPIO_USE_SEL2) DIFF
gpiobase+0x0034: 0x15038ff2 (GP_IO_SEL2)
gpiobase+0x0034: 0x1f57fff4 (GP_IO_SEL2) DEFAULT
gpiobase+0x0034: 0x0a547006 (GP_IO_SEL2) DIFF
gpiobase+0x0038: 0xb65e7f4f (GP_LVL2)
gpiobase+0x0038: 0xa4aa0007 (GP_LVL2) DEFAULT
gpiobase+0x0038: 0x12f47f48 (GP_LVL2) DIFF
gpiobase+0x003c: 0x00000000 (RESERVED)
gpiobase+0x0040: 0x000001f3 (GPIO_USE_SEL3)
gpiobase+0x0040: 0x00000130 (GPIO_USE_SEL3) DEFAULT
gpiobase+0x0040: 0x000000c3 (GPIO_USE_SEL3) DIFF
gpiobase+0x0044: 0x00000ef3 (GPIO_SEL3)
gpiobase+0x0044: 0x00000ff0 (GPIO_SEL3) DEFAULT
gpiobase+0x0044: 0x00000103 (GPIO_SEL3) DIFF
gpiobase+0x0048: 0x00000dfc (GPIO_LVL3)
gpiobase+0x0048: 0x000000c0 (GPIO_LVL3) DEFAULT
gpiobase+0x0048: 0x00000d3c (GPIO_LVL3) DIFF
gpiobase+0x004c: 0x00000000 (RESERVED)
gpiobase+0x0050: 0x00000000 (RESERVED)
gpiobase+0x0054: 0x00000000 (RESERVED)
gpiobase+0x0058: 0x00000000 (RESERVED)
gpiobase+0x005c: 0x00000000 (RESERVED)
gpiobase+0x0060: 0x00000000 (GP_RST_SEL1)
gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DEFAULT
gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DIFF
gpiobase+0x0064: 0x00000000 (GP_RST_SEL2)
gpiobase+0x0068: 0x00000000 (GP_RST_SEL3)
gpiobase+0x006c: 0x00000000 (RESERVED)
gpiobase+0x0070: 0x00000000 (RESERVED)
gpiobase+0x0074: 0x00000000 (RESERVED)
gpiobase+0x0078: 0x00000000 (RESERVED)
gpiobase+0x007c: 0x00000000 (RESERVED)

Change-Id: If99cf8d5c93e34ad28f52080fff64e01c220eb27
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: http://review.coreboot.org/3001
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-04-01 22:39:30 +02:00
Nico Huber 09dcbf0cdb inteltool: Add option to show differences in GPIO setup
This adds an option -G, --gpio-diffs to inteltool, which shows GPIO settings
that differ from platform defaults. For differing registers, the current,
the default, and an xor of the default and the current value is printed. A
follow-up commit will add defaults for the Cougar/Panther Point platform
controller hubs. If you specify both, -g and -G on the command line, all
GPIO registers will be printed interleaved with the diff.

Here's a preview:

$ ./inteltool -G
CPU: Processor Type: 0, Family 6, Model 3a, Stepping 9
Northbridge: 8086:0150 (unknown)
Southbridge: 8086:1e4a (H77)

========== GPIO DIFFS ===========

GPIOBASE = 0x0500 (IO)

gpiobase+0x0000: 0xb96ba1fb (GPIO_USE_SEL)
gpiobase+0x0000: 0xb96ba1ff (GPIO_USE_SEL) DEFAULT
gpiobase+0x0000: 0x00000004 (GPIO_USE_SEL) DIFF

gpiobase+0x0004: 0x06ff6efb (GP_IO_SEL)
gpiobase+0x0004: 0xeeff6eff (GP_IO_SEL) DEFAULT
gpiobase+0x0004: 0xe8000004 (GP_IO_SEL) DIFF

gpiobase+0x000c: 0xe1f17f7e (GP_LVL)
gpiobase+0x000c: 0x02fe0100 (GP_LVL) DEFAULT
gpiobase+0x000c: 0xe30f7e7e (GP_LVL) DIFF

gpiobase+0x002c: 0x00002000 (GPI_INV)
gpiobase+0x002c: 0x00000000 (GPI_INV) DEFAULT
gpiobase+0x002c: 0x00002000 (GPI_INV) DIFF

gpiobase+0x0030: 0x0aff70ff (GPIO_USE_SEL2)
gpiobase+0x0030: 0x020300ff (GPIO_USE_SEL2) DEFAULT
gpiobase+0x0030: 0x08fc7000 (GPIO_USE_SEL2) DIFF

gpiobase+0x0034: 0x15038ff2 (GP_IO_SEL2)
gpiobase+0x0034: 0x1f57fff4 (GP_IO_SEL2) DEFAULT
gpiobase+0x0034: 0x0a547006 (GP_IO_SEL2) DIFF

gpiobase+0x0038: 0xb65e7f4f (GP_LVL2)
gpiobase+0x0038: 0xa4aa0007 (GP_LVL2) DEFAULT
gpiobase+0x0038: 0x12f47f48 (GP_LVL2) DIFF

gpiobase+0x0040: 0x000001f3 (GPIO_USE_SEL3)
gpiobase+0x0040: 0x00000130 (GPIO_USE_SEL3) DEFAULT
gpiobase+0x0040: 0x000000c3 (GPIO_USE_SEL3) DIFF

gpiobase+0x0044: 0x00000ef3 (GPIO_SEL3)
gpiobase+0x0044: 0x00000ff0 (GPIO_SEL3) DEFAULT
gpiobase+0x0044: 0x00000103 (GPIO_SEL3) DIFF

gpiobase+0x0048: 0x00000dfc (GPIO_LVL3)
gpiobase+0x0048: 0x000000c0 (GPIO_LVL3) DEFAULT
gpiobase+0x0048: 0x00000d3c (GPIO_LVL3) DIFF

gpiobase+0x0060: 0x00000000 (GP_RST_SEL1)
gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DEFAULT
gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DIFF

$ ./inteltool -gG
CPU: Processor Type: 0, Family 6, Model 3a, Stepping 9
Northbridge: 8086:0150 (unknown)
Southbridge: 8086:1e4a (H77)

============= GPIOS =============

GPIOBASE = 0x0500 (IO)

gpiobase+0x0000: 0xb96ba1fb (GPIO_USE_SEL)
gpiobase+0x0000: 0xb96ba1ff (GPIO_USE_SEL) DEFAULT
gpiobase+0x0000: 0x00000004 (GPIO_USE_SEL) DIFF
gpiobase+0x0004: 0x06ff6efb (GP_IO_SEL)
gpiobase+0x0004: 0xeeff6eff (GP_IO_SEL) DEFAULT
gpiobase+0x0004: 0xe8000004 (GP_IO_SEL) DIFF
gpiobase+0x0008: 0x00000000 (RESERVED)
gpiobase+0x000c: 0xe1f17f7e (GP_LVL)
gpiobase+0x000c: 0x02fe0100 (GP_LVL) DEFAULT
gpiobase+0x000c: 0xe30f7e7e (GP_LVL) DIFF
gpiobase+0x0010: 0x00000000 (RESERVED)
gpiobase+0x0014: 0x00000000 (RESERVED)
gpiobase+0x0018: 0x00040000 (GPO_BLINK)
gpiobase+0x001c: 0x00000000 (GP_SER_BLINK)
gpiobase+0x0020: 0x00080000 (GP_SB_CMDSTS)
gpiobase+0x0024: 0x00000000 (GP_SB_DATA)
gpiobase+0x0028: 0x0000     (GPI_NMI_EN)
gpiobase+0x002a: 0x0000     (GPI_NMI_STS)
gpiobase+0x002c: 0x00002000 (GPI_INV)
gpiobase+0x002c: 0x00000000 (GPI_INV) DEFAULT
gpiobase+0x002c: 0x00002000 (GPI_INV) DIFF
gpiobase+0x0030: 0x0aff70ff (GPIO_USE_SEL2)
gpiobase+0x0030: 0x020300ff (GPIO_USE_SEL2) DEFAULT
gpiobase+0x0030: 0x08fc7000 (GPIO_USE_SEL2) DIFF
gpiobase+0x0034: 0x15038ff2 (GP_IO_SEL2)
gpiobase+0x0034: 0x1f57fff4 (GP_IO_SEL2) DEFAULT
gpiobase+0x0034: 0x0a547006 (GP_IO_SEL2) DIFF
gpiobase+0x0038: 0xb65e7f4f (GP_LVL2)
gpiobase+0x0038: 0xa4aa0007 (GP_LVL2) DEFAULT
gpiobase+0x0038: 0x12f47f48 (GP_LVL2) DIFF
gpiobase+0x003c: 0x00000000 (RESERVED)
gpiobase+0x0040: 0x000001f3 (GPIO_USE_SEL3)
gpiobase+0x0040: 0x00000130 (GPIO_USE_SEL3) DEFAULT
gpiobase+0x0040: 0x000000c3 (GPIO_USE_SEL3) DIFF
gpiobase+0x0044: 0x00000ef3 (GPIO_SEL3)
gpiobase+0x0044: 0x00000ff0 (GPIO_SEL3) DEFAULT
gpiobase+0x0044: 0x00000103 (GPIO_SEL3) DIFF
gpiobase+0x0048: 0x00000dfc (GPIO_LVL3)
gpiobase+0x0048: 0x000000c0 (GPIO_LVL3) DEFAULT
gpiobase+0x0048: 0x00000d3c (GPIO_LVL3) DIFF
gpiobase+0x004c: 0x00000000 (RESERVED)
gpiobase+0x0050: 0x00000000 (RESERVED)
gpiobase+0x0054: 0x00000000 (RESERVED)
gpiobase+0x0058: 0x00000000 (RESERVED)
gpiobase+0x005c: 0x00000000 (RESERVED)
gpiobase+0x0060: 0x00000000 (GP_RST_SEL1)
gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DEFAULT
gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DIFF
gpiobase+0x0064: 0x00000000 (GP_RST_SEL2)
gpiobase+0x0068: 0x00000000 (GP_RST_SEL3)
gpiobase+0x006c: 0x00000000 (RESERVED)
gpiobase+0x0070: 0x00000000 (RESERVED)
gpiobase+0x0074: 0x00000000 (RESERVED)
gpiobase+0x0078: 0x00000000 (RESERVED)
gpiobase+0x007c: 0x00000000 (RESERVED)

Change-Id: Ic77474c4bc0871e95103ddecd9f6a9406c8f016d
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: http://review.coreboot.org/3000
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-04-01 22:39:04 +02:00
Nico Huber 5ed986b8ab inteltool: Support PM registers on Cougar/Panther Point
This adds the power management register definitions for Intel's Cougar
Point and Panther Point platform controller hubs (PCH). The definitions
are actually a subset of the older ICH10R registers: I've added just
those that are mentioned in the public specifications in [1] and [2].
I've tested dumping with an H77 PCH.

NM70 is missing in [1]. Therefore, I didn't add it here.

[1] Intel 6 Series Chipset and Intel C200 Series Chipset - Datasheet
    Document-Number: 324645-006

[2] Intel 7 Series / C216 Chipset Family Platform Controller Hub (PCH) -
    Datasheet
    Document-Number: 326776-003

Change-Id: Ia6945fe96cd96b568ed5191e91dbba5556e1ee95
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: http://review.coreboot.org/2985
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-04-01 21:00:16 +02:00
Nico Huber 14290b3cbb inteltool: Add Cougar/Panther Point IDs to rootcmplx.c
This adds the PCI IDs of Intel's Cougar Point and Panther Point platform
controller hubs (PCH) to the dumping of the root complex configuration
under the root complex base address (RCBA). Those PCHs are handled exactly
as the older ICHs which can be seen in [1] and [2]. I've tested dumping
with an H77 PCH.

NM70 is missing in [1]. Therefore, I didn't add it here.

[1] Intel 6 Series Chipset and Intel C200 Series Chipset - Datasheet
    Document-Number: 324645-006

[2] Intel 7 Series / C216 Chipset Family Platform Controller Hub (PCH) -
    Datasheet
    Document-Number: 326776-003

Change-Id: I2296caae57e614171300362d41715deecec77762
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: http://review.coreboot.org/2986
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-03-30 18:17:08 +01:00
Paul Menzel be2c6340b3 superiotool: Allow to override Makefile variables `CC`, `INSTALL` and `PREFIX`
This way for example a different compiler can easily be used.

    CC=clang make

Change-Id: I50b83554fd4826d00d87e60a30eb1f6a88834397
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2935
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-29 21:32:48 +01:00
Nico Huber 6983a6829a inteltool: Support GPIO registers on Cougar/Panther Point
This adds the GPIO register definitions for Intel's Cougar Point and
Panther Point platform controller hubs (PCH). All information is taken
from the public specifications in [1] and [2]. I've tested it with an
H77 PCH.

NM70 is missing in [1]. Therefore, I didn't add it here.

[1] Intel 6 Series Chipset and Intel C200 Series Chipset - Datasheet
    Document-Number: 324645-006

[2] Intel 7 Series / C216 Chipset Family Platform Controller Hub (PCH) -
    Datasheet
    Document-Number: 326776-003

Change-Id: I31711e24f852e68b3c113e3bd9243dc7e89ac197
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: http://review.coreboot.org/2961
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-29 21:07:55 +01:00
Nico Huber 76d60494ef inteltool: Add definitions for Cougar/Panther Point PCI IDs
This adds correspondings #defines for the PCI IDs of the LPC device on
Intel's Cougar Point and Panther Point platform controller hubs. Those
will be used more in later commits.

I've checked all those IDs against the specification updates [1] and [2].

[1] Intel 6 Series Chipset and Intel C200 Series Chipset Specification
    Update
    Document-Number: 324646-019

[2] Intel 7 Series / C216 Chipset Family Platform Controller Hub (PCH)
    Family - Datasheet Specification Update
    Document-Number: 326777-010

Change-Id: Ibef5a30d283c568c345eb8d8149723e7a3049272
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: http://review.coreboot.org/2960
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-29 21:07:30 +01:00
Nico Huber 69a21b1eb9 crossgcc: Fix building with texinfo-5.x
If you have a recent version of texinfo installed, building the reference
toolchain fails with the following error:
(in util/crossgcc/build-gcc/crossgcc-build.log)

[...]/gcc-4.7.2/gcc/doc/cppopts.texi:806: @itemx must follow @item

Looks like a warning-became-an-error problem in texinfo, to me. Fix that by
making every erroneous @itemx an @item.

Change-Id: I685ae1ecfee889b7c857b148cfab7411a10e7ecd
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: http://review.coreboot.org/2939
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2013-03-28 21:14:50 +01:00
Aaron Durbin 6b0d0d6e14 cbfstool: Add update-fit command
Add support for filling in the Firmware Interface Table.
For now it only supports adding microcode entries.

It takes 2 options:
1. Name of file in cbfs where the mircocode is located
2. The number of empty entries in the table.

Verified with go firmware tools. Also commented out updating
microcode in the bootblock. When romstage runs, the CPUs indicate
their microcode is already loaded.

Change-Id: Iaccaa9c226ee24868a5f4c0ba79729015d15bbef
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2712
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
2013-03-27 01:25:12 +01:00
Stefan Reinauer dc7bc8e589 cbfstool: Fix cbfs_image.c
- The read-only structures are const now
- cosmetic fixes
  - put { on a new line for functions
  - move code after structures

Change-Id: Ib9131b80242b91bd5105feaebdf8306a844da1cc
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2922
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
2013-03-27 01:24:48 +01:00
Aaron Durbin 73982c3c68 xcompile: honor LINKER_SUFFIX variable
In commit e820e5cb3a titled
"Make xcompile support multiple architectures" the LINKER_SUFFIX
variable was introduced to bypass gold if the bfd linker was
available. However, the LINKER_SUFFIX wasn't honored when
the compiler evironment variables were set. Fix the original
intention.

Change-Id: I608f1e0cc3d0bea3ba1e51b167d88c66d266bceb
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2879
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-23 19:32:44 +01:00
Hung-Te Lin b02c873190 cbfstool: Fix initial empty space in image creation.
When calculating initial CBFS empty entry space, the size of header itself must
be not included (with the reserved space for entry name). This is a regression
of the old cbfstool size bug.

Before this fix, in build process we see:
 OBJCOPY    cbfs/fallback/romstage_null.bin
 W: CBFS image was created with old cbfstool with size bug.
    Fixing size in last entry...

And checking the output binary:
 cbfstool build/coreboot.pre1 print -v -v
 DEBUG: read_cbfs_image: build/coreboot.pre1 (262144 bytes)
 DEBUG: x86sig: 0xfffffd30, offset: 0x3fd30
 W: CBFS image was created with old cbfstool with size bug.
    Fixing size in last entry...
 DEBUG: Last entry has been changed from 0x3fd40 to 0x3fd00.
 coreboot.pre1: 256 kB, bootblksz 688, romsize 262144, offset 0x0 align: 64
 Name                           Offset     Type         Size
 (empty)                        0x0        null         261296
 DEBUG:  cbfs_file=0x0, offset=0x28, content_address=0x28+0x3fcb0

After this fix, no more alerts in build process.
Verified to build successfully on x86/qemu and arm/snow configurations.

Change-Id: I35c96f4c10a41bae671148a0e08988fa3bf6b7d3
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2731
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-22 00:21:41 +01:00
Hung-Te Lin e4ea2ca18d cbfstool locate: Implement alignment switch --align/-a
cbfstool usage change:
 "-a" for "cbfstool locate" can specify base address alignment.

To support putting a blob in aligned location (ex, microcode needs to be aligned
in 0x10), alignment (-a) is implemented into "locate" command.

Verified by manually testing a file (324 bytes) with alignment=0x10:
 cbfstool coreboot.rom locate -f test -n test -a 0x10
 # output: 0x71fdd0
 cbfstool coreboot.rom add -f test -n test -t raw -b 0x71fdd0
 cbfstool coreboot.rom print -v -v
 # output: test                           0x71fd80   raw          324
 # output:  cbfs_file=0x71fd80, offset=0x50, content_address=0x71fdd0+0x144

Also verified to be compatible with old behavior by building i386/axus/tc320
(with page limitation 0x40000):
 cbfstool coreboot.rom locate -f romstage_null.bin -n romstage -P 0x40000
 # output: 0x44
 cbfstool coreboot.rom locate -f x.bin -n romstage -P 0x40000 -a 0x30
 # output: 0x60

Change-Id: I78b549fe6097ce5cb6162b09f064853827069637
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2824
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
2013-03-20 05:47:32 +01:00
Hung-Te Lin e91983767c cbfstool locate: Rename -a align switch to -P for page size
cbfstool usage change:
   The "-a" parameter for "cbfstool locate" is switched to "-P/--page-size".

The "locate" command was used to find a place to store ELF stage image in one
memory page. Its argument "-a (alignment)" was actually specifying the page size
instead of doing memory address alignment. This can be confusing when people are
trying to put a blob in aligned location (ex, microcode needs to be aligned in
0x10), and see this:
  cbfstool coreboot.rom locate -f test.bin -n test -a 0x40000
  # output: 0x44, which does not look like aligned to 0x40000.

To prevent confusion, it's now switched to "-P/--page-size".

Verified by building i386/axus/tc320 (with page limitation 0x40000):
 cbfstool coreboot.rom locate -f romstage_null.bin -n romstage -P 0x40000
 # output: 0x44

Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Change-Id: I0893adde51ebf46da1c34913f9c35507ed8ff731
Reviewed-on: http://review.coreboot.org/2730
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
2013-03-19 11:12:10 +01:00
Андрей Павлов ab9b71d54c superiotool: Add support for the IT8728F Super I/O
$ superiotool -d
superiotool r4.0-3712-gd549279
Found ITE IT8728F (id=0x8728, rev=0x1) at 0x2e
Register dump:
idx 02 07 20 21 22 23 24 2b  2e 2f
val 00 0a 87 28 01 00 00 40  00 00
def NA NA 87 28 01 00 00 MM  00 00
LDN 0x00 (Floppy)
idx 30 60 61 70 74 f0 f1
val 00 03 f0 06 02 00 00
def 00 03 f0 06 02 00 00
LDN 0x01 (COM1)
idx 30 60 61 70 f0 f1
val 01 03 f8 04 00 50
def 00 03 f8 04 00 50
LDN 0x02 (COM2)
idx 30 60 61 70 f0 f1
val 00 02 f8 03 00 50
def 00 02 f8 03 00 50
LDN 0x03 (Parallel port)
idx 30 60 61 62 63 70 74 f0
val 01 03 78 00 00 07 04 08
def 00 03 78 07 78 07 03 03
LDN 0x04 (Environment controller)
idx 30 60 61 62 63 70 f0 f1  f2 f3 f4 f5 f6 f9 fa fb
val 01 0a 30 0a 20 09 00 80  00 00 20 00 f0 48 00 00
def 00 02 90 02 30 09 00 00  00 00 00 MM MM MM MM MM
LDN 0x05 (Keyboard)
idx 30 60 61 62 63 70 71 f0
val 01 00 60 00 64 01 02 08
def 01 00 60 00 64 01 02 48
LDN 0x06 (Mouse)
idx 30 70 71 f0
val 01 0c 02 00
def 00 0c 02 00
LDN 0x07 (GPIO)
idx 25 26 27 28 29 2a 2c 2d  60 61 62 63 64 65 70 71  72 73 74 b0 b1 b2 b3 b4  b8 b9 ba bb bc bd c0 c1  c2 c3 c4 c8 c9 ca cb cc  cd ce cf e0 e1 e2 e3 e4  e9 f0 f1 f2 f3 f4 f5 f6  f7 f8 f9 fa fb
val 00 f3 10 00 00 00 80 00  00 00 0a 00 00 00 00 00  20 00 00 00 00 00 00 00  20 00 00 00 00 00 01 00  00 40 00 01 00 00 00 00  00 00 00 00 00 00 00 00  21 10 42 00 00 00 00 1c  00 00 00 00 00
def 00 f3 00 00 00 00 03 00  00 00 00 00 00 00 00 00  20 38 00 00 00 00 00 00  20 00 00 00 00 00 01 00  00 40 00 01 00 00 40 00  00 00 00 00 00 00 00 00  MM 00 00 00 00 00 00 00  00 00 00 00 00
LDN 0x0a (Consumer IR)
idx 30 60 61 70 f0
val 00 03 10 0b 06
def 00 03 10 0b 06

Change-Id: Ifb45d28005d78b2a99d8552b59154d11bdf44f6f
Signed-off-by: Андрей Павлов <7134956@gmail.com>
Reviewed-on: http://review.coreboot.org/2775
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2013-03-17 23:20:38 +01:00
Ronald G. Minnich c2c97231e3 Show the device tree.
This is a bit of a hack but it's very handy. It compiles in your static.c
and then shows what coreboot would see when it is run. It uses your static.c
and functions pulled from src/device/device_util.c.
I've already used it to debug problems with the snow device tree.

I'm waiting someone to tell me this is already written :-)

Change-Id: Ia8c8a5d08d8757bec49eaf70473efa701bc56581
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/2767
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-03-16 04:30:16 +01:00
Paul Menzel a46a712610 GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«
In the file `COPYING` in the coreboot repository and upstream [1]
just one space is used.

The following command was used to convert all files.

    $ git grep -l 'MA  02' | xargs sed -i 's/MA  02/MA 02/'

[1] http://www.gnu.org/licenses/gpl-2.0.txt

Change-Id: Ic956dab2820a9e2ccb7841cab66966ba168f305f
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2490
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2013-03-01 10:16:08 +01:00
Patrick Georgi 12781422d5 nvramtool: reduce memory mapping
Instead of trying to map the first megabyte, only map what is
required to read the tables.

Change-Id: I9139dbc8fd1dd768bef7ab85c27cd4c18e2931b3
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/2485
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2013-02-22 16:04:03 +01:00
Patrick Georgi 11a7db3b57 romcc: Don't fail on function prototypes
Instead, ignore them. One is as non-standard as the other
and ignoring is more convenient since we don't need to
guard prototypes with #ifndef __ROMCC_ all the time.

Change-Id: I7be93a2ed0966ba1a86f0294132a204e6c8bf24f
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/2424
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-02-19 11:01:05 +01:00
Hung-Te Lin 7b654a9702 cbfstool: Fix compile warnings caused by incorrect data types.
The "offset" in cbfs-mkpayload should be printed as type %lu
instead of %d as `gcc` rightfully warns about.

    gcc -g -Wall -D_7ZIP_ST -c -o /srv/filme/src/coreboot/util/cbfstool/cbfs-mkpayload.o cbfs-mkpayload.c
    cbfs-mkpayload.c: In function ‘parse_fv_to_payload’:
    cbfs-mkpayload.c:284:3: warning: format ‘%d’ expects argument of type ‘int’, but argument 3 has type ‘long unsigned int’ [-Wformat]
    cbfs-mkpayload.c:296:3: warning: format ‘%d’ expects argument of type ‘int’, but argument 3 has type ‘long unsigned int’ [-Wformat]

This warning was introduced in the following commit.

    commit 4610247ef1
    Author: Patrick Georgi <patrick@georgi-clan.de>
    Date:   Sat Feb 9 13:26:19 2013 +0100

        cbfstool: Handle alignment in UEFI payloads

        Reviewed-on: http://review.coreboot.org/2334

Change-Id: I50c26a314723d45fcc6ff9ae2f08266cb7969a12
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2440
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
2013-02-18 12:28:43 +01:00
Paul Menzel 475d42a16c cbfstool: Add `-Werror` to make all warnings into errors
Ensure that no changes with warnings are committed. Although using
`-Werror` is debatable [1][2].

[1] http://blog.flameeyes.eu/2009/02/future-proof-your-code-dont-use-werror
[2] http://gcc.gnu.org/onlinedocs/gcc/Warning-Options.html

Change-Id: I402f2d82dd4087d8a575b0a85305a02ef04bb537
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2441
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-02-18 12:10:44 +01:00
Stefan Reinauer 0aa37c488b sconfig: rename lapic_cluster -> cpu_cluster
The name lapic_cluster is a bit misleading, since the construct is not local
APIC specific by concept. As implementations and hardware change, be more
generic about our naming. This will allow us to support non-x86 systems without
adding new keywords.

Change-Id: Icd7f5fcf6f54d242eabb5e14ee151eec8d6cceb1
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2377
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-14 07:07:20 +01:00
Stefan Reinauer 4aff4458f5 sconfig: rename pci_domain -> domain
The name pci_domain was a bit misleading, since the construct is only
PCI specific in a particular (northbridge/cpu) implementation, but not
by concept. As implementations and hardware change, be more generic
about our naming. This will allow us to support non-PCI systems without
adding new keywords.

Change-Id: Ide885a1d5e15d37560c79b936a39252150560e85
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2376
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-14 02:00:10 +01:00
Hung-Te Lin ebae438bf2 crossgcc: Support hosts using non-GNU make as default make.
On hosts using non-GNU make as default make program (ex, FreeBSD's default is
BSD make and having GNU make as "gmake"), building acpica will fail. We should
use the correct path of make $(MAKE).

Verified to build on FreeBSD 9.0 with gcc 4.7 from ports. Note, the shipped gcc
in FreeBSD 9.0 is 4.2.1 and needs more patches to remove -Wbad-function-case and
-Wempty-body. That should be fixed in a future patch.

Change-Id: Iacbf5a05e84a8a53d9d3e783a10131de603282c9
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2333
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-02-11 14:34:17 +01:00
Patrick Georgi 4610247ef1 cbfstool: Handle alignment in UEFI payloads
Tiano for X64 is much cleaner to start up when using higher alignments in
firmware volumes. These are implemented using padding files and sections
that cbfstool knew nothing about. Skip these.

Change-Id: Ibc433070ae6f822d00af2f187018ed8b358e2018
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/2334
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-09 20:58:22 +01:00
Hung-Te Lin 408aefd176 cbfstool: Fix crash on image without bootblock in end of ROM.
On platforms with CBFS data filling end of ROM image without bootblock in the
end (ex, ARM), calculation of "next valid entry" may exceed ROM image buffer in
memory and raise segmentation fault when we try to compare its magic value.

To fix this, always check if the entry address is inside ROM image buffer.

Verified to build and boot successfully on qemu/x86 and armv7/snow.

Change-Id: I117d6767a5403be636eea2b23be1dcf2e1c88839
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2330
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-02-09 06:30:10 +01:00
Zheng Bao 30b895f7e2 crossgcc: Save the script itself when cross build is over.
In case that the new toolchains don't work well, we can trace back
and reproduce the old tools by checking the xgcc folder. It is useful
when my team members need to get my old toolchains on their own host
machines.

Change-Id: I54e4bc6afcfbbf622165af6eae27bbb6efc2e8cc
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2247
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-02-06 19:25:43 +01:00
Hung-Te Lin c5ff6487e6 armv7: Prevent CBFS data overlapping bootblock.
For arm/snow, current bootblock is larger than previously assigned CBFS offset
and will fail to boot. To prevent this happening again in future, cbfstool now
checks if CBFS will overlap bootblock.

A sample error message:
	E: Bootblock (0x0+0x71d4) overlap CBFS data (0x5000)
	E: Failed to create build/coreboot.pre1.tmp.

arm/snow offset is also enlarged and moved to Kconfig variable.

Change-Id: I4556aef27ff716556040312ae8ccb78078abc82d
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2295
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-02-06 10:53:19 +01:00
Stefan Reinauer e87641840f cbfstool: Add support for 64bit UEFI
Right now cbfstool only accepts firmware volumes with
a x86 SEC core and refuses an x86-64 SEC core because
some magic values and the extended PE header are
different. With this patch, both IA32/x64 images are
supported. (No check is done whether the mainboard
actually supports 64bit CPUs, so careful!)

This needs another patch to Tiano Core that switches
to long mode after jumping to the 64bit entry point.
Right now that code assumes we're already in 64bit code
and the machine crashes.

Change-Id: I1e55f1ce1a31682f182f58a9c791ad69b2a1c536
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2283
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-02-06 00:37:26 +01:00
Stefan Reinauer 543a682458 cbfstool: support parsing UEFI firmware volumes
This removes the hack implemented in http://review.coreboot.org/#/c/2280
(and should make using 64bit Tiano easier, but that's not yet supported)

Change-Id: Ie30129c4102dfbd41584177f39057b31f5a937fd
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2281
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-05 22:43:23 +01:00
Hung-Te Lin c13e4bf3e1 cbfstool: Use cbfs_image API for "add-*" (add-payload, add-stage, ...) commands.
add-payload, add-stage, and add-flat-binary are now all using cbfs_image API.
To test:
	cbfstool coreboot.rom add-stage -f FILE -n fallback/romstage -b 0xXXXX
	cbfstool coreboot.rom add-payload -f FILE -n fallback/pyload
And compare with old cbfstool.

Verified to boot on ARM(snow) and X86(qemu-i386).

Change-Id: If65cb495c476ef6f9d90c778531f0c3caf178281
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2220
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-05 22:27:20 +01:00
Hung-Te Lin 5f3eb26d85 cbfstool: Use cbfs_image api for "add" command.
The "add" command is compatible with all legacy usage. Also, to support
platforms without top-aligned address, all address-type params (-b, -H, -l) can
now be ROM offset (address < 0x8000000) or x86 top-aligned address (address >
0x80000000).

Example:
	cbfstool coreboot.rom add -f config -n config -t raw -b 0x2000
	cbfstool coreboot.rom add -f stage -n newstage -b 0xffffd1c0

Verified boot-able on both ARM(snow) and x86(QEMU) system.

Change-Id: I485e4e88b5e269494a4b138e0a83f793ffc5a084
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2216
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-05 22:27:13 +01:00
Hung-Te Lin f56c73f1e1 cbfstool: Use cbfs_image API for "create" command.
Usage Changes: To support platforms with different memory layout, "create" takes
two extra optional parameters:

    "-b": base address (or offset) for bootblock. When omitted, put bootblock in
          end of ROM (x86  style).
    "-H": header offset. When omitted, put header right before bootblock,
          and update a top-aligned virtual address reference in end of ROM.

  Example: (can be found in ARM MAkefile):
    cbfstool coreboot.rom create -m armv7 -s 4096K -B bootblock.bin \
             -a 64 -b 0x0000 -H 0x2040 -o 0x5000

Verified to boot on ARM (Snow) and X86 (QEMU).

Change-Id: Ida2a9e32f9a459787b577db5e6581550d9d7017b
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2214
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-05 22:27:08 +01:00
Hung-Te Lin 215d1d7c9b cbfstool: Use cbfs_image API for "locate" command.
To support platforms without top-aligned address mapping like ARM, "locate"
command now outputs platform independent ROM offset by default.  To retrieve x86
style top-aligned virtual address, add "-T".

To test:
	cbfstool coreboot.rom locate -f stage -n stage -a 0x100000 -T
	# Example output: 0xffffdc10

Change-Id: I474703c4197b36524b75407a91faab1194edc64d
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2213
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-05 22:27:03 +01:00
Hung-Te Lin 49fcd75564 cbfstool: Fix incorrect CBFS free space by old cbfstool.
Old cbfstool may produce CBFS image with calculation error in size of last empty
entry, and then corrupts master header data when you really use every bit in
last entry. This fix will correct free space size when you load ROM images with
cbfs_image_from_file.

Change-Id: I2ada319728ef69ab9296ae446c77d37e05d05fce
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2211
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-05 22:26:58 +01:00
Hung-Te Lin c03d9b0c43 cbfstool: Use cbfs_image API for "remove" command.
To delete a component (file) from existing CBFS ROM image.

To test:
	cbfstool coreboot.rom remove -n fallback/romstage
	# and compare with old cbfstool output result.

Change-Id: If39ef9be0b34d8e3df77afb6c9f944e02f08bc4e
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2208
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-05 22:26:53 +01:00
Hung-Te Lin 0f8af71f1a cbfstool: Use cbfs_image API for "extract" command.
Change the "extract" command to use cbfs_export_entry API. Nothing changed in
its usage.

To verify, run "cbfstool coreboot.rom extract -f blah -n blah" and check if the
raw type file is correctly extracted.

Change-Id: I1ed280d47a2224a9d1213709f6b459b403ce5055
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2207
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-05 22:25:20 +01:00
Hung-Te Lin 3bb035b095 cbfstool: Use cbfs_image API for "print" command.
Process CBFS ROM image by new cbfs_image API.
To verify, run "cbfstool coreboot.rom print -v" and compare with old cbfstool.

Change-Id: I3a5a9ef176596d825e6cdba28a8ad732f69f5600
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2206
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-05 22:25:13 +01:00
Hung-Te Lin eab2c81949 cbfstool: Add cbfs_image new CBFS image manipulation API.
Current cbfstool implementation is relying on global variables to pass processed
data, and the calculation of address is based on x86 architecture (ex, always
assuming 0x0000 as invalid address), not easy to be used on platforms without
top-aligned memory mapping. This CL is a first step to start a new cbfstool
without global variables, and to prevent assuming memory layout in x86 mode.

The first published APIs are for reading and writing existing CBFS ROM image
files (and to find file entries in a ROM file).

Read cbfs_image.h for detail usage of each API function.

Change-Id: I28c737c8f290e51332119188248ac9e28042024c
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2194
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-05 22:25:02 +01:00
Hung-Te Lin 3cfacbf196 cbfstool: Add buffer management API.
Many functions in cbfstool need to deal with a memory buffer - both location and
size. Right now it's made by different ways: for ROM image using global variable
(romsize, master_header); and in cbfs-* using return value for size and char**
to return memory location.

This may cause bugs like assuming incorrect return types, ex:
	uint32_t file_size = parse();	// which returns "-1" on error
	if (file_size <= 0) { ...
And the parse error will never be caught.

We can simplify this by introducing a buffer API, to change
	unsigned int do_something(char *input, size_t len, char **output, ...)
into
	int do_something(struct buffer *input, struct buffer *output, ...)

The buffer API will be used by further commits.

Change-Id: Iaddaeb109f08be6be84c6728d72c6a043b0e7a9f
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2205
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-05 22:24:45 +01:00
David Hendricks dada1259a2 crossgcc: add armv7a-eabi to list of working toolchains
Change-Id: Ibf221db4ca60d802b460d56f5fcca95ff49fc542
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2273
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-02-04 16:44:26 +01:00
Hung-Te Lin 5be66730cf cbfstool: Update example file.
The syntax of cbfstool has been changed for a while (using getopt). Updated
EXAMPLE file to show the right way to test cbfstool.

Change-Id: I5cb41b76712d8c2403fffc9fdad83c61fb2af98c
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2215
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2013-02-04 11:12:15 +01:00
Hung-Te Lin 332795cc59 cbfstool: Make endian detection functions to work without prior setup.
The 'host_bigendian' variable (and functions relying on it like ntohl/htonl)
requires host detection by calling static which_endian() first -- which may be
easily forgotten by developers.  It's now a public function in common.c and
doesn't need initialization anymore.

Change-Id: I13dabd1ad15d2d6657137d29138e0878040cb205
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2199
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-02-01 06:50:17 +01:00
Hung-Te Lin 05dccae75d cbfstool: move flat-binary parsing to cbfs-mkpayload.
The ELF parsing and payload building in add-flat-binary command should be
isolated just like mkpayload and mkstage.

Since the add-flat-binary command creates a payload in the end , move payload
processing to cbfs-mkpayload.c.

To test:
   cbfstool coreboot.rom add-flat-binary -f u-boot.bin -n fallback/payload \
	-l 0x100000 -e 0x100020

To verify, get output from "cbfstool coreboot.rom print -v":
   fallback/payload               0x73ccc0   payload      124920
   INFO:     code  (no compression, offset: 0x38, load: 0x1110000, length:..)

Change-Id: Ia7bd2e6160507c0a1e8e20bc1d08397ce9826e0d
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2197
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-02-01 06:06:41 +01:00
Hung-Te Lin 4d87d4e09b cbfstool: Add -v (verbose) output.
Add -v (verbose) to every command, and allow printing debug messages.

Revise logging and debugging functions (fprintf(stderr,...), dprintf...)
and verbose message printing with following macros:
	ERROR(xxx):	E: xxx
	WARN(xxx)	W: xxx
	LOG(xxx)	xxx
	INFO(...)	INFO: xxx  (only when runs with -v )
	DEBUG(...)	DEBUG: xxx (only when runs with more than one -v)

Example:
	cbfstool coreboot.rom print -v
	cbfstool coreboot.rom add -f file -n file -t raw -v -v

Normal output (especially for parsing) should use printf, not any of these
macros (see usage() and cbfs_locate(), cbfs_print_directory() for example).

Change-Id: I167617da1a6eea2b07075b0eb38e3c9d85ea75dc
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2196
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-02-01 05:54:24 +01:00
Ronald G. Minnich 21d0fc0d37 Add a clean target to the run firmware (runfw) Makefile
It's just good hygiene.

Change-Id: Ie7d4557c1d0dcf7fc015852c4c9b2eae29c4acfc
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/2232
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-01-30 21:22:04 +01:00
Hung-Te Lin 5a9f45c757 cbfstool: Prevent file name to be corrupted by basename().
Calling basename(3) may modify content. We should allocate another buffer to
prevent corrupting input buffer (full file path names).

Change-Id: Ib4827f887542596feef16e7829b00444220b9922
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2203
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-01-30 03:07:34 +01:00
Hung-Te Lin 657ea6a13d cbfstool: Change "locate" output to prefix "0x".
Currently "cbfstool locate" outputs a hex number without "0x" prefix.
This makes extra step (prefix 0x, and then generate another temp file) in build
process, and may be a problem when we want to allow changing its output format
(ex, using decimal). Adding the "0x" in cbfstool itself should be better.

Change-Id: I639bb8f192a756883c9c4b2d11af6bc166c7811d
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2201
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-01-29 06:08:31 +01:00
Hung-Te Lin 4505cebdad cbfstool: Remove unused header files.
cbfs-mk*.c does not work with real files / command line so header files with
file I/O and getopt can be removed.

Change-Id: I9d93152982fd4abdc98017c983dd240b81c965f5
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2200
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-01-29 04:14:43 +01:00
Hung-Te Lin d173962c6e cbfstool: Store global variables into struct.
cbfstool.c uses lots of global variables for command line options and all named
as "rom*". This may be confusing when other global variables also start with
rom, ex:	int size = rom_size + romsize;
(rom_size is from command line and romsize is the size of last loaded ROM image).

If we pack all rom_* into a struct it may be more clear, ex:
	do_something(param.cbfs_name, param.size, &romsize);

Change-Id: I5a298f4d67e712f90e998bcb70f2a68b8c0db6ac
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2195
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-01-28 19:59:40 +01:00
Anton Kochkov dd678a2e16 msrtool: Decoding for most of Intel Core 2 MSRs
Added bits/bitfields descriptions and decoding values
into intel_core2_later.c file, which describe
MSRs for Intel processors, based on later Core 2
architecture.

Change-Id: If577c8ed944afe34f86944cc03a780fba6b3dbba
Signed-off-by: Anton Kochkov <anton.kochkov@gmail.com>
Reviewed-on: http://review.coreboot.org/1171
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-01-28 18:36:33 +01:00
Olivier Langlois 70f39871a9 inteltool: Add support for Atom N455 (0x106c0) in CPU MSRs dump
reference for Atom MSRs are from
Intel 64 and IA-32 Architectures Software Developer's Manual
Volume 3C: System Programming Guide, Part 3
Order Number 326019, January 2013, Table 35-4, 35-5

Has been successfully tested on the targeted cpu.

Change-Id: If94279caeab27121c63ec43c258dc962c167ad51
Signed-off-by: Olivier Langlois <olivier@olivierlanglois.net>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2192
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-01-25 20:09:24 +01:00
Paul Menzel 5e732b8bf0 util/runfw/googlesnow.c: Remove trailing whitespace
$ git stripspace < util/runfw/googlesnow.c > /tmp/bla
    $ mv /tmp/bla util/runfw/googlesnow.c

Introduced with original commit.

    commit b867281a07
    Author: Ronald G. Minnich <rminnich@gmail.com>
    Date:   Wed Jan 16 11:59:34 2013 -0600

        Utility to run the snow bios in user mode

Change-Id: I146c07a918ef99e8ae3c0dd72cf28fae22312e43
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2183
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-22 19:04:29 +01:00
Ronald G. Minnich b867281a07 Utility to run the snow bios in user mode
This program lets you test run a snow coreboot image in user mode
on a properly equipped arm system (usually an ARM chromebook).
This is a real time saver as you don't have to flash each time.
We've found and fixed some nasty bugs with this one.

Anyway, the instructions on how to use this are in the binary.

Change-Id: Ib555ef51fd7e930905a2ee5cbfda1cc6f068278e
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/2159
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-01-19 18:35:31 +01:00
Stefan Reinauer db5b893569 Add more information to the cbfstool print
Show what's in a stage or payload. This will let people better understand
what's in a stage or payload.

Change-Id: If6d9a877b4aedd5cece76774e41f0daadb20c008
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/2176
Tested-by: build bot (Jenkins)
2013-01-19 02:19:14 +01:00
Stefan Reinauer 88c4939c1b make crossgcc: compile all required toolchains
The ARMv7 toolchain is now also needed for abuild (at least
if you want to be able to compile ARM images)

Change-Id: If1253203a2198f7dea632ba45540222ba3361932
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2147
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-01-17 01:56:53 +01:00
David Hendricks 0b23d47ffd armv7: Place reset vector + CBFS header + bootblock dynamically
This replaces hard-coded bootblock offsets using the new scheme.
The assembler will place the initial branch instruction after BL1,
skip 2 aligned chunks, and place the remaining bootblock code after.

It will also leave an anchor string, currently 0xdeadbeef which
cbfstool will find. Once found, cbfstool will place the master CBFS
header at the next aligned offset.

Here is how it looks:

             0x0000 |--------------|
                    |     BL1      |
             0x2000 |--------------|
                    |    branch    |
    0x2000 + align  |--------------|
                    |  CBFS header |
0x2000 + align * 2  |--------------|
                    |   bootblock  |
                    |--------------|

TODO: The option for alignment passed into cbfstool has always been
64. Can we set it to 16 instead?

Change-Id: Icbe817cbd8a37f11990aaf060aab77d2dc113cb1
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2148
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-17 01:06:43 +01:00
David Hendricks a12eaccc0b use a relative path for #line 3
The current path doesn't make much sense (unless you're Sven)
and may also incur a very long access penalty if /home happens
to be on a network mounted filesystem.

Change-Id: I8cfceb3cf237757ce9ea8f1953bce5a72691838a
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2153
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-01-16 09:58:00 +01:00
Stefan Reinauer d37ab454d4 Implement GCC code coverage analysis
In order to provide some insight on what code is executed during
coreboot's run time and how well our test scenarios work, this
adds code coverage support to coreboot's ram stage. This should
be easily adaptable for payloads, and maybe even romstage.

See http://gcc.gnu.org/onlinedocs/gcc/Gcov.html for
more information.

To instrument coreboot, select CONFIG_COVERAGE ("Code coverage
support") in Kconfig, and recompile coreboot. coreboot will then
store its code coverage information into CBMEM, if possible.
Then, run "cbmem -CV" as root on the target system running the
instrumented coreboot binary. This will create a whole bunch of
.gcda files that contain coverage information. Tar them up, copy
them to your build system machine, and untar them. Then you can
use your favorite coverage utility (gcov, lcov, ...) to visualize
code coverage.

For a sneak peak of what will expect you, please take a look
at http://www.coreboot.org/~stepan/coreboot-coverage/

Change-Id: Ib287d8309878a1f5c4be770c38b1bc0bb3aa6ec7
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2052
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Martin Roth <martin@se-eng.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-12 19:09:55 +01:00
David Hendricks 9ad1f56951 armv7: dynamically calculate the branch offset in cbfstool
This tidies up the ARMV7 case when creating cbfs:
- Calculate the offset using the size of the master header and offsets
  rather than using a magic constant.
- Re-order some assignments so things happen in a logical order.

Change-Id: Id9cdbc3389c8bb504fa99436c9771936cc4c1c23
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2125
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-10 18:01:14 +01:00
Stefan Reinauer c01990789f cbmem utility: Find actual CBMEM area
... without the need for a coreboot table entry for each of them.

Change-Id: I2917710fb9d00c4533d81331a362bf0c40a30353
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2117
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-08 20:40:26 +01:00
Stefan Reinauer d7144dcd57 cbmem utility: unify debug output
... and indent it to make output more comprehensible.

Change-Id: If321f3233b31be14b2723175b781e5dd60dd72b6
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2116
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-08 20:25:21 +01:00
zbao 062730d7cb cbfstool: index is replaced by strchr.
From index(3):
CONFORMING TO 4.3BSD; marked as LEGACY in POSIX.1-2001. POSIX.1-2008
removes the specifications of index() and rindex(), recommending
strchr(3) and strrchr(3) instead.

Change-Id: I3899b9ca9196dbbf2d147a38dacd7e742a3873fe
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/2112
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-01-08 04:00:30 +01:00
Stefan Reinauer 19f8756f00 cbmem utility: Add option to dump cbmem console
This adds an option to the cbmem utility to dump the cbmem console.
To keep the utility backwards compatible, specifying -c disables
printing of time stamps. To print both console and time stamps, run
the utility with -ct

Change-Id: Idd2dbf32c3c44f857c2f41e6c817c5ab13155d6f
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2114
Tested-by: build bot (Jenkins)
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
2013-01-08 01:24:11 +01:00
Stefan Reinauer 1665bb3896 cbmem utility: drop obsolete python based implementation
The first version of the cbmem utility was written in python,
but it had issues with 64bit systems and other little hick ups.
Since the C version has much fewer dependencies (no python needed
on target system), and it works in all corner cases, drop the
python version.

Change-Id: Ida3d6c9bb46f6d826f45538e4ceaa4fc1e771ff5
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2115
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: build bot (Jenkins)
2013-01-08 00:04:33 +01:00
Stefan Reinauer 9da7570b07 cbfstool: Fix warnings on OS X
Most hton and noth functions are already available
through the system headers we include on OS X, causing
the compiler to warn about duplicate definitions.

Change-Id: Id81852dfc028cf0c48155048c54d431436889c0e
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2106
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: build bot (Jenkins)
2013-01-04 23:29:37 +01:00
Stefan Reinauer 05cbce672e cbmem utility: Use mmap instead of fseek/fread
The kernel on Ubuntu 12.04LTS does not allow to use
fseek/fread to read the coreboot table at the end of
memory but will instead abort cbmem with a "Bad Address"
error.

Whether that is a security feature (some variation of
CONFIG_STRICT_DEVMEM) or a kernel bug is not  yet clear,
however using mmap works nicely.

Change-Id: I796b4cd2096fcdcc65c1361ba990cd467f13877e
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2097
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2013-01-04 06:37:59 +01:00
Hung-Te Lin 086842a13e Change "VERSION*" to more determined name "CBFS_HEADER_VERSION*".
The 'VERSION' in CBFS header file is confusing and may conflict when being used
in libpayload.

Change-Id: I24cce0cd73540e38d96f222df0a65414b16f6260
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2098
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-01-04 06:27:33 +01:00
David Hendricks 10c90d3126 update CFLAGS for armv7
This updates $CFLAGS used for armv7. Most of them were just added
to be consistent with what u-boot does. The important ones here
are -march=armv7-a and -mthumb (to allow 16-bit Thumb instructions).

I removed the hard float support because it got errors and
coreboot should never use floats anyway. We're still having trouble
with enums but I want to see how far it gets with this patch.

Also, put the flags in a form that makes diffs easier to read. It's
almost impossible otherwise.

Finally, move some flags to the architecture Makefile, and
rely on the fact that some are set for all architectures.

Depends-On: I6f730d017391f9ec4401cdfd34931c869df10a9e
Change-Id: Ia8a1ae22959933e06f7b996d1832cea40819f1ff
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/2075
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-01-04 00:48:49 +01:00
David Hendricks 454856b274 add user-specified offset when creating armv7 cbfs image
The "offs" provided on the command-line was not taken into account
when creating an image for armv7...

Change-Id: I1781bd636f60c00581f3bd1d54506f0f50bb8ad0
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2092
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-03 06:45:25 +01:00
Stefan Reinauer 1e0e55615f cbmem utility: support command line options
The tool could print much more useful information than
just time stamps, for example the cbmem console on systems
that don't have a kernel patched to support /sys/firmware/log.

Hence, add command line option parsing to make adding such
features easier in the future.

Change-Id: Ib2b2584970f8a4e4187da803fcc5a95469f23a6a
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2091
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: build bot (Jenkins)
2013-01-03 01:09:50 +01:00
David Hendricks ceb82da99f add a return type to test function used by xcompile
This fixes a minor bug that could cause testcc to fail unexpectedly.

Change-Id: Ib75d343104b6937682c05acf5232596aac83f105
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2068
Tested-by: build bot (Jenkins)
2012-12-21 20:18:31 +01:00