Commit Graph

30 Commits

Author SHA1 Message Date
Patrick Georgi 796fe068d3 Mark non-executable files non-executable
No need to mark Makefiles, C files or devicetrees
executable.

Change-Id: Ide3a0efc5b14f2cbd7e2a65c541b52491575bb78
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/7618
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-01 17:33:07 +01:00
Felix Held 1e3a22649a superio/nuvoton: Add support for Nuvoton NCT6776
Add support for both NCT6776D and NCT6776F devices.

Change-Id: If6686ea0a1cd6be537e286699b4ee8f88ba8ad7c
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: http://review.coreboot.org/5450
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-10-30 03:24:17 +01:00
Felix Held 14be0da303 superio/nuvoton: Add support for Nuvoton NCT5572D
Change-Id: I3b720cf879bf5326be885d2d3a3f9cfba0a27c7e
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: http://review.coreboot.org/6229
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Tested-by: build bot (Jenkins)
2014-10-30 03:23:31 +01:00
Edward O'Callaghan f21bdc3020 superio/*/superio.c: Don't hide pointer types behind typedefs
Hiding pointer types behind 'typedef's is usually not a great
idea at the best of times. Worse the typedef becomes an integer
at different stages in Coreboot. Let us refrain from doing this
at all.

Change-Id: Ia2ca8c98bb489daaa58f379433875864f6efabc8
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7136
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2014-10-27 12:51:00 +01:00
Edward O'Callaghan 85836c2215 superio: Use 'pnp_devfn_t' over 'device_t' in romstage component
The romstage component of Super I/O support is in fact written around
passing a lower and upper half packed integer. We currently have two
typedef's for this, 'device_t' and 'pnp_devfn_t'. We wish to make use of
'pnp_devfn_t' over 'device_t' as 'device_t' changes it's typedef in the
ramstage context and so is really a conflicting definition. This helps
solve problems down the road to having the 'real' 'device_t' definition
usable in romstage later.

This follows on from the rational given in:
c2956e7 device/pci_early.c: Mixes up variants of a typedefs to 'u32'

Change-Id: Ia9f238ebb944f9fe7b274621ee0c09a6de288a76
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6231
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins)
2014-10-27 12:50:33 +01:00
Edward O'Callaghan ff9e45e0b2 superio,Makefile.inc: Trivial - drop trailing blank lines at EOF
Change-Id: Ia452e22af9491c1681c859691eb4ac1868eeb938
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6282
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-07-17 02:19:14 +02:00
Dave Frodin 29179f0735 superio/nuvoton: Add chip support for setting IRQs to edge/level
Change-Id: I08b9eef9d6b0f120c17c3293f1f90b847742dc06
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/6064
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <gaumless@gmail.com>
2014-06-20 23:29:27 +02:00
Dave Frodin da2daef4b4 superio/nuvoton: Adds a function to route pins 41-48 to UARTD
Pins 41-48 default to being GPIs. This switches the internal
mux to connect them to UARTD.

Change-Id: I61393b8c35cbc664f6520f60eed09ba4bbede0dc
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/5963
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-20 23:28:59 +02:00
Dave Frodin 0240f9492b nuvoton/nct5104d: Update the #defined LDNs
Change-Id: I4e4bc09a8f8fabe68519a29dc421af82c76c9873
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/5944
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-06-09 23:33:22 +02:00
Felix Held da09d02c57 superio/nuvoton: factor out generic romstage components
The romstage of Nuvoton Super I/O chips (but not Nuvoton BMC chips)
is identical, so the early_serial.c file can be moved under
nuvoton/common.
The Nuvoton BMC chip WPCM450 is however left untouched.

Change-Id: I4663176c1003b24a49a9fe5f9ebd27a1963b5565
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: http://review.coreboot.org/5909
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2014-06-06 23:05:42 +02:00
Edward O'Callaghan f6f1ad6376 superio/*: Remove redundant chip.h header
Change-Id: If7141112ea67071ee05c52f455c3b2496aa7e17e
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5622
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13 12:14:00 +02:00
Edward O'Callaghan def00be41d src/drivers/pc80: Remove empty struct keyboard
This is a empty struct that has propagated through the superio's & ec's
but really does nothing. Time to get rid of it before it adds yet more
cruft. However, since this touches many superio's at once we do this in
stages by first changing the function type to be a pure procedure.

Change-Id: Ibc732e676a9d4f0269114acabc92b15771d27ef2
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5617
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2014-05-13 10:03:51 +02:00
Edward O'Callaghan 3c04917a00 superio/nuvoton/nct5104d: Avoid .c includes
Following the same reasoning as commit
d304331 superio/fintek/f81865f: Avoid .c includes
Clean up the early_serial #include directives in mainboard/romstage
code.

Change-Id: I14c438968bfed917977862efd8a393ec48cb04c9
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5446
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-06 06:08:37 +02:00
Kyösti Mälkki e2f4c2a72f uart8250: Drop includes in superio
Change-Id: If723896cc31da75dbb3a63d5dc959764e96fded1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5139
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-02-06 11:17:24 +01:00
Idwer Vollering 8c0cb8ae3b Correct file permissions.
Some files have incorrect/odd permissions,
correct them: remove unnecessary +x flags.

Change-Id: I784e6e599dfee88239f85bb58323aae9e40fb21c
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: http://review.coreboot.org/4490
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2013-12-07 00:39:09 +01:00
Nico Huber 1c81128dcd pnp: Add some default functions to enter/exit config state
Implement some common default functions to enter and exit the
configuration state. Also provide default pnp_mode_ops for common
enter()/exit() function pairs.

The following cocci ensures their use:
    @ mode_match @
    identifier enter, exit, ops;
    @@
     struct pnp_mode_ops ops = {
             .enter_conf_mode  = enter,
             .exit_conf_mode   = exit,
     };

    @ enter_match_8787 @
    identifier mode_match.enter, dev;
    @@
     enter(...)
     {
             outb(0x87, dev->path.pnp.port);
             outb(0x87, dev->path.pnp.port);
     }

    @ depends on enter_match_8787 @
    identifier mode_match.enter, mode_match.ops;
    @@
     struct pnp_mode_ops ops = {
    -        .enter_conf_mode  = enter,
    +        .enter_conf_mode  = pnp_enter_conf_mode_8787,
     };

    @ enter_match_55 @
    identifier mode_match.enter, dev;
    @@
     enter(...)
     {
             outb(0x55, dev->path.pnp.port);
     }

    @ depends on enter_match_55 @
    identifier mode_match.enter, mode_match.ops;
    @@
     struct pnp_mode_ops ops = {
    -        .enter_conf_mode  = enter,
    +        .enter_conf_mode  = pnp_enter_conf_mode_55,
     };

    @ depends on enter_match_8787 || enter_match_55 @
    identifier mode_match.enter;
    @@
    -enter(...) {...}

    @ exit_match_aa @
    identifier mode_match.exit, dev;
    @@
     exit(...)
     {
             outb(0xaa, dev->path.pnp.port);
     }

    @ depends on exit_match_aa @
    identifier mode_match.exit, mode_match.ops;
    @@
     struct pnp_mode_ops ops = {
    -        .exit_conf_mode   = exit,
    +        .exit_conf_mode   = pnp_exit_conf_mode_aa,
     };

    @ depends on exit_match_aa @
    identifier mode_match.exit;
    @@
    -exit(...) {...}

    @ depends on enter_match_8787 || enter_match_55 || exit_match_aa @
    @@
     #include <device/pnp.h>
    +#include <superio/conf_mode.h>

    @ mode_match_55_aa @
    identifier ops;
    @@
     struct pnp_mode_ops ops = {
             .enter_conf_mode  = pnp_enter_conf_mode_55,
             .exit_conf_mode   = pnp_exit_conf_mode_aa,
     };

    @@
    identifier mode_match_55_aa.ops;
    @@
    -struct pnp_mode_ops ops = {...};

    @@
    identifier mode_match_55_aa.ops, devops;
    @@
     struct device_operations devops = {
    -        .ops_pnp_mode     = &ops,
    +        .ops_pnp_mode     = &pnp_conf_mode_55_aa,
     };

    @ mode_match_8787_aa @
    identifier ops;
    @@
     struct pnp_mode_ops ops = {
             .enter_conf_mode  = pnp_enter_conf_mode_8787,
             .exit_conf_mode   = pnp_exit_conf_mode_aa,
     };

    @@
    identifier mode_match_8787_aa.ops;
    @@
    -struct pnp_mode_ops ops = {...};

    @@
    identifier mode_match_8787_aa.ops, devops;
    @@
     struct device_operations devops = {
    -        .ops_pnp_mode     = &ops,
    +        .ops_pnp_mode     = &pnp_conf_mode_8787_aa,
     };

Change-Id: I1480336b54523cc95210d99cf31c1a0b3a14b464
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: http://review.coreboot.org/3484
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2013-07-03 16:13:11 +02:00
Nico Huber 0b2ee93910 pnp: Remove now plain wrappers for default PnP functions
After removing the enter()/exit() functions for configuration mode,
most wrappers for our standard PnP functions just call the underlying
default implementation.

Remove those with a little cocci:
    @ op_match @
    identifier op;
    identifier pnp_op =~ "^pnp_((alt_|)enable|(set|enable)_resources)$";
    type device_t;
    identifier dev;
    @@
     static void op(device_t dev) { pnp_op(dev); }

    @@
    identifier op_match.op;
    @@
    -op(...) {...}

    /* Three rules to match the alignment, hmmp... */
    @@
    identifier op_match.op, op_match.pnp_op;
    identifier ops;
    @@
     struct device_operations ops = {
    -        .set_resources    = op,
    +        .set_resources    = pnp_op,
     };

    @@
    identifier op_match.op, op_match.pnp_op;
    identifier ops;
    @@
     struct device_operations ops = {
    -        .enable_resources = op,
    +        .enable_resources = pnp_op,
     };

    @@
    identifier op_match.op, op_match.pnp_op;
    identifier ops;
    @@
     struct device_operations ops = {
    -        .enable           = op,
    +        .enable           = pnp_op,
     };

Change-Id: Idc0e52c7e3600a01f3b6a4e17763557b271b481e
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: http://review.coreboot.org/3483
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-17 21:42:21 +02:00
Nico Huber 13dc976a52 pnp: Register implementations of enter/exit config state
Find all the (ramstage) implementations of enter()/exit() functions
for the configuration state, register and call them through the new
struct pnp_mode_ops. As our standard PnP functions are aware of the
pnp_mode_ops, it's not necessary to call enter()/exit() around them
anymore.

Patch generated with the cocci below. It's not perfect. The movement
of the enter()/exit() calls is somehow fragile. So I checked the
remaining calls for sense, and changed some empty lines. Also a
duplicate insertion of pnp_conf_mode_ops had to be removed.
    /* Try to find enter and exit functions by their outb() structure and
       their usage around calls to our standard pnp functions: */
    @ enter_match @
    identifier enter;
    identifier dev;
    type device_t;
    @@
     void enter(device_t dev)
     {
             <...
             outb(..., dev->path.pnp.port);
             ...>
     }

    @ exit_match @
    identifier exit;
    identifier dev;
    type device_t;
    @@
     void exit(device_t dev)
     {
             <...
             outb(..., dev->path.pnp.port);
             ...>
     }

    @ pnp_match @
    identifier op;
    identifier pnp_op =~ "^pnp_((alt_|)enable|(set|enable)_resources)$";
    identifier enter_match.enter, exit_match.exit;
    type device_t;
    identifier dev;
    @@
     void op(device_t dev)
     {
             ...
             enter(dev);
             ...
             pnp_op(dev);
             ...
             exit(dev);
             ...
     }

    /* Now add enter/exit to a pnp_mode_ops structure: */
    @ depends on pnp_match @
    identifier enter_match.enter;
    identifier exit_match.exit;
    identifier ops;
    @@
    +static const struct pnp_mode_ops pnp_conf_mode_ops = {
    +        .enter_conf_mode  = enter,
    +        .exit_conf_mode   = exit,
    +};
    +
     struct device_operations ops = {
             ...,
    +        .ops_pnp_mode     = &pnp_conf_mode_ops,
     };

    /* Match against the new structure as we change the code and the above
       matches might not work anymore: */
    @ mode_match @
    identifier enter, exit, ops;
    @@
     struct pnp_mode_ops ops = {
             .enter_conf_mode  = enter,
             .exit_conf_mode   = exit,
     };

    /* Replace enter()/enter() calls with new standard calls (e.g.
       pnp_enter_conf_mode()): */
    @@
    identifier mode_match.enter;
    expression e;
    @@
    -enter(e)
    +pnp_enter_conf_mode(e)

    @@
    identifier mode_match.exit;
    expression e;
    @@
    -exit(e)
    +pnp_exit_conf_mode(e)

    /* If there are calls to standard PnP functions, (re)move the
       enter()/exit() calls around them: */
    @@
    identifier pnp_op =~ "^pnp_((alt_|)enable|(set|enable)_resources)$";
    expression e;
    @@
    -pnp_enter_conf_mode(e);
     pnp_op(e);
    +pnp_enter_conf_mode(e);
     ...
     pnp_exit_conf_mode(e);

    @@
    identifier pnp_op =~ "^pnp_((alt_|)enable|(set|enable)_resources)$";
    expression e;
    @@
     pnp_enter_conf_mode(e);
     ...
    +pnp_exit_conf_mode(e);
     pnp_op(e);
    -pnp_exit_conf_mode(e);

    @@
    expression e;
    @@
    -pnp_enter_conf_mode(e);
    -pnp_exit_conf_mode(e);

Change-Id: I5c04b0c6a8f01a30bc25fe195797c02e75b6c276
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: http://review.coreboot.org/3482
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-17 21:42:06 +02:00
Nico Huber f898f7ba4d pnp: Provide alternative pnp_enable() implementation
The current default implementation of pnp_enable() only disables devices
- if set so in the devicetree - but does not enable them. Enablement takes
place in pnp_enable_resources(). Yet, many PnP chips implement their own
version of pnp_enable() which also enables devices if set in the devicetree.

It's arguable, if enabling those devices makes sense, before they get
resources assigned. Maybe we can't write the resource registers if not,
who knows? The least we can do is providing a common implementation for
this behavior, and get rid of some code duplication.

Used the following cocci:
    @@
    expression e;
    @@
    +pnp_alt_enable(e);
    -pnp_set_logical_device(e);
    (
    -pnp_set_enable(e, !!e->enabled);
    |
    -(e->enabled) ? pnp_set_enable(e, 1) : pnp_set_enable(e, 0);
    |
    -if (e->enabled) { pnp_set_enable(e, 1); }
    -else { pnp_set_enable(e, 0); }
    )

Change-Id: I8d695e8fcd3cf8b847b1aa99326b51a554700bc4
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: http://review.coreboot.org/3480
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-17 21:38:37 +02:00
Steven Sherk d9de6c4f0e Add new superio device
- Added in new support for Nuvoton NCT5104D LPC device.

Change-Id: I0af8c5e3e46fdd0a549475b30917897ae9e144a7
Signed-off-by: Steven Sherk <steven.sherk@se-eng.com>
Reviewed-on: http://review.coreboot.org/3072
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-12 00:37:34 +02:00
Stefan Reinauer 24d1d4b472 x86: Unify arch/io.h and arch/romcc_io.h
Here's the great news: From now on you don't have to worry about
hitting the right io.h include anymore. Just forget about romcc_io.h
and use io.h instead. This cleanup has a number of advantages, like
you don't have to guard device/ includes for SMM and pre RAM
anymore. This allows to get rid of a number of ifdefs and will
generally make the code more readable and understandable.

Potentially in the future some of the code in the io.h __PRE_RAM__
path should move to device.h or other device/ includes instead,
but that's another incremental change.

Change-Id: I356f06110e2e355e9a5b4b08c132591f36fec7d9
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2872
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-22 00:00:09 +01:00
Paul Menzel a46a712610 GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«
In the file `COPYING` in the coreboot repository and upstream [1]
just one space is used.

The following command was used to convert all files.

    $ git grep -l 'MA  02' | xargs sed -i 's/MA  02/MA 02/'

[1] http://www.gnu.org/licenses/gpl-2.0.txt

Change-Id: Ic956dab2820a9e2ccb7841cab66966ba168f305f
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2490
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2013-03-01 10:16:08 +01:00
Ronald G. Minnich 5079a0d32f Remove assembly coded log2 function
As we move to supporting other systems we need to get rid of assembly
where we can. The log2 function in src/lib is identical to the assembly
one (tested for all 32-bit signed integers :-) and takes about 10 ns
to run as opposed to 5ns for the non-portable assembly version. While speed
is good, I think we can spare the 15 ns or so we add to boot time
by using the C version only.

Change-Id: Icafa565eae282c85fa5fc01b3bd1f110cd9aaa91
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/1928
Tested-by: build bot (Jenkins)
2012-11-28 07:57:17 +01:00
Kyösti Mälkki fee73df07a Auto-declare chip_operations
The name is derived directly from the device path.

Change-Id: If2053d14f0e38a5ee0159b47a66d45ff3dff649a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1471
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-08-22 05:06:41 +02:00
Kerry Sheh 91be49b2d0 SIO: condition compile Nuvoton WPCM450 early_init.c
Compile Nuvoton WPCM450 early_init.c when CONFIG_SUPERIO_NUVOTON_WPCM450

Change-Id: Ie31b8ae6aa45d6f77efa2b61e215ba0987abf878
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/566
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-02-05 17:45:08 +01:00
Stefan Reinauer 5ff7c13e85 remove trailing whitespace
Change-Id: Ib91889a374515d36a2b12b53aeb12b6ea6e22732
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/364
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-11-01 19:07:45 +01:00
Alexandru Gagniuc 1a2b318625 Do not compile nuvoton superio for all board
The nuvoton WPCM450 code is compiled for all boards regardless of
whether or not they use it. Compile it only for boards needing it.

Change-Id: Iaf4cf2c479eb3238863f0771be799f02a8cc3421
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/129
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry She <shekairui@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-08-09 20:11:01 +02:00
efdesign98 00c8c4a316 Update AMD SR5650 and SB700
This updates the code for the AMD SR5650 and SB700 southbridges.
Among other things, it changes the romstage.c files by replacing a
.C file include with a pair of .H file includes.  The .C file is
now added to the romstage in the SB700 or SR5650 Makefile.inc.
file to the romstage and ramstage elements.  This particular change
affects all mainboards that use the SB700, and their changes are
include herein.  These mainboards are:
  Advansus a785e,
  AMD Mahogany, Mahogany-fam10, Tilapia-fam10,
  Asrock 939a785gmh,
  Asus m4a78-em, m4a785-m,
  Gigabyte ma785gm,
  Iei Kino-780am2-fam10
  Jetway pa78vm5
  Supermicro h8scm_fam10
The nuvoton/wpcm450 earlysetup interface is changed because the file
is no longer included in the mainboard romstage.c files.

Change-Id: I502c0b95a7b9e7bb5dd81d03902bbc2143257e33
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/107
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry She <shekairui@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-07-22 00:20:59 +02:00
Stefan Reinauer 13508b94cb Drop baud rate init to an arbitrary baud rate from Super I/O code.
See discussion at                                                                                                                                                               
http://www.mail-archive.com/coreboot@coreboot.org/msg29394.html                                                                                                                 
                                                                                                                                                                                
config->com1, devicetree.cb cleanup and init_uart8250() removal                                                                                                                 
will follow once this patch is comitted                                                                                                                                         
                                                                                                                                                                                
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>                                                                                                                   
Acked-by: Patrick Georgi <patrick@georgi-clan.de>                                                                                                                               

Updated to drop com1, com2.... from config structure and devicetree.cb



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6521 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-19 21:33:40 +00:00
Zheng Bao 8a281880a3 This is for board Supermicro H8scm. The code was done by existing chips and
superiotool.

WPCM450 is more like an EC. SuperIO is just a part of multi-features.

Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6461 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-27 16:33:09 +00:00