In preparation to allow devicetree overrides, it will be necessary to
use the same parsing functions to prepare two separate parse
trees. This change does the following things:
1. Updates root device and bus names to add base_ prefix.
2. Adds a function parse_devicetree that sets the root_parent and
linenum before calling yyparse().
3. Updates all uses of root_dev to refer to the next base_root_dev.
BUG=b:80081934
TEST=Verified that static.c generated for all boards built using
abuild is the same with and without this change.
Change-Id: I403a90c1ebf07ac66115ddfe137daf0980dc1a18
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27017
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This change gets rid of rescnt member in struct device since it is
redundant. "res" member can be used to determine if resource list is
present or not.
BUG=b:80081934
TEST=Verified that static.c generated with and without this CL is
exactly the same for all boards built using abuild.
Change-Id: I73a2361686ad1130716a7d29576f2d02b9ed33c1
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change re-factors the device structure in parse tree to be able
to support multidev devices just like non-multidev devices.
With this change, every device has a bus under it which is the parent
of all devices that fall on the bus. If there are duplicate entries in
the devicetree, then there will be multiple buses under the device and
each bus will have its own set of children.
The tree starts out with a root device which has a root bus under
it. This is a special device which is created statically and its
parent is its own root bus. When parsing the device tree file, devices
get added under the root bus as children.
Since this change re-organizes the way devicetree is represented, it
gets rid of latestchild and next_sibling pointers from struct
device. Also, the tree traversal to generate static.c is changed to
breadth-first walk instead of using the next_sibling.
BUG=b:80081934
TEST=Verified using abuild that all boards compile successfully.
Change-Id: Ic8c8a73a247e8e992ab6b1b2cc3131e06fa2e5a1
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26800
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change updates queue handling routines to be more generic so that
it can be used by more than just chip queue. Additionally, it provides
functions to dequeue element from head and peek head of a queue which
will be used in a follow-up commit.
BUG=b:80081934
TEST=Verified that abuild compiles successfully for all boards.
Change-Id: Ibd2de85b48c5d4e2790bf974ea3bb1bd387f66ee
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26802
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
During compilation sconfig/main.c gives an error regarding number of
arguments passed in fprintf.
BUG=none
BRANCH=none
TEST=check if compilation warning has been fixed
Change-Id: Ia769cc606a1e3f7e1188cd82235442493d37f664
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/26972
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change gets rid of unused 3rd parameter chips to the function
walk_device_tree.
BUG=b:80081934
TEST=Verified that abuild compiles successfully for all boards.
Change-Id: I255ff030562073b16310fc22a0981808bf2c062f
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26801
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Now that chips and devices are treated differently and the device tree
actually contains only devices, next and nextdev are exactly the same
for all devices in the tree. This change gets rid of nextdev pointer
and updates all uses of nextdev to next.
BUG=b:80081934
TEST=Verified that static.c generated for all boards built by abuild
is same with and without this change.
Change-Id: Ie50b3d769a78fe0beddba2e5551441b43cb212a2
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Now that chips and devices are treated differently in sconfig, this
change gets rid of struct header and add_header function which were
responsible for maintaining list of headers that need to be added to
static.c.
Instead, struct chip is re-factored into struct chip and
struct chip_instance, where chip is a list of unique chips required by
the mainboard whereas chip_instance is an instance of the chip. One
chip can have multiple instances dependending upon the devices in the
system. Also, struct device is updated to hold a pointer to chip
instance instead of the chip structure. This unique list of chips is
then used to add appropriate headers to static.c
BUG=b:80081934
TEST=Verified using abuild that all boards compile successfully.
Change-Id: I6fccdf7c361b4f55a831195adcda9b21932755aa
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26739
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a helper function s_alloc (sconfig alloc) that allocates memory
using calloc to get 0 initialized memory and checks to ensure it is
not NULL.
BUG=b:80081934
Change-Id: I56a70cf4865c50ed238226ace86e867bb1ec53db
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26738
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The only reason bus pointer existed in device structure in sconfig was
to allow a node to point to the parent which could be a chip and bus
which is the true parent in device tree hierarchy. Now that chip is no
longer a device, there is no need for separate bus and parent
pointers. This change gets rid of the redundant bus pointer in struct
device in sconfig.
BUG=b:80081934
TEST=Verified that static.c generated for all boards built by abuild
is same with and without this change.
Change-Id: I21f8fe1545a9ed53d66d6d4462df4a5d63023844
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26736
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change removes call to add_header from parsing functions and
moves it to a local function within main.c. It also adds a new
function emit_headers that is responsible for creating the linked list
for chip headers and emitting those to static.c
BUG=b:80081934
TEST=Verified that static.c for all files compiled using abuild is the
same with and without this change.
Change-Id: I24d526e81323115d3cc927242a4b9e49414afbe0
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26726
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change adds a new structure "struct chip" to identify elements of
type chip rather than re-using the structure for device. Until now
chip was treated as a device while generating the parse tree and then
device tree postprocessing skipped over all the chip entries in
children and sibling pointers of device nodes.
With this change, the device tree will only contain struct device in
the parsed tree. It helps by avoiding unnecessary pointers to chip
structure as children or next_sibling and then skipping those elements
in post processing. Every device can then hold a pointer to its chip.
When generating static.c, chip structure is emitted before device
structure to ensure that the device structure has chip within its
scope. Externally, the only visible change in static.c should be the
order in which chip/device elements are emitted i.e. previously all
chips under a particular device were emitted to static.c and then the
devices using those chips. Now, all chips are emitted before all the
devices in static.c
BUG=b:80081934
TEST=Verified that abuild is successful for all boards. Also, verified
that static.c generated for eve, kahlee, scarlet, asrock imb_a180 is
unchanged from before in node definitions.
Change-Id: I255092f527c8eecb144385eb681df20e54caf8f5
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26720
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit adds support for describing USB ports in devicetree.cb.
It allows a USB port location to be described in the tree with
configuration information, and ACPI code to be generated that
provides this information to the OS.
A new scan_usb_bus() is added that will scan bridges for devices so
a tree of ports and hubs can be created.
The device address is computed with a 'port type' and a 'port id'
which is flexible for SOC to handle depending on their specific USB
setup and allows USB2 and USB3 ports to be described separately.
For example a board may have devices on two ports, one with a USB2
device and one with a USB3 device, both of which are connected to an
xHCI controller with a root hub:
xHCI
|
RootHub
| |
USB2[0] USB3[2]
device pci 14.0 on
chip drivers/usb/acpi
register "name" = ""Root Hub""
device usb 0.0 on
chip drivers/usb/acpi
register "name" = ""USB 2.0 Port 0""
device usb 2.0 on end
end
chip drivers/usb/acpi
register "name" = ""USB 3.0 Port 2""
device usb 3.2 on end
end
end
end
end
Change-Id: I64e6eba503cdab49be393465b535e139a8c90ef4
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/26169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add support for a mmio resource in the devicetree to allow
memory-mapped IO addresses to be assigned to given values.
AMD platforms perform a significant amount of configuration through
these MMIO addresses, including I2C bus configuration.
BUG=b:72121803
Change-Id: I5608721c22c1b229f527815b5f17fff3a080c3c8
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The devicetree data structures have been available in more than just
ramstage and romstage. In order to provide clearer and consistent
semantics two new macros are provided:
1. DEVTREE_EARLY which is true when !ENV_RAMSTAGE
2. DEVTREE_CONST as a replacment for ROMSTAGE_CONST
The ROMSTAGE_CONST attribute is used in the source code to mark
the devicetree data structures as const in early stages even though
it's not just romstage. Therefore, rename the attribute to
DEVTREE_CONST as that's the actual usage. The only place where the
usage was not devicetree related is console_loglevel, but the same
name was used for consistency. Any stage that is not ramstage has
the const C attribute applied when DEVTREE_CONST is used.
Change-Id: Ibd51c2628dc8f68e0896974f7e4e7c8588d333ed
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/19333
Tested-by: build bot (Jenkins)
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Update sconfig lex and yacc files to add support for a new "SPI" device
type in the devicetree. SPI device takes only parameter i.e. chip select
number for the device on the SPI bus.
Re-generate the shipped files for sconfig using flex 2.6.0 and bison
3.0.4 (make CONFIG_SCONFIG_GENPARSER=1). Clean up local paths that leak
into generated files.
BUG=chrome-os-partner:59832
BRANCH=None
TEST=Compiles successfully.
Change-Id: If0831e25b3e4ed87827ad92356d7bf47b6387884
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18339
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: Idfd1bd8240413026b992ae1382a57bccf9d8ddb5
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/16082
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The mainboard chip.h files were (mostly) removed long ago.
Change-Id: I1d5a9381945427c96868fa17756e6ecabb1048b2
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/16080
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The command line parameters for these modes haven't worked in two
years and nobody noticed. They're obviously not getting used, so
remove them.
TEST=Generate static.c before and after the change, verify they're
identical.
Change-Id: I1d746fb53a2f232155f663f4debc447d53d4cf6b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/16079
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Instead of having directories and file names hardcoded, pass in the full
path and filename of both the input and output files.
In the makefile, create variables for these values, and use them in
places that previously had the names and paths written out.
Change-Id: Icb6f536547ce3193980ec5d60c786a29755c2813
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/16078
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Instead of forcing the hardcoded 'devicetree.cb' filename under the
mainboard directory, this allows mainboards to select a filename for
the devicetree file.
This allows mainboard variants that need to use different devicetree
files to live under the same directory.
Change-Id: I761e676ba5d5f70d1fb86656b528f63db169fcef
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12529
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Add support for a basic generic device in the devicetree to bind to a
device that does not have a specific bus, but may need to be described
in tables for the operating system. For instance some chips may have
various GPIO connections that need described but do not fall under any
other device.
In order to support this export the basic 'scan_static_bus()' that can
be used in a device_operations->scan_bus() method to scan for the generic
devices.
It has been possible to get a semi-generic device by using a fake PNP
device, but that isn't really appropriate for many devices.
Also Re-generate the shipped files for sconfig. Use flex 2.6.0 to avoid
everything being rewritten. Clean up the local paths that leak into the
generated configs.
Change-Id: If45a5b18825bdb2cf1e4ba4297ee426cbd1678e3
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/14789
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Use the second token for an i2c device entry in devicetree.cb to
indicate if it should use 10-bit addressing or 7-bit. The default if
not provided is to use 7-bit addressing, but it can be changed to
10-bit addressing with the ".1" suffix. For example:
chip drivers/i2c/generic
device i2c 3a.1 on end
end
Change-Id: I1d81a7e154fbc040def4d99ad07966fac242a472
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/14788
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
and re-generate _shipped files
Change-Id: I7a18824d64d3f6212e8566695376bf97e2196ee2
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14733
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
It's not deprecated if it's still in active use. The code layout is just
"funny" (and could warrant a chipset-side cleanup, but not today)
Change-Id: I5f7776ceba0134f20364a0c4a1ca51382e9877e2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/12429
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
It encourages users from writing to the FSF without giving an address.
Linux also prefers to drop that and their checkpatch.pl (that we
imported) looks out for that.
This is the result of util/scripts/no-fsf-addresses.sh with no further
editing.
Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/11888
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
As per discussion with lawyers[tm], it's not a good idea to
shorten the license header too much - not for legal reasons
but because there are tools that look for them, and giving
them a standard pattern simplifies things.
However, we got confirmation that we don't have to update
every file ever added to coreboot whenever the FSF gets a
new lease, but can drop the address instead.
util/kconfig is excluded because that's imported code that
we may want to synchronize every now and then.
$ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} +
$ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} +
$ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} +
$ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} +
$ find * -type f
-a \! -name \*.patch \
-a \! -name \*_shipped \
-a \! -name LICENSE_GPL \
-a \! -name LGPL.txt \
-a \! -name COPYING \
-a \! -name DISCLAIMER \
-exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} +
Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/9233
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
In order to enumerate CPU devices that are non-x86 (read: no lapic)
provide a generic 'cpu' device.
Change-Id: Ifeafdad8076935c3448784e6958117002509acbf
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/6824
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Running sconfig with four arguments where the third
does not match /-./ made sconfig use uninitialized
memory to build the output filename.
Change-Id: If4a147ff23771ca9b6a913605af60249be1ca3d0
Found-By: Coverity Scan
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/6483
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Cppcheck 1.65 report the style style issue below.
[main.c:434]: (style) Variable 'link' is assigned a value that is never used.
So remove the variable `link` as it is not needed.
Change-Id: Ib77b80b74a70985a76eaa3247c4a43832ef23a59
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/6488
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
When parsing a string to numbers, we don't need to copy it.
And when creating strings, we should eventually free them.
Change-Id: I9023fef6e97a1830bc68502be32e79879c1617d4
Found-By: Coverity Scan
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/6484
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Valid invocations are when -s|b|k outputfile is missing (argc == 3)
and when it is followed by the file name (argc == 5); it's an error
when "outputfile" is missing (argc == 4) or when there are more
arguments than expected (argc > 5).
Fixes "Uninitialized argument value" error found by scan-build from
clang version 3.2-11.
Change-Id: I8c489863323eb60cbaa5e82a80f5d78a6ca893c2
Signed-off-by: Daniele Forsi <dforsi@gmail.com>
Reviewed-on: http://review.coreboot.org/6378
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
It's useless and makes clang unhappy.
Change-Id: If256b99aebabd87df30a3a078c5804330b82989b
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/4713
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
There are no files to build left under AMD nortbridge/x/root_complex
directories. For some cases, even the Kconfig file was no longer sourced.
Remove all such references and empty files.
For devicetree.cb treat component paths with "/root_complex" in them valid
even when the directory does not exists. This is because AMD boards us this
dummy chip component as the root node in their devicetree.cb.
The generated devicetree file static.c remains unchanged.
Change-Id: I9278ebb50a83cebbf149b06afb5669899a8e4d0b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3434
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
The name lapic_cluster is a bit misleading, since the construct is not local
APIC specific by concept. As implementations and hardware change, be more
generic about our naming. This will allow us to support non-x86 systems without
adding new keywords.
Change-Id: Icd7f5fcf6f54d242eabb5e14ee151eec8d6cceb1
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2377
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
The name pci_domain was a bit misleading, since the construct is only
PCI specific in a particular (northbridge/cpu) implementation, but not
by concept. As implementations and hardware change, be more generic
about our naming. This will allow us to support non-PCI systems without
adding new keywords.
Change-Id: Ide885a1d5e15d37560c79b936a39252150560e85
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2376
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This provides weak empty declaration for mainboard_ops.
The struct chip_operations is not defined for __PRE_RAM__ so
the declaration is also moved upwards in the output.
Change-Id: I101f0b8b9f0a55fb51a7c6475d53cc588c84026d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1931
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
sconfig creates empty defaults for all chip_ops, which can be overridden
by drivers simply by providing a concrete implementation.
Change-Id: Ib37515f0b0747bdbf4da780d28690a1e719944b2
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1567
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Fix side-effects of name translation, treat original name as const.
Change-Id: Iae26be8cefe7db11eeb8e62fce6f3b8bc9c1f4ed
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/799
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Compose the name from Kconfig strings instead.
As the field is for debug print use only, a minor change in the output
should do no harm. The strings no longer include word "Mainboard".
Change-Id: Ifd24f408271eb5a5d1a08a317512ef00cb537ee2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1635
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Forcing this rule, chip_ops can be added in the static devicetree
regardless of the existence of the chip.h files.
Change-Id: Iec1c23484e85cab3f80a34f2b082088f38ac4de9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1472
Tested-by: build bot (Jenkins)
The name is derived directly from the device path.
Change-Id: If2053d14f0e38a5ee0159b47a66d45ff3dff649a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1471
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
Dropping mainboard's chip.h broke execution of the mainboard's enable
function and the addition of mainboard specific smbios tables.
The former was fixed by Kyosti in http://review.coreboot.org/1374
This patch fixes the breakage in static.c and also backs out a small
portion of Kyosti's patch (because it's not needed anymore)
Change-Id: I6fdea9cbb8c6041663bd36f68f1cae4b435c1f9b
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1421
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
We thought about two ways to do this change. The way we decided to try
was to
1. drop all ops from devices in romstage
2. constify all devices in romstage (make them read-only) so we can
compile static.c into romstage
3. the device tree "devices" can be used to read configuration from
the device tree (and nothing else, really)
4. the device tree devices are accessed through struct device * in
romstage only. device_t stays the typedef to int in romstage
5. Use the same static.c file in ramstage and romstage
We declare structs as follows:
ROMSTAGE_CONST struct bus dev_root_links[];
ROMSTAGE_CONST is const in romstage and empty in ramstage; This
forces all of the device tree into the text area.
So a struct looks like this:
static ROMSTAGE_CONST struct device _dev21 = {
#ifndef __PRE_RAM__
.ops = 0,
#endif
.bus = &_dev7_links[0],
.path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x1c,3)}}},
.enabled = 0,
.on_mainboard = 1,
.subsystem_vendor = 0x1ae0,
.subsystem_device = 0xc000,
.link_list = NULL,
.sibling = &_dev22,
#ifndef __PRE_RAM__
.chip_ops = &southbridge_intel_bd82x6x_ops,
#endif
.chip_info = &southbridge_intel_bd82x6x_info_10,
.next=&_dev22
};
Change-Id: I722454d8d3c40baf7df989f5a6891f6ba7db5727
Signed-off-by: Ronald G. Minnich <rminnich@chromium.org>
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1398
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
mainboard_config never worked right, at least not since we've had sconfig.
Hence, drop mainboard/<vendor>/<device>/chip.h and fix up the mainboards that
tried to use it anyways.
Change-Id: I7cd403ea188d8a9fd4c1ad15479fa88e02ab8e83
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1359
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
eliminate printf format warning.
Change-Id: I51f75a259d28c5de788f57c3d720b76ca638e330
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1248
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
This patch adds support for autogenerating the MPTABLE from
devicetree.cb. This is done by a write_smp_table() declared
weak in mpspec.c. If the mainboard doesn't provide it's own
function, this generic implementation is called.
Syntax in devicetree.cb:
ioapic_irq <APICID> <INTA|INTB|INTC|INTD> <INTPIN>
The ioapic_irq directive can be used in pci and pci_domain
devices. If there's no directive, the autogen code traverses
the tree back to the pci_domain and stops at the first device
which such a directive, and use that information to generate the
entry according to PCI IRQ routing rules.
Change-Id: I4df5b198e8430f939d477c14c798414e398a2027
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1138
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
clang complained about a missing include and wrong fprintf use.
Change-Id: Idc023b653e694147c624d5f8f9ed3b797c462e9f
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1067
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Mainboard and chip Kconfig files have several build options that
are redundant with information in devicetree.cb. This patch enables
sconfig to auto-generate equivalent configuration.
sconfig -s
Generates mainboard's static.c file, as before.
sconfig -b
This operation creates mainboard's bootblock init code. By default,
for every chip listed in mainboard/devicetree.cb, if there is a
chip/bootblock.c file, the init function is called.
A mainboard/bootblock.c file can be added to override default
behaviour.
sconfig -k
This operation generates select -options for component paths.
Change-Id: I808d44af552dbc5e0565d6a0f4f72c7be9f5740e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/472
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Furquan Shaikh