Add support for GPIO and SPD driver for pirika
BUG=b:184157747
BRANCH=dedede
TEST=emerge-dedede coreboot
Signed-off-by: Kirk Wang <kirk_wang@pegatron.corp-partner.google.com>
Change-Id: Id367a83b04aad62b7deabae99b3f91905a2fc46c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52923
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alex1 Kao <alex1_kao@pegatron.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This will change the names of the GPP bridges, but this ok since there
is no hand written ASL that references these names.
BUG=b:184766519
TEST=Boot picasso and dump ACPI
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ic09200156e8a37bd1a29ca95a17c8f8ae2b92bd3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54028
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Lowercase characters are not valid ACPI identifiers.
BUG=b:184766519
TEST=Boot picasso to OS and verify ACPI errors are no longer printed.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I75aca67f4607e97ced8ac00ac68e51c359aff944
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54027
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Cezanne and Picasso can now use the same driver.
BUG=b:184766519
TEST=Boot guybrush and dump ASL. Verified it didn't change.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ie4ede82935d6c69b323c1fdceaa61e306aa2820a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54026
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Now that Boot blobs have landed, need to uprev the qc_blobs.
Change-Id: I510de2d1e4334612c81f35a082dea92d445da0bb
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54037
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Soft straps, that can be configured by the vendor in the Intel Flash
Image Tool (FIT), can influence some pads' default state. It is possible
to select either a native function or GPIO mode for some pads on
non-server SoCs, while on server SoCs most pads can be controlled.
Thus, add a recommendation to always configure all pads for a board to
guarantee integrity between different board or vendor firmware revisions
where the soft straps might have been changed.
Change-Id: I33063a3f6a1c9cd5267d85f7da84deb554489a26
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52297
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Intel PDGs starting from Skylake / Sunrise Point state that, different
from the general recommendation in digital electronics, unconnected
GPIOs defaulting to GPIO mode do explicitly not require termination.
The reason for this is, that these GPIOs have the `GPIORXDIS` bit set,
which effectively disconnects the pad from the internal logic by
disabling the input buffer.
This bit - besides `GPIOTXDIS` - can also be set explicitly by using
the gpio macro `PAD_NC(pad, NONE)`.
In some cases, a pull resistor may be required due to bad board design
or when a vendor sets the RX/TX disable bits together with a pull
resistor and schematics are not available to check if the pad is really
unconnected or just unused. In this case the pull resistor should be
kept.
Pads defaulting to native functions usually don't need special handling.
However, when pads requiring external pull-ups are missing these due to
bad board design, they should be configured with `PAD_NC` to disconnect
them internally.
Rewrite the documentation to reflect these new findings.
Also clarify the comment in soc/intel gpio code accordingly.
Change-Id: Id01b197ebe8f2b8bb4ecf3d119ec2298b26d9be0
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52139
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update LTE USB port configuration at run-time after probing the firmware
config. By default the concerned USB port takes the Type-A port
configuration.
BUG=b:186380807
BRANCH=dedede
TEST=Build and boot to OS in metaknight
Change-Id: I5ad5a1670adef54075923cf912fb41a1ce776155
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52960
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Evan Green <evgreen@chromium.org>
Reviewed-by: Raymond Wong <wongraymond@google.com>
This callback is required to update the devicetree config at run-time
after probing the firmware config.
BUG=b:186380807
BRANCH=dedede
TEST=Build and boot to OS in metaknight.
Change-Id: I857211bfc4beb36ab225f3786c1707336a34aae9
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52887
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Evan Green <evgreen@chromium.org>
Reviewed-by: Raymond Wong <wongraymond@google.com>
Remove a blank line and correct the indentation of another line.
Change-Id: Id66f0a847720713c1d3445ac70a9e075228dfe88
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54017
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For consistency with other log messages, print bus numbers in decimal.
Change-Id: Ib08ae40fc67c5f8fafd760e8dbb729d6de34c2bb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54015
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This is still causing boot errors on zork:
coreboot-4.13-3659-g269e03d5c42f Fri May 7 22:03:11 UTC 2021 bootblock starting (log level: 8)...
Family_Model: 00820f01
PSP boot mode: Development
Silicon level: Pre-Production
Set power off after power failure.
PMxC0 STATUS: 0x800 BIT11
I2C bus 3 version 0x3132322a
DW I2C bus 3 at 0xfedc5000 (400 KHz)
FMAP: area COREBOOT found @ 875000 (7909376 bytes)
ASSERTION ERROR: file 'src/commonlib/bsd/cbfs_mcache.c', line 106
BUG=b:177323348
TEST=Boot ezkinil to OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I68b4b73670e750207414f0d85ff96f21481be8ce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53933
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Building the cbnt-prov tool requires godeps which does not work if
offline. Therefore, add an option to provide this binary via Kconfig.
It's the responsibility of the user to use a compatible binary then.
Change-Id: I06ff4ee01bf58cae45648ddb8a30a30b9a7e027a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51982
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
eint event mask register is used to mask eint wakeup source.
All wakeup sources are masked by default. Since most MediaTek SoCs do
not have this design, we can't modify the kernel eint upstream driver to
solve the issue 'Can't wake using power button (cros_ec) or touchpad'.
So we add a driver here to unmask all wakeup sources.
Change-Id: I703d87e3dc49cf4e0b7ff0c75a6ea80245dd73d3
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54007
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
UFS reference clock (refclk) is enabled by default, which will cause
the UFSHCI to hold the SPM signal and lead to suspend failure. Since
UFS kernel driver is not built-in, disable refclk in coreboot stage.
Change UFSHCI base register to 0x11270000.
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Change-Id: I1386e59f802a9e3c938a7e8dbeea547fbcb02709
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54011
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Fixes compilation on FreeBSD CURRENT, and possibly other releases.
The compiler, clang, complained about:
util/cbfstool/cbfstool.c:181:40: error: implicit declaration of function 'memmem' is invalid in C99 [-Werror,-Wimplicit-function-declaration]
util/cbfstool/cbfstool.c:181:31: error: incompatible integer to pointer conversion initializing 'struct metadata_hash_anchor *' with an expression of type 'int' [-Werror,-Wint-conversion]
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Change-Id: I45c02a21709160df44fc8da329f6c4a9bad24478
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53996
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fix booting issues on google/kahlee introduced by CB:51723.
Update use inital apic id in smm_stub.S to support xapic mode error.
Check more bits(LAPIC_BASE_MSR BIT10 and BIT11) for x2apic mode.
TEST=Boot to OS and check apicid, debug log for CPUIDs
cpuid_ebx(1), cpuid_ext(0xb, 0), cpuid_edx(0xb) etc
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Ia28f60a077182c3753f6ba9fbdd141f951d39b37
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52696
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
No board defines this macro. In preparation to drop OptionsIds.h files
from mainboards, remove commented-out references to `IDS_DEBUG_PORT`.
Change-Id: I67a10d863aeea9e1b91c38aa02d19106b7b97659
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53981
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
This macro is not used anywhere in AGESA. Remove all references.
Change-Id: Ibc2876a5a8419ec4fa5a793bb996f5c14d989bac
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53980
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
This macro is not used anywhere in AGESA. Remove all references.
Change-Id: I9cd9fa0dc25b1143f8b4c1f20beffba638437398
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53979
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
This macro is not used anywhere in AGESA. Remove all references.
Change-Id: Icae0ecae77a20e1568440e3191a29db33b5581d8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53978
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
These global variables are not used anywhere. Drop them.
Change-Id: I3fe60b970153d913ae7b005257e2b53647d6f343
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53977
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
soc_memory_init_params() does not only configure memory init parameters.
Despite its name, it also configures many other things. Therefore, merge
it into its caller function platform_fsp_memory_init_params_cb() to
prevent confusions.
Built clevo/l140cu with BUILD_TIMELESS=1. coreboot.rom remains the same.
Change-Id: Id3b6395ea5d5cb714a412c856d66d4a9bcbd9c12
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52491
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The values were copied from Foxconn D41S, which uses a different codec.
Adjust the codec config as per the settings dumped from vendor firmware.
Change-Id: If6a4c41b5d424adb23ebef402d2d2ad21269fe25
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53914
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Some changes:
- bg-prov got renamed to cbnt-prov
- cbfs support was added which means that providing IBB.Base/Size
separatly is not required anymore. Also fspt.bin gets added as an
IBB to secure the root of trust.
Change-Id: I20379e9723fa18e0ebfb0622c050524d4e6d2717
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52971
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This prepares for updating the intel-sec-tools submodule pointer. In
that submodule bg-prov got renamed to cbnt-prov as Intel Bootguard
uses different structures and will require a different tool.
Change-Id: I54a9f458e124d355d50b5edd8694dee39657bc0d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52970
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
We need to modify update CmdMirror and LpDdrDqDqsRetraining parameters
for ADLRVP board.
Allowing this parameters to be filled by devicetree will allow
flexibility to update values as per board designs.
Note that both UPDs are applicable for both DDR and Lpddr memory types.
BUG=None
BRANCH=None
TEST=Build works and UPD values have been filled correctly
Change-Id: I55b4b4aee46231c8c38e208c357b4376ecf6e9d9
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51027
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This reverts commit 6eced03b25.
This prevents zork from booting. We get the following error:
eSPI cmd0-cmd2: 00080009 00000000 00000000 data: 00000000.
Error: unexpected eSPI status register bits set (Status = 0x10000010)
Error: Slave GET_CONFIGURATION failed!
This isn't a pure revert. It is more of a fix that keeps the old
behavior.
BUG=b:187122344
TEST=Boot zork an no longer see eSPI error
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: If75a35d3994b0fd23945a450032d3cc81abeb136
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53932
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Cezanne must use cold resets. Change the warm reset request to always
set TOGGLE_ALL_PWR_GOOD. And, since the bit is sticky across power
cycles, set it early for good measure.
BUG=b:184281092
TEST=Majolica successfully resets using 0xcf9
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I7d4ca5665335b20100a5c802d12d79c0d0597ad9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52982
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Loading address and size for the user app has been changed with recent
PSP release.
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: If247cdf3413c6a10f4b3c92fb7e43dd1057865d9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Verify if transfer buffer is valid before progressing further to catch
invalid transfer buffer early.
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I4c470b156944b50e581dcdee47b196f46b0993f3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52965
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
AMDFW tool stores bios dir entry to bios1_entry in picasso but
bios3_entry in cezanne. Separate getting bios_dir_addr into a function
and implement it on each platforms.
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: Ie18ed7979a04319c074b9b251130d419dc7f22dc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52964
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move all platform-specific code except direct svc calls to chipset.c.
There will be differences between each platforms and we can't put
everything into svc.c.
TEST=build firmware for zork
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: Ie7a71d1632800072a17c26591e13e09e0269cf75
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52963
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Kirk Wang