Commit Graph

4276 Commits

Author SHA1 Message Date
Kangheui Won 275ade9539 Revert "amdfwtool: Use relative address for EFS gen2"
This reverts commit 0fc87e31e0.

Reason for revert: Breaks psp_verstage in guybrush

BUG=b:182477057

Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: Ie50cba4aaf31425ef8fee848c098a826f55c98da
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56131
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14 20:45:10 +00:00
Martin Roth 299558874c util/sconfig: Remove unused devicetree keywords ESPI & LPC
The ESPI & LPC keywords were added for the zork program, but it was
found that they weren't needed, so they were never used.

BUG=None
TEST=Build

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I3a78afc55477d62eac8056e2ca4bcdd3ab12ea47
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56197
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14 20:24:00 +00:00
Patrick Georgi 53ea1d44f0 util/kconfig: Uprev to Linux 5.13's kconfig
This was originally several commits that had to be squashed into one
because the intermediate states weren't able to build coreboot:

 - one to remove everything that wasn't our own code, leaving only
   regex.[ch], toada.c, description.md and Makefile.inc.
 - one to copy in Linux 5.13's scripts/kconfig and adapt Makefile.inc
   to make the original Makefile work again.
 - adapt abuild to use olddefconfig, simplifying matters.
 - apply patches in util/kconfig/patches.
 - Some more adaptations to the libpayload build system.

The patches are now in util/kconfig/patches/, reverse applying them
should lead to a util/kconfig/ tree that contains exactly the Linux
version + our own 5 files.

Change-Id: Ia0e8fe4e9022b278f34ab113a433ef4d45e5c355
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37152
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-07-13 20:28:14 +00:00
Arthur Heymans 8585eabc5d util/abuild: Fix overriding results with the default configuration
I a file in configs/* has no suffix, then the default configuration
will override the results of the build generated by the configfile
from configs/*. Fix this by adding a '_' to the buildname.

Change-Id: Ic47105fafca41f1905a6569943079623bec5405a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56041
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-07-13 20:20:15 +00:00
Zheng Bao ec5a5d7abf amdfwtool: Fix the NULL pointer in parameters
Change-Id: Ia2c65013d48fc1ad88d3caf6ef59824745c992de
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55550
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-08 18:52:00 +00:00
Zheng Bao 0fc87e31e0 amdfwtool: Use relative address for EFS gen2
The second generation EFS (offset 0x24[0]=0) uses
"binary relative" offsets and not "x86 physical
MMIO address" like gen1.

Chips like Cezanne can run in both cases, so no problem
comes up so far.

BUG=b:188754219
Test=Majolica (Cezanne)

Change-Id: I3a54f8ce5004915a7fa407dcd7d59a64d88aad0d
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-07-08 16:04:09 +00:00
Jan Tatje b7eec4a844 util/ifdtool: Add sklkbl to IFDv2 platforms
Currently ifdtool breaks the descriptor because it treats it as IFDv1.
This change adds it to the list of IFDv2 platforms.
Fixes boot for X11SSH-LN4F.

Fixes: 8c082e5fef ("util/ifdtool: Use -p platform name to detect IFDv2 platform and chipset")
Change-Id: I3f92b090e929336b5c18b442d1504ee1000f5594
Signed-off-by: Jan Tatje <jan@jnt.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56070
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-07 14:55:40 +00:00
Paul Menzel adface7ace util/board_status: Do not display grep message
Redirect stdout and stderr from grep to check for unknown timestamps,
when no timestamps are stored, which is already logged earlier.

    Failed to run "/root/coreboot/util/cbmem/cbmem -t", ignoring
    Getting remote dmesg
    grep: /tmp/coreboot_board_status.dXmbUIBP/emulation/qemu-i440fx/4.14-876-gdb28040ee1/2021-07-02T23_14_33Z/coreboot_timestamps.txt: No such file or directory

Change-Id: Ib5400d4bd17e957b4cc1bf75bbd332d60ad226f5
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56056
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-05 10:51:12 +00:00
Raul E Rangel db28040ee1 util/cbfstool: Allow setting alignment for payload
The -a flag was already implemented, it just wasn't exposed for the
add-payload command.

Setting the alignment of the payload will enable using the SPI DMA
controller to read the payload on AMD devices.

BUG=b:179699789
TEST=cbfstool foo.bin add-payload -a 64 ...

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I9f4aea5f0cbeaa8e761212041099b37f4718ac39
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55973
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-07-02 23:14:33 +00:00
Maxim Polyakov 8b35851e4c util/intelp2m: use import once for all included modules
There is no need to repeat "import" for each module in GoLang. Use
this keyword only once in each file for code cleanliness.

Change-Id: Ibb24fafd409b31b174946a39ca1f810d59b87e76
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55985
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-02 07:48:58 +00:00
Arthur Heymans 5bb7dc4e05 cbfstool/cbfs-mkstage.c: Change signature of parse_elf_to_xip_stage()
The dereferced parameter is never updated so passing a copy would work
too.

Change-Id: Ie36f64f55d4fc7034780116c28aaed65aa304d5e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55792
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-01 15:22:08 +00:00
Arthur Heymans c44ffc3084 security/intel/cbnt: Build test CBnT provisioning
This updates the intel-sec-tools submodule pointer to include a fake
acm binary to be included for buildtesting.

Change-Id: Id4a9e177f71306b8c5538a578da229a53d19487a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55609
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-28 04:13:54 +00:00
Nico Huber 6cd4d32039 cbfstool: Unset ${DEBUG} when making vboot hostlib
Vboot's Makefile is controlled by a ${DEBUG} environment variable.
As the name is very generic, it may be set by accident without any
intention to change the build. Having it set would break reproduci-
bility at least but it also turns out that the hostlib build would
be incomplete so that linking cbfstool fails due to internal calls
to vb2api_fail() which is not built in.

Change-Id: I2a9eb9a645c70451a320c455b8f24bfed197117c
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55764
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-06-26 10:07:34 +00:00
Johnny Lin e273a02d25 util/ifdtool: Add Xeon SP Lewisburg PCH platform support under IFDv2
After commit 8c082e5fe (util/ifdtool: Use -p platform name
to detect IFDv2 platform and chipset) w/o this xeon_sp/cpx would be
detected as IFDv1 and see build error.

Fixes: 8c082e5fe ("util/ifdtool: Use -p platform name to detect IFDv2 platform and chipset")
Change-Id: I444e7d35a85d9d42fc25d654e57386f38cf1ec85
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55745
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-26 10:05:53 +00:00
Nico Huber f22f408956 cbfstool: Make use of spurious null-termination
The null-termination of `filetypes` was added after the code was
written, obviously resulting in NULL dereferences. As some more
code has grown around the termination, it's hard to revert the
regression, so let's update the code that still used the array
length.

This fixes commit 7f5f9331d1 (util/cbfstool: fix buffer over-read)
which actually did fix something, but only one path while it broke
two others. We should be careful with fixes, they can always break
something else. Especially when a dumb tool triggered the patching
it seems likely that fewer people looked into related code.

Change-Id: If2ece1f5ad62952ed2e57769702e318ba5468f0c
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55763
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-06-25 04:28:36 +00:00
Patrick Georgi fd977f2f11 docker/coreboot.org-status: Update URL schemes to git repos
We moved from gitweb to cgit to gitiles and some of the URL schemes
were lost during the transitions. Update to the gitiles scheme so
board-status links work again.

Change-Id: Id2a840bf89fab172e0eab21e303ac0c4666b6751
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55594
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-06-22 04:23:18 +00:00
Subrata Banik 621ed4c06c util/ifdtool: Use ICH Strap Length (ISL) to identify APL chipset
Use offset FLMAP1 bit 24:31, called ISL (ICH Strap Lenth) to uniquely
identify the chipsets without any additional logic.

+---------+-----------+
| Chipset | PSL Value |
+---------+-----------+
| APL     | 0x13      |
+---------+-----------+

BUG=b:153888802
TEST=Able to dump FD contains correctly without specifying platform
quirks on APL (IFDv1) Platform.
> ifdtool -d coreboot.rom
PCH Revision: Apollo Lake: N3xxx, J3xxx

Change-Id: I02bcc6b1ca61c4ee59582f1b310ed0fba0ef1d9a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55617
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-20 06:02:00 +00:00
Subrata Banik 8c082e5fef util/ifdtool: Use -p platform name to detect IFDv2 platform and chipset
ifdtool uses `chipset` information to determine how certain straps
are decoded. This has been used for IFDv1 platforms as well as IFDv2
platforms (CHIPSET_500_600_SERIES_TIGER_ALDER_POINT).

IFDv2 platforms are all expected to pass in `-p` argument to identify
the platform. This platform information can be used to identify the
appropriate chipset information. For IFDv1 since `-p` argument is not
provided, ifdtool needs to use certain fields in the descriptor
(e.g. strap length) for unique identification of IFDv1 chipset.

This change updates `check_ifd_version()` function to:
1. Determine if IFD version is v1 or v2 based on `-p` argument.
If `-p` is not provided, it assumes that the platform is using IFDv1.
2. Based on IFD version, it calls either `ifd2_platform_to_chipset()`
or `ifd1_guess_chipset()` to determine chipset information.

This fixes the issue reported with CB:44815, where ifdtool is unable
to identify Alder Lake chipsets.

BUG=b:153888802
TEST=Able to dump FD contains correctly with platform quirks on Brya Platform.
> ifdtool -d coreboot.rom -p adl
PCH Revision: 500 series Tiger Point/ 600 series Alder Point

Change-Id: I25f69ce775454409974056d8326c02e29038ec8a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54305
Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-20 06:01:52 +00:00
Lean Sheng Tan 0faba3cf23 util/ifdtool: Add Elkhart Lake platform support under IFDv2
Add EHL under same family tree as TGL & JSL, also fix a
spacing inconsistency line.

Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: Ice09861c104c4e339fc83631c75089fa069b3931
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55357
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-18 04:40:17 +00:00
Benjamin Doron dfb6a0b1a3 util/intelp2m/fsp: Update some deprecated macros
Avoid using deprecated macros, where possible.

"GpioResetPwrGood" represents multiple valid updated values, depending
on the GPIO community and will be more difficult to update.
While Kabylake supports both sets of macros, it will cause build errors
on Coffeelake. In the GPD group, replace with "GpioDswReset."
Replace with "GpioResumeReset" in any GPP group.

Change-Id: Iab0bb09adad997bef3a2133c443471d4c634f423
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54974
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
2021-06-16 05:10:53 +00:00
Patrick Rudolph d023909b01 treewide: Disable R_AMD64_32S relocation support
This fixes a hard to debug hang that could occur in any stage, but in
the end it follows simple rules and is easy to fix.

In long mode the 32bit displacement addressing used on 'mov' and 'lea'
instructions is sign-extended. Those instructions can be found using
readelf on the stage and searching for relocation type R_X86_64_32S.

The sign extension is no issue when either running in protected mode or
the code module and thus the address is below 2GiB. If the address is
greater than 2GiB, as usually the case for code in TSEG, the higher
address bits [64:32] are all set to 1 and the effective address is
pointing to memory not paged. Accessing this memory will cause a page
fault, which isn't handled either.

To prevent such problems
- disable R_AMD64_32S relocations in rmodtool
- add comment explaining why it's not allowed
- use the pseudo op movabs, which doesn't use 32bit displacement addressing
- Print a useful error message if such a reloc is present in the code

Fixes a crash in TSEG and when in long mode seen on Intel Sandybridge.

Change-Id: Ia5f5a9cde7c325f67b12e3a8e9a76283cc3870a3
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55448
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-06-15 07:47:35 +00:00
Zheng Bao b035f58940 amdfwtool: Null check the pointers before using them
BUG=b:188769922

Reported-by: Coverity (CID:1438963)
Change-Id: Ia520e33c9e4065236478665fb0ef047fa47c9b81
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54999
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-14 05:52:40 +00:00
Wisley Chen 1852303682 util: Add DDR4 generic SPD for MT40A512M16TB-062E:R
Add SPD support for DDR4 memory part

BUG=b:190020997
TEST=none

Change-Id: I423131cb674e1e5ec699c7a28e5b5e6746247b2a
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55164
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-14 05:27:39 +00:00
Benjamin Doron d593bf7dfe util/intelp2m/fsp: Fix wrong register decoding for direction and interrupt
Using the wrong registers to build the fields led to incorrect
GPIO direction and interrupt trigger values. Change the calls
to fix the tables.

Change-Id: Icbeeb1fec6a863d0f86659c21924e15ae6765d47
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54973
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-12 21:21:16 +00:00
Zheng Bao addf340adf amdfwtool: Add missing license header
Change-Id: Id466e733d421602cfe0403ead95e417f0bb37eb4
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55159
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-06-09 05:17:25 +00:00
Zheng Bao 6be1ab67e2 amdfwtool: Move EFS related definitions to header file
EFS: Embedded Firmware Structure

These structs and macros are defined in PSP specs(#55758).
They are supposed to be used by all C sources.

Change-Id: I8c7ed9fa626b249b4aa48544316a941dc2625c60
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54942
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-06-09 05:17:18 +00:00
Julius Werner 218906df66 lint: checkpatch: Add SUSPICIOUS_CODE_INDENT test
This patch adds a new test to checkpatch that identifies cases where a
line after a conditional statement is incorrectly intended (possibly
indicating the mistake of forgetting to add braces), like this:

 if (a)
   b;
   c;

Unfortunately, it seems like checkpatch is partially unmaintained in
upstream Linux at the moment with maintainers either not responding at
all or not even willing to look at new patches [1]. Since detecting this
error class is important to coreboot, let's just carry this feature
locally for now.

[1] https://lkml.org/lkml/2021/4/15/1488

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I7bb90b56dfc7582271d2b82cb42a2c1df477054f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51838
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-06-08 22:10:07 +00:00
Zheng Bao 826f1c4610 amdfwtool: Print the entry type when dumping the firmwares
Change-Id: I07bf10e16a42a2b2ab784ee6ac4a4465b7412da6
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-06-07 17:11:43 +00:00
Zheng Bao e8e6043489 amdfwtool: Set the region_type as 0 for entry "BIOS level 2"
This region_type is actually not used. But we need to set it
explicitly as a known value.

We can refer "PSP spec #55758" or the link below:
   https://doc.coreboot.org/soc/amd/psp_integration.html

Change-Id: I8b914f9f02beecce707aba86248826cd9208e6c0
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54871
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-06-07 17:11:24 +00:00
Angel Pons 427e435b9b sb/intel/bd82x6x: Drop P_LVLx support in FADT
IO MWAIT redirection is not enabled, and C-states are reported using the
_CST ACPI object, which overrides the P_LVLx values.

Change-Id: I737bd58bcda3e7c5f6591e4c2309530ff035e2c8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55218
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-06-07 11:37:17 +00:00
Patrick Georgi 54f86a5a07 util/crossgcc: Avoid complex filename sets
bin/{foo,bar,baz} can fail if one of the files doesn't exist (depending
on the shell in use). Instead, cd into the directory and list the
files individually.

Change-Id: I042b2e45fded1b63551d8e65ead2a7bbbf96b1e7
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-06 13:08:37 +00:00
Patrick Georgi 5a76a53034 util/crossgcc: Update to clang 12
Change-Id: I38fc64fa872e2ecb0a10fb5378b3ce0d6a02443c
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55157
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-06 13:08:29 +00:00
Angel Pons 7014efd8cf Revert "util/vboot_lib: Add description.md"
This reverts commit 255b6f8646.

No longer needed after commit dd01e0131a
(Revert "util/lint: Add test for documentation in util dirs") has been
submitted. Plus, `util/vboot_lib/description.md` gets deleted whenever
one runs `make -C util/cbfstool clean`, which is rather annoying.

Change-Id: Ic93da096b6186d1d2af12243a74ec597694960c4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55162
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-04 12:35:40 +00:00
Angel Pons b85393742d util/cbfstool/linux_trampoline.h: Fix typo in comment
inlucde ---> include

Change-Id: I38987119ddabb08c457c9a7c8aecb8025fe2d9d3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55161
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-04 12:35:14 +00:00
Amanda Huang 4f870594aa util/spd_tools: Modify MT53E1G32D2NP-046 WT:B LPDDR4 config
CB:52586 ("util/spd_tools: Add MT53E1G32D2NP-046 WT:B LPDDR4 config")
incorrectly set ranks per channel to 1. However, MT53E1G32D2NP-046 WT:B
part has 2 channels per die and 2 physical dies. Each channel in each die shares DQ-DQS lines with the channel in other die and uses separate CS lines. Thus, number of ranks per channel is 2.

This change fixes the attribute ranksPerChannel for MT53E1G32D2NP-046 WT:B in LP4x global config by setting it to 2.

BUG=b:186616388

Change-Id: Iba87754ca04c2e026a9cbc8ef07412b467140cba
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55000
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-06-03 15:51:12 +00:00
Arthur Heymans 71971c9d7e cbfstool/linux_trampoline.S: Fix up the e820 table
The e820 type don't fully match the LB_TAG_MEMORY types, so change all
unknown types to e820 to '2', reserved memory.

TESTED with Linuxboot: e820 now shows the CBMEM region as reserved.

Change-Id: Ie0e41c66e002919e41590327afe0f543e0037369
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55074
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Rocky Phagura
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-02 07:47:01 +00:00
Felix Held 4fbab545b2 mainboards using soc/amd/picasso: use aliases for PCIe devices on bus 0
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia6199c70163d32467abe5ba5da55c73ff62ba10f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-06-01 20:37:15 +00:00
Felix Held c4eb45fa85 soc/amd/picasso: introduce and use chipset device tree
The chipset devicetree only has the essential PCIe devices enabled that
are needed for the SoC code to work. It also defines aliases for all
PCIe devices that can be used to reference the devices in the mainboard-
specific devicetrees and devicetree overrides. To make the change easier
to review that part will be done in a follow-up patch.

Despite missing in the PPR, device pci 18.7 exists on Picasso.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6b7c3fd32579a23539594672593a243172c161c7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-06-01 20:37:04 +00:00
Patrick Georgi 67d958b640 util/cbfstool/Makefile: Check out vboot before trying to use it
Change-Id: Ie2044d73b97663f7816964c4d908a46570aafdbc
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55072
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-06-01 10:24:01 +00:00
Arthur Heymans f2b7104308 util/cbfstool/fit.c: Fix getting the topswap table
There is a function to fetch the fit table at both the regular address
and the TS address. So reuse that function instead of attempting to
find the TS fit using some pointer aritmetics that is incorrect.

Change-Id: I9114f5439202ede7e01cd0fcbb1e3c4cdb8698b0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54680
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-27 14:38:34 +00:00
Iru Cai 6e3f048111 autoport: add a go.mod file
Go 1.16 needs this when running `go build` without GO111MODULE=off.

Change-Id: I9dcb134a68b7a726f1466a472a415c9558f60524
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51175
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-25 12:27:00 +00:00
Furquan Shaikh e59ad2e0da sconfig: Emit probe_list in all stages
`probe_list` member in `struct device` is present in all stages,
however, util/sconfig emits the list only when !DEVTREE_EARLY. This
change ensures that `probe_list` is emitted in all stages. In follow
up changes, this is used to get the correct device state using probe
conditions.

Change-Id: I61f7e909d48b616ac2127a5a9f36bdf4817a5165
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54829
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-05-24 16:55:14 +00:00
Dtrain Hsu c8b22418aa util/spd_tools/lp4x: Add new memory part to to global memory definition
This new definition is for MT53E512M32D1NP-046 WT:B used on Cret.

BUG=b:183057749
TEST=Generate SPDs

Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: Ica5df61d96d2c4cbe62a560a53bd3bd08eb121f9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54746
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-05-22 05:42:45 +00:00
Patrick Georgi b2b5781bb4 util/crossgcc: Update acpica to 20210331
Change-Id: Ic517a2b9c9b7122d2a65f67380d3ce368303d725
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54061
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2021-05-22 05:39:05 +00:00
Paul Fagerburg 0d2d9db143 util/mb/google: add support for brya
Add the file templates for creating a new variant of Brya.

BUG=b:177017247

Signed-off-by: Paul Fagerburg <pfagerburg@google.com>
Change-Id: If141d9b43ea5b845c1855f12e03e7d0cf535d2ec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54489
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-18 19:20:43 +00:00
Jakub Czapiga 9482807f1d util/testing/Makefile.inc: Add new line as help section separator
coreboot test targets help section was missing an empty line at the end.
This caused the next help section to be visually merged with it.
Empty line makes help output more aesthetic.

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I2f7202b0a636f62b60788215058611c9c86183de
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54367
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2021-05-18 10:09:59 +00:00
Nikolai Vyssotski 1965f650ea amdfwtool:cezanne: use correct bootloader binary for whitelist support
PSP whitelist bootloader (PSPBTLDR_WL_FILE) should be copied to type
0x73 entry and not type 0x01 (stage1 bootloader). We will also need to
change WHL BL filename (Type0x01->Type0x73) in a separate CL.

BUG=b:181135622

Change-Id: I71539a2065546547edc8a2621474cd1388b6434b
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53892
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-05-18 10:00:13 +00:00
Zheng Bao 806892a347 amdfwtool: Remove the misleading option characters
Change-Id: I8b0d53d5e5eb494741b7fac32029cf16cabe66d8
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2021-05-18 05:56:55 +00:00
Patrick Georgi f963a0f8e5 util/crossgcc: Update mpc to 1.2.1
Change-Id: Ic1422464d0a95c9cba1c417aaa05e4f1fe799d26
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54048
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-05-12 15:26:08 +00:00
Patrick Georgi 0afb90a73b util/crossgcc: Update gmp to 6.2.1
Change-Id: I871942f66e8fc496ebe523fdab539ea20950a202
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54047
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-05-12 15:26:01 +00:00