Commit Graph

41191 Commits

Author SHA1 Message Date
Angel Pons 437c2baac4 soc/intel/{skl,cnl}: Uniformize romstage.h whitespace
Change-Id: Ide0e33826dd237bcd13f00400bbc8a08255b4f62
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50945
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-25 10:06:34 +00:00
Angel Pons 57a2a3ba93 sb/intel/lynxpoint/acpi: Add missing USB ports
Broadwell has these devices, so add them to Lynx Point as well. This is
done in preparation to have Broadwell boards use Lynx Point ACPI code.

Change-Id: Id66f169070cdfe3a6d166ca18916d4ddaf4a5fea
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46959
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-25 10:05:06 +00:00
FrankChu acd65dddbd mb/google/dedede/var/galith: Update DPTF parameters
Update the first version DPTF parameters received from the thermal team.

BUG=b:177628854
TEST=cros build-ap --debug -b dedede --fw-name galtic

Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: Ia8e76d303db0add95e77693f15cad108fa92303b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49480
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-02-25 10:04:19 +00:00
Paul Menzel 4fb2328fed sb/amd/agesa/hudson/lpc: Remove space between function and signature
Change-Id: I4dd40014259ac3fd0223f7feb08620b87735f60b
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46638
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-25 10:04:01 +00:00
Paul Menzel 4df6b2673b sb/amd/agesa/hudson: Use comment style from style guide
Change-Id: I73d713ec3aa62ae207640ac7e5550e5407f5afa2
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46637
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-25 10:03:54 +00:00
Martin Roth 01b5dd60a8 util/lint: Check for windows line endings
The codebase currently has only unix line endings, so add a lint tool
to check for windows line endings.

BUG=None
TEST=Verify that line endings are caught both inside and outside a git
repo.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I6faf99a3184e4843640fb8965f8124de0bc52ce7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50851
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-25 10:03:32 +00:00
Martin Roth 0bb62907eb util/ectool: Update Makefile
- Add a help target
- Add the -Wshadow and -Werror options
- Add a way to disable -Werror

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I0d9fe5beb3a2e103a0bf4603712c3a5ed15f93be
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50850
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-25 10:03:17 +00:00
Martin Roth 2ae89398aa util/cbmem: Update Makefiles
- Add a help target
- Add the -Wshadow option
- Add a way to disable -Werror

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Icd4e5cf51d60254d274c6e5093285cd49ff1607a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-25 10:03:11 +00:00
Martin Roth 92f447aa92 util/cbfstool: Update Makefiles
- Add a distclean target
- Add a help target
- Add the -Wshadow option

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ie31d61bd0e28b1e228656dfa09b5ab1996868706
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50848
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-25 10:03:05 +00:00
Martin Roth 122011453d util/bucts: Clean up Makefile to match others
- Add a TARGET variable
- Enable optimization and additional warnings
- Add distclean target
- Add help target

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I8eb190abd1ab20da7dd1ae43ef0358ba91df000e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50847
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-25 10:03:00 +00:00
Martin Roth 90a43067dd util/bucts: Fix compiler complaints shown with -Wextra
This fixes the following 2 complaints:

bucts.c: In function ‘main’:
error: unused parameter ‘envp’
error: ‘bucts_state’ may be used uninitialized in this function.

The bucts_state wasn't real, but the compiler couldn't tell, so use
one variable to check for modifications instead of two.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Iff1aae3441ec366d272e88b6b6634980d61cb8ea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50846
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-25 10:02:53 +00:00
Yu-Ping Wu a84414a0fe mb/google/asurada: Enable RTC for event log
BUG=b:177399759
TEST=firmware_EventLog passed on asurada
BRANCH=none

Change-Id: I759f9030f525fa9e34ed542198a9dba8f25909f5
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49453
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-02-25 08:18:17 +00:00
Raul E Rangel 7e96518e63 soc/amd/cezanne/acpi/pci0.asl: Add LPC device
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Iadb8e77fb618e14cd9a6c0214bb3f5ae2dbc829d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50922
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-25 00:19:50 +00:00
Angel Pons 56823f53dc nb/intel/ironlake: Rewrite early QPI init
Rewrite early QPI initialisation to account for variables in the
register values. Trace replays did not capture these relationships.

Tested on out-of-tree HP 630, still boots.

Change-Id: I5d393e8222be286ab4d4dc074d85f721b07bbca4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49586
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-24 22:35:38 +00:00
Zheng Bao 91947604af soc/amd/cezanne: Add eSPI support
Change-Id: I7ed24e76df3c0542b04c0f072c1eaacceea4b71f
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49965
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-24 19:40:47 +00:00
Felix Held 0151b463c3 soc/amd/picasso/data_fabric: add missing data fabric device function 7
The device function is missing in the PCI device table in the PPR, but
is present in the hardware. Verified on a Mandolin board with PCO APU.
The corresponding ticket for the PPR is DESPCSOC-6667.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie91438bc905691d443ca4e7841549d1e3bca39ca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51041
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-24 19:37:12 +00:00
Felix Held 8240cc33ec soc/amd/cezanne/Makefile: move setting of PSP soft fuse bit 6
The PSP soft fuse bit 6 doesn't do what the comment above it says. See
NDA document #55758 for details.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic84cf6e1eee30af92cd700dc4bf78290143bf88b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51040
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-24 19:36:48 +00:00
Angel Pons 5d7c3a4f01 nb/intel/haswell/northbridge.c: Correct DPR handling
DPR size is in MiB, but the range boundaries are expressed in KiB. In
addition, DPR and TSEG use the same attributes, so unify both regions.
Also improve a comment about DPR, since `is special` is uninformative.

Change-Id: I4479483e17890b5a4c39165138fa1c5f8215bc84
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46987
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-24 11:43:07 +00:00
Angel Pons 3d35756d5a nb/intel/ironlake: Correct even more replay issues
The per-lane registers need to be modified in some cases. Also, MRC
does not have any delay after the loop, so remove it.

Tested on out-of-tree HP 630, still boots.

Change-Id: If02e171d2e999f4a5be5b43ecc5aafe8ca092951
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49585
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-24 11:42:29 +00:00
Angel Pons a8b82717ee nb/intel/ironlake: Relocate early QuickPath init
Given that the PCI devices/registers being accessed are about QuickPath,
this code must be part of QuickPath init. Move it with the other code.

Tested on out-of-tree HP 630, still boots.

Change-Id: I0854e7f0ce3070eed1adc0603f68a9d1552204d4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49584
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-24 11:42:24 +00:00
Angel Pons 0a8b1136e6 nb/intel/ironlake: Deduplicate programming 274/265 values
Transform the existing functions so that their functionality does not
overlap. Also, deduplicate printing these values in debug builds.

Tested on out-of-tree HP 630, still boots.

Change-Id: I3f50dcf56284c9648b116bc5aacc0adf2d863b5d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49583
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-24 11:42:14 +00:00
Angel Pons 7a87c9203e nb/intel/ironlake: Split out some QuickPath init code
The platform performs a CPU-only reset after initializing QPI (QuickPath
Interconnect) and before actually performing raminit. The state is saved
in the sticky scratchpad register at MCHBAR + 0x2ca8.

Relocate some QuickPath init to a separate file. All moved functions are
only used within QPI init code, and had to be relocated in one commit.

Tested on out-of-tree HP 630, still boots.

Change-Id: I48e3517285d8fd4b448add131cd8bfb80641e7ef
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49582
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-24 11:42:02 +00:00
Angel Pons a65ff854cd nb/intel/ironlake: Remove unnecessary declaration
Change-Id: I14c5671dfc611209e28f25f38b4e82d11aef88ab
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49580
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-24 11:41:56 +00:00
Angel Pons 266819104f nb/intel/ironlake: Fix more replay issues
Introduce the `get_bits_420` helper to avoid doing the same thing in
three different ways, and also correct a related register write.

Tested on out-of-tree HP 630, still boots.

Change-Id: Iec87f080714f0f07f5d43200ec01d6d3f31e8120
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49579
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-24 11:41:48 +00:00
Angel Pons c627dc9f8c nb/intel/ironlake: Fix some replay issues
Dummy reads followed by writes are actually read-modify-write operations
in disassembled binaries. Handling of the scratchpad register 0x2ca8 is
still nonsense, but that should be taken care of in a separate commit.

Tested on out-of-tree HP 630, still boots.

Change-Id: Ie33f42ecdb25febf3c82febeca13662232dea9ec
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45606
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-24 11:41:42 +00:00
Angel Pons c10f8b219e nb/intel/ironlake: Correct `set_4cf`
We only need to toggle one bit at a time. Introduce `rmw_500` to
simplify the code. The rank population doesn't seem to matter.

Tested on out-of-tree HP 630, still boots.

Change-Id: Ic1a680dae90889c84c9b2c536745e254475ff878
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49577
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-24 11:41:36 +00:00
Angel Pons b6d7a12d0f soc/intel/*/smmrelocate.c: Sync includes
Since Elkhart Lake and Alder Lake use alphabetical ordering, apply that
to the other platforms. Now there are only two versions of smmrelocate.c
across seven different platforms. They will be unified in follow-ups.

Change-Id: I5425323a6d4eecaa97916b6f2683dff57392157c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50935
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-24 11:40:47 +00:00
Angel Pons 11aeebec32 soc/intel/*/smmrelocate.c: Uniformize cosmetics
Use the same log message everywhere for consistency.

Change-Id: I9d2230bc92313269470839486f6644f16e837d7c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50934
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-24 11:35:32 +00:00
Angel Pons 1b8e65dee1 soc/intel/{skl,cnl}: Move smm_lock() to cpu.c
Looks like smmrelocate.c is nearly identical across multiple platforms.
This is done to be able to deduplicate smmrelocate.c in the follow-ups.

Change-Id: I2edc64c9eabc3815b12a2e3cffb03cba2228eea0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50933
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-24 11:35:05 +00:00
Angel Pons 9a1853a98c soc/intel/{cnl,icl}: Use matching type cast
Change-Id: Ie534a05f8d3945492ab5b817522486cdcd3c4cab
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50932
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-24 11:34:55 +00:00
Angel Pons f5d090d19a soc/intel/*/pmutil.c: Align cosmetics across platforms
Change-Id: I78d1b15deac2b80cc319dcfc5ab6bf419e2d61db
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50931
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-24 11:34:42 +00:00
Angel Pons a15a6045d2 soc/intel/skylake/pmutil.c: Define __SIMPLE_DEVICE__
Change-Id: I01035ad88dc6ba702fde2c58aa0093214a57e482
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50930
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-24 11:34:35 +00:00
Angel Pons df8462c36a soc/intel/skylake/pmutil: Correct soc_smi_sts_array()
The array was copied from Broadwell, which uses a different bit layout
for SMI_STS. Copy the array from Cannonlake instead, because Skylake
uses the same bit layout. This could be deduplicated in the future.

Change-Id: I1c4df727c549eac6f361754d6011bf302da64c5a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50929
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-24 11:34:20 +00:00
Patrick Rudolph 560eab7de5 mb/prodrive/hermes/hda_verb: Update verb table for latest board revision
Use different verb tables depending on board revision.

For board revision R03 and older use the existing verb tables.

For revisions newer than R03 use the new verb tables and also
apply the dynamic audio configuration recently added.

Also do the following:
* Use correct NID port mapping
* Fix verb count in ALC888 header
* Fix NID in Intel codec verbs

Change-Id: I24ea9149eb2cddb815ff82744a351c926a94aaef
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-24 11:32:41 +00:00
Varshit Pandya 4084702567 mb/intel/adlrvp_m: Add initial code for adl-m variant board
List of changes:
1. Add mainboard Kconfig to Kconfig.name files
2. Handle mainboard names in Kconfig file for adlrvp
3. Created a new devicetree.cb for Adlrvp-m.
3. Add override devicetree for ADL-M RVP.
4. Configure proper PCI and USB ports as per schematics for ADL-M

BUG=None
BRANCH=None
TEST=Able to build ADL-M RVP variants adlrvp_m and adlrvp_m_ext_ec.

Signed-0ff-by: Maulik Vaghela <maulik.v.vaghela@intel.com>
Signed-off-by: Varshit Pandya <varshit.b.pandya@intel.com>
Change-Id: I997b89ba87fb03dfa6a836caec51efd05baa2e8d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49871
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-24 11:30:11 +00:00
chenzanxi 7eac884bad mb/google/dedede/var/storo: Enable ELAN touchpad
Add ELAN touchpad into devicetree for storo.

BUG=b:177393444
BRANCH=dedede
TEST=built storo firmware and verified touchpad function

Change-Id: I95780d23b9ea5425d7762e850c25fd14d8a9caf4
Signed-off-by: chenzanxi <chenzanxi@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50979
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-24 11:29:49 +00:00
Martin Roth 8be0146528 toolchain.inc: Update and fix the test-toolchain target
Due to some change, the test-toolchain was no longer working, and was
always reporting that the toolchain is out of date.

This fixes the failure, and prints both the expected versions of Clang,
GCC, and IASL on failures.

Additional changes fix some indentation issues and skip trying to update
submodules when the test is run.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ia350f279c3fd3533523996327cc6b2304e0bead4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-02-24 11:29:39 +00:00
Tony Huang 9056fde023 mb/google/dedede/var/lantis: Configure IRQ as level triggered for ELAN TS
Follow vendor suggestion to configure IRQs as level triggered to prevent TS lost.

BUG=b:171440909
BRANCH=dedede
TEST=1. emerge-dedede coreboot chromeos-bootimage
     2. power on, suspend DUT to check TS is functional

Change-Id: I07a5cd5e2ac9caad9dbcca12e05bda7f08f42dce
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50964
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-02-24 11:29:30 +00:00
Tao Xia 096426b457 mb/google/dedede/var/sasukette: Adding LTE module support into devicetree and
associated GPIO configuartion

Adding LTE module support into devicetree and associated GPIO configuartion.

BUG=b:177385043
BRANCH=dedede
TEST=LTE function is OK

Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Change-Id: I4d91045176fd6413ac6a5eed70289a5668e5b94f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50985
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-02-24 11:29:20 +00:00
Tao Xia e747e8557e mb/google/dedede/var/sasukette: Adding audio codec and
speaker amplifier support into devicetree

Adding audio codec and speaker amplifier support into devicetree

BUG=b:177479444
BRANCH=dedede
TEST=audio function is OK

Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Change-Id: I90ff3a107278c711a085d04ae708e41f95d454ab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50984
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-02-24 11:29:09 +00:00
Tao Xia b7b41732c9 mb/google/dedede/var/sasukette: Adding Touchpad support into devicetree
Adding Touchpad support into devicetree.

BUG=b:177348842
BRANCH=dedede
TEST=touchpad function is OK

Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Change-Id: I7ecafb5b3e39ff2ed9e176531bd0939f830a6397
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50983
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-02-24 11:29:04 +00:00
Tao Xia e64513c767 mb/google/dedede/var/sasukette: Adding camera support in devicetree
and associated GPIO configuration

Adding camera support in devicetree and associated GPIO configuration.

BUG=b:177351873
BRANCH=dedede
TEST=camera function is OK

Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Change-Id: I539e969e180c8c71d4b54b50519d2e1ff25415f8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50982
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-02-24 11:28:59 +00:00
Aamir Bohra 4742f53770 soc/intel/{adl,jsl,ehl,tgl}: Remove ITSS polarity restore
Post boot SAI PCR access to ITSS polarity regsiter is locked.
Restore of ITSS polarity does not take effect anyways. Hence
removing the related programming.

Change-Id: I1adab45ee903b9d9c1d98a060143445c0cee0968
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51002
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-02-24 11:28:45 +00:00
Stanley Wu a04d37ccb3 mb/google/dedede/var/boten: Configure GPP_G7 as native
Configuring GPP_G7 as NC causes SD card detection issue.
Remove the GPP_G7 override and keep the baseboard
configuration as native function (SDIO_WP).

BUG=b:179733306
BRANCH=firmware-dedede-13606.B
TEST=Built and verified Kingston 64G SD card operation on boten

Change-Id: Ied319437de0e867ee9821d0151ff0c76834c4726
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50977
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-02-24 11:28:38 +00:00
Arthur Heymans b238caaaca device/device.c: Rename .disable to .vga_disable
This makes it clear what this function pointer is used for.

Change-Id: I2090e164edee513e05a9409d6c7d18c2cdeb8662
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51009
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-24 11:28:16 +00:00
Arthur Heymans 318c3ad674 nb/intel/haswell/pcie.c: remove disable NOP
The .disable function pointer is only referenced inside
set_vga_bridge_bits() and is used to unset VGA decoding on the
internal GFX device.

Change-Id: I0443a45522b2267e8e23b28e4e2033f25a7ccbf0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51008
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-24 11:28:06 +00:00
Arthur Heymans 522b39e757 nb/intel/sandybridge/pcie.c: remove disable NOP
The .disable function pointer is only referenced inside
set_vga_bridge_bits() and is used to unset VGA decoding on the
internal GFX device.

Change-Id: I6888b08ac11ba2431601fa179d063cee0bb93370
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51007
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-24 11:28:01 +00:00
Tim Wawrzynczak 291b58f06e soc/intel/alderlake: Add soc_get_xhci_usb_info() for elog support
Add MMIO offsets for USB2 and USB3 port status registers, for
both north (TCSS) and south (PCH) XHCI controllers; implement
soc_get_xhci_usb_info() to return the appropriate entries for
elog.

Change-Id: I5ceb73707a0af0542a07027fd5c873a9658b19d6
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-02-24 11:27:51 +00:00
Johnny Lin aed1952f05 doc/mb/ocp: Update DeltaLake for VPD variables used in LinuxBoot
u-root commits:
bmc_bootorder_override
https://github.com/u-root/u-root/pull/1902
systemboot_log_level:
https://github.com/u-root/u-root/pull/1922

Change-Id: I3da7291188ee06c50008aa3fc7142210215044d4
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50377
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2021-02-24 11:27:43 +00:00
Rocky Phagura afefa506d6 src/soc/intel/xeon_sp/cpx: Add enable IIO error masks
This adds functionality to mask certain IIO errors on the root complex as recommended by HW vendor.

Tested on DeltaLake mainboard. Boot to OS, verify IIO mask registers are programmed correctly.

Signed-off-by: Rocky Phagura <rphagura@fb.com>
Change-Id: I99f05928930bbf1f617c2d8ce31e8df2a6fd15e6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2021-02-24 11:27:10 +00:00