Needed so get_lid_switch will actually call the EC. Otherwise it
returns -1.
BUG=b:183524609
TEST=Depthcharge no longer halts complaining that coreboot didn't sample
the pin
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I4639b3713d726192e251dcffa14381dd92518fa2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51954
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
It looks like we are having SI issues on eSPI at 33 MHz. Switching to 16
MHz makes everything a lot more stable.
BUG=b:183524609
TEST=Boot to OS and run `ectool version` 1000 times and see no problems.
Before with 33 MHz there was an error every few cycles.
declare -i i=0; while ectool version; do i+=1; echo "$i"; sleep .11; done; echo "Finished: $i"
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I6ab515629703a157c1d1ac6adcf5cf379e80f8ee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51953
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
pci_rom_ssdt reloads the oprom from cbfs. It then places it into cbmem
and writes the offsets as the ROM ACPI node. The GOP driver modifies the
VBIOS so we don't want to reread from cbfs. When using GOP we also pass
the offsets with the VFCT table.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Iaf53e750564f1f0e115cd354790da62e672d74b7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51541
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
The coordtype parameter of acpigen_write_CSD_package expects a CSD_coord
enum value, but HW_ALL that got passed as parameter is a PSD_coord enum
value, so replace that with the correct CSD_HW_ALL enum value.
TEST=Timeless build results in identical binary for Mandolin.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Found-by: Paul Menzel <pmenzel@molgen.mpg.de>
Change-Id: I90b19345b8dc6d386b6acfa81c6c072dcd6981ca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51931
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This replays the changes made in commit 9b1f3cc6fb (cbfs: Pull
handling of the CBFS_CACHE mem_pool into CBFS core) for the latest
work on the BeagleBone port. I hope it's the right thing to do.
Fixes: Makes `master` compile again.
Change-Id: Ia51c66dbe425a662ea2a6b2527b2b6982f587891
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51943
Reviewed-by: Sam Lewis <sam.vr.lewis@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Causing the AOAC register access as part of system suspend (S3) causes
the suspend procedure to be stuck. Comment it for now to unblock
entering S3 and collecting the power numbers.
BUG=b:181766974
TEST=Build and boot to OS in Majolica. Enter S3 through "echo mem >
/sys/power/state".
Change-Id: Ie93bbe393b209b784b9a2257f3916b29d84b25d1
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51926
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The PCR algorithms used for vboot are frequently causing confusion (e.g.
see CB:35645) because depending on the circumstances sometimes a
(zero-extended) SHA1 value is interpreted as a SHA256, and sometimes a
SHA256 is interpreted as a SHA1. We can't really "fix" anything here
because the resulting digests are hardcoded in many generations of
Chromebooks, but we can document and isolate it better to reduce
confusion. This patch adds an explanatory comment and fixes both
algorithms and size passed into the lower-level TPM APIs to their actual
values (whereas it previously still relied on the TPM 1.2 TSS not
checking the algorithm type, and the TPM 2.0 TSS only using the size
value for the TCPA log and not the actual TPM operation).
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ib0b6ecb8c7e9a405ae966f1049158f1d3820f7e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51720
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andrey Pronin <apronin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
To generate a working BPM, boot policy manifest for Intel CBnT the
tool that generates it, requires ACPI base and PCH PWRM base as input.
Therefore make it a Kconfig symbol, that can be used in Makefile.inc.
Change-Id: I6f1f9b53e34114682bd3258753f2d5aada9a530d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51805
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This add an option to generate BPM using the 9elements bg-prov tool
using a json config file.
A template for the json config file can be obtained via
"bg-prov template".
Another option is to extract it from a working configuration:
"bg-prov read-config".
The option to just include a provided BPM binary is kept.
Change-Id: I38808ca56953b80bac36bd186932d6286a79bebe
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50411
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is useful if you have external infrastructure to sign KM.
Change-Id: If5e9306366230b75d97e4e1fb271bcd7615abd5f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51572
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Maps the useable RAM so that it can be used for booting a payload.
TEST: Booted a simple ELF payload (that just flashes LEDs) on the
Beaglebone Black.
Change-Id: I7f657c97e4753071c90ba8ca800a96108807e6b9
Signed-off-by: Sam Lewis <sam.vr.lewis@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44388
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Adds initialisation of 512MB of DDR memory on the BBB to the romstage.
The parameters for the DDR peripherals are taken from U-Boot.
TEST: Booted from romstage into ramstage. Also successfully managed to
run the "ram_check" in lib.h.
Change-Id: I692bfd913c8217a78d073d19c5344c9bb40722a8
Signed-off-by: Sam Lewis <sam.vr.lewis@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Adds code taken and (barely) adapted from U-Boot (release 2020.04,
commit 36fec02b1f90b92cf51ec531564f9284eae27ab4) for SDRAM initialization.
This should in theory work for other configurations than the Beaglebone
Black's DRAM configuration, but hasn't been tested.
Change-Id: Ib1bc2fa606f7010c8c789aa7a5c37cd41bc484b9
Signed-off-by: Sam Lewis <sam.vr.lewis@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44386
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Adds a "sd_media" boot_device to allow booting from the SD card. This
assumes that the generated "MLO" file is placed at a 128KB offset from
the start of the SD card, to allow for the MBR etc. to be at the start
of the SD card. Placing the MLO file here allows the AM335x boot ROM to
load and execute the bootblock stage as well, as 128KB is one of the
offsets the boot ROM checks when looking for the next stage to execute.
As part of this, a FMD for the Beaglebone has also been defined. It's
sized at 32M somewhat arbitrarily, as SD cards could allow for much
bigger payloads.
TEST: Beaglebone boots from bootblock into romstage. Romstage to
ramstage still doesn't work as it needs RAM initialization first.
Change-Id: I5f6901217fb974808e84aeb679af2f47eeae30fd
Signed-off-by: Sam Lewis <sam.vr.lewis@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44385
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Adds a driver for the am335x MMC peripheral. This has only been tested
with SD cards and probably needs some modification to use eMMC or MMC
cards.
It's also currently a little slow as it only supports reading a block at
a time.
Change-Id: I5c2b250782cddca17aa46cc8222b9aebef505fb2
Signed-off-by: Sam Lewis <sam.vr.lewis@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44384
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Fix the format warning below by using `PRIxPTR`, which is defined as
unsigned long.
src/soc/amd/common/block/smbus/smbus.c:33:56: error: format specifies type 'size_t' (aka 'unsigned int') but the argument has type 'uintptr_t' (aka 'unsigned long') [-Werror,-Wformat]
printk(BIOS_ERR, "Invalid SMBus or ASF base %#zx\n", mmio);
~~~~ ^~~~
%#lx
src/include/console/console.h:60:61: note: expanded from macro 'printk'
#define printk(LEVEL, fmt, args...) do_printk(LEVEL, fmt, ##args)
~~~ ^~~~
1 error generated.
Change-Id: I727c490d3097dcf36cdbcd4db2852cd49d11785f
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
At the end of the built, the line below is printed.
coreboot has been built without an the Microchip EC FW.
Remove *an*, as one article is enough.
Change-Id: I28b24f0f2dade17e30e16cc6d935976e331a7a97
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51842
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Move the parts of romstage.c that populate the UPD-M data structure to
the newly created fsp_m_params.c file. Since
platform_fsp_memory_init_params_cb gets called from the FSP driver and
not directly from car_stage_entry the two code parts in romstage.c
weren't directly interacting.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1f7f5879ac318372042ff703ebbe584ce1c32c91
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51835
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Move the parts of romstage.c that populate the UPD-M data structure to
the newly created fsp_m_params.c file. Since
platform_fsp_memory_init_params_cb gets called from the FSP driver and
not directly from car_stage_entry the two code parts in romstage.c
weren't directly interacting. Since soc/romstage.h only contains the
mainboard_updm_update function prototype, rename it to soc/fsp.h. This
patch also removes a few unused includes.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I52c21f13520dbdfab37587d17b3a8a3b1a780f36
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51834
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This file populates the UPD-S data structure that gets passed to the
FSP-S, so add that s part to make it a bit clearer which FSP parameters
it'll set up. This is also a preparation to add a fsp_m_params.c file in
the following patches.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I53786df0909055e66eac675b5580909b7960944f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51833
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Now that we have the DISABLE_KEYBOARD_RESET_PIN Kconfig option, select
it and remove the temporary workaround that was implemented in the
mainboard code in commit 39ef890336.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I634d11290dad8c93f10979f06243b1bf84737ae2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51785
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The KBRST_L pin will cause a reset when driven or pulled low even when
the GPIO mux is set to GPIO and not native function. So when you want to
use that pin as general purpose output the keyboard reset input
functionality needs to be disabled by selecting this option in the
board's Kconfig file to avoid causing a reset by writing a 0 to the
output level bit when it's configured as an output.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Furquan Shaikh <furquan@google.com>
Change-Id: I517ad551db9321f26afdba15d97ddb61be1f7d51
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51757
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
BUG=none
TEST=Build guybrush and verified with the PPR that the register and bits
are still the same
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I0619f84cf82cbb90ded9dfd58afa6acc9520fb8e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
TEST=Verified that this register and the defined bits exist in Cezanne,
Picasso, Stoneyridge, Bolton and SB800.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I32d1d577b05edab006981516a5aefd822e7b984a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51783
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reference code does a 32-bit write, and the values don't fit in 16 bits.
Change-Id: I1195c0637b5c215a45328ebae312cf620cd4c950
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51860
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reference code uses the `0x06` as an or-mask, which makes more sense.
Change-Id: I04e5262d9ab36ae866fccd90255e4a0f85328e85
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51859
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
While the macro value is the same, the DMIBAR register is not HTBONUS1.
Tested with BUILD_TIMELESS=1, Foxconn D41S remains identical.
Change-Id: I5025f115f5a55dc782092989f3d158802d1d9353
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51858
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Commit 56823f53dc (nb/intel/ironlake:
Rewrite early QPI init) rewrote this part, but the or-value is missing
one zero. Correct this magic value to align with MRC binaries.
Change-Id: Id7a6766b3f0fe415dea70cbc54afc30f808c8b16
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51857
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This was copied from Sandy Bridge and does not apply to Ironlake. These
offsets go past the MCHBAR window (MCHBAR size is 16 KiB on Ironlake).
Some of these writes would have collided with `DEFAULT_HECIBAR` if the
PCI resource had been reported as fixed. Remove the copy-pasted code.
Change-Id: I7688921ad7517cbd68a0c48262b29ecf7b4c396c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51856
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
While 64-bit writes seem to work properly, there could be unknown
side-effects in some cases, e.g. when running in long mode. Since
reference code uses two 32-bit writes, follow suit.
Change-Id: I48ed3d94c7865b3a3cce52108e99cf1656b57fc2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51855
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Thermal sensor2 defined in baseboard do not exist in boten.
With the format the DPTF policies are defined in boten, all the entries
from the baseboard are included and then the overrides applied.
This causes the non-existent DPTF devices to be exported in the ACPI table
and in turn OS reading invalid temperatures. Fix the format for
DPTF passive and critical policies.
BUG=None
BRANCH=dedede
TEST=Build and boot to OS in boten. Ensure that the DPTF entries look
correct in both static.c and SSDT tables i.e. passive and critical
policies for applicable devices only are present.
Change-Id: I63c781e0a439f1e7a3525fa7cf290fa9300cb066
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Ben Kao <ben.kao@intel.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Original Stamp_boost parameter will cause boost time over 2500sec(3960sec)
To pass balance performance and skin temperature test, decrease stamp_boost:
2500 -> 1640
BUG=b:182753072
TEST=1. emerge-zork coreboot
2. run balance performance and skin temperature test
Change-Id: I43c104ef912aafecadf9497f9ea20c8478c0e920
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51738
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add processor power limits control support to configure values for
alderlake soc based platforms.
BRANCH=None
BUG=None
TEST=Build and test on alderlake rvp board
Change-Id: I9dc37c7a43e6bd6f1ff5e8a97e22a0c7ac421802
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Updating from commit id 3a9d7cd:
2021-03-03 15:37:08 -0700 - (picasso: Update Dali SMU firmware)
to commit id dded82f:
2021-03-23 15:36:36 -0600 - (picasso: Update Dali SMU firmware)
This brings in 2 new commits.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: If71e52a2a3e50aeb8599798de7b49bc71ed26a04
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
On production boards, the touchpad interrupt line was moved
from GPP_B20 to GPP_B3. Fix the GPIO pad config and devicetree entry,
and update documentation to remove touchpad config issue.
Change-Id: Iaefeba8f78c567b67e7a416c27299bff574c23ab
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51797
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The gpio_get_index_in_group function returns the index of the GPIO
within its own group
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I7f6b312bd1d0388ef799cd127c88b17bad6a3886
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
REG_BASE_SIZE is supposed to represent the size of the REGBAR MMIO space
in KiB. It is currently sized at 4MiB, but this is incorrect, EDS Vol. 2
indicates REGBAR is 16MiB in size, therefore update the constant to
reflect this.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I0cfbe5b8bb07faa854efd4bf70640daa117f2bb2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51754
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This name isn't very meaningful, rename the config option to
ENABLE_TCSS_DISPLAY_DETECTION to make its meaning more obvious.
Change-Id: Ib21a3b5a37d25f93bd515f8c6e5ad39c9d2ea1c4
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51771
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Type-C subsystem ("TCSS") IP block is similar between TGL and
ADL. For pre-boot purposes, the limited amount of functionality required
appears to be common between the two, therefore move the functionality
to intel/common/block and rename from `early_tcss to `tcss` along the way.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I1c6bb9c7098691f0c828f9d5ab4bd522515ae966
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51753
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Raul E Rangel