Commit graph

110 commits

Author SHA1 Message Date
Justin TerAvest
22595f6e45 mb/google/octopus: Fix GPIO config for DRAM_IDs
The GPIO pad configurations for GPIO68-71 are incorrectly configured as
outputs. This change corrects them to be inputs.

BUG=b:74932341
TEST=None

Change-Id: I319f8a64d83c29ed150316c15a8d429cc7c024f3
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/25217
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-19 15:09:10 +00:00
Justin TerAvest
cc6953bb34 mb/google/octopus: Configure PCH_WP_OD early.
The GPIO for EEPROM write-protect should be configured early, before
romstage. This change configures that pad earlier. This pad is the same
on the existing Octopus schematics.

BUG=None
TEST=None

Change-Id: Idf296ba6aad75b890afabd6f7c7c51fbaf911214
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/25250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-19 14:24:04 +00:00
Furquan Shaikh
6bff3bf4be mb/google/octopus: Do not configure GPIO_149 as GPO
GPIO_149 is used as ESPI clock feedback and configuring it as a GPO
results in EC communication failure. This change removes the
configuration of GPIO_149 as GPO in ramstage so that it remains
configured for ESPI (as it was when AP came out of reset).

BUG=b:75348718

Change-Id: Ie4f21b12fae027cdba54ce147e6d1a88ee854792
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/25259
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-17 21:52:13 +00:00
Shamile Khan
cb9f55ec38 mb/google/octopus: Enable audio components.
Octopus uses MAX98357A speaker amplifier and DA7219 codec.
Add device tree entries and Kconfig settings for these
components.

BUG=b:73292699,b:73230879
BRANCH=None
TEST=Build coreboot for Octopus board.

Change-Id: I27b5113677a8bd44dbbae587e27616d9e0b90d7f
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://review.coreboot.org/25117
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-15 08:50:14 +00:00
Justin TerAvest
36c926d86c mb/google/octopus: Add yorp variant
This creates a yorp variant for octopus; nothing too interesting now,
just picks up values from the baseboard.

BUG=b:74443669,b:74067452
TEST=Build

Change-Id: I55af8f02d33138a3b6bab7860a665e3deb5595c2
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/25086
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-13 17:01:56 +00:00
Justin TerAvest
898e2b4399 mb/google/octopus: Fix lpddr4 skus
The current lpddr4 skus entries do not match the RAMID table in the
schematic. This commit updates that so they are consistent. Thankfully,
the values are the same as for glkrvp, so I just copied from there.

BUG=b:74392818
TEST=None

Change-Id: I2e63ea0b27ef58038e5a37949c31a808989c98c2
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/25063
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-12 16:12:15 +00:00
Shaunak Saha
cbedd8fd2a mb/google/octopus: Add gpio configs for communities
This patch configures the gpios for all the gpio communites.

Change-Id: Ibc16edd96f4ef6d55f3a99b195bf4920929b1578
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://review.coreboot.org/23799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-03-08 16:47:02 +00:00
Shamile Khan
c5f354b97b mb/google/octopus: Add device tree settings
Change-Id: Id45409a9561671237410dd2f8f0bbfe61ff33562
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://review.coreboot.org/23846
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-08 16:46:11 +00:00
Ravi Sarawadi
3c2310d2df mb/google/octopus: Add LPDDR4 memory init
Add LPDDR4 initialization support.

BUG=b:73136980
BRANCH=None
TEST=Build coreboot for Octopus board.

Change-Id: Ieffcfa2f9d075eb0be13562f1a0c7ee503b005d9
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-on: https://review.coreboot.org/23832
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-28 17:36:37 +00:00
Hannah Williams
5e83e8b130 mb/google/octopus: Add new board
Add octopus board using GLK soc. Copied base code from mainboard/intel/glkrvp.
TODO: Fix as per octopus schematic.

Change-Id: Ic8c25b3fafbfef31b8b3b802acb3bc53ee7146b6
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/23685
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-15 21:38:50 +00:00